aboutsummaryrefslogtreecommitdiff
path: root/hw/misc
diff options
context:
space:
mode:
Diffstat (limited to 'hw/misc')
-rw-r--r--hw/misc/mac_via.c87
-rw-r--r--hw/misc/macio/cuda.c8
-rw-r--r--hw/misc/macio/pmu.c40
-rw-r--r--hw/misc/mos6522.c226
-rw-r--r--hw/misc/trace-events4
5 files changed, 259 insertions, 106 deletions
diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c
index 71b74c3372..525e38ce93 100644
--- a/hw/misc/mac_via.c
+++ b/hw/misc/mac_via.c
@@ -325,10 +325,11 @@ static void via1_sixty_hz(void *opaque)
{
MOS6522Q800VIA1State *v1s = opaque;
MOS6522State *s = MOS6522(v1s);
- MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_60HZ_BIT);
- s->ifr |= VIA1_IRQ_60HZ;
- mdc->update_irq(s);
+ /* Negative edge trigger */
+ qemu_irq_lower(irq);
+ qemu_irq_raise(irq);
via1_sixty_hz_update(v1s);
}
@@ -337,44 +338,15 @@ static void via1_one_second(void *opaque)
{
MOS6522Q800VIA1State *v1s = opaque;
MOS6522State *s = MOS6522(v1s);
- MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA1_IRQ_ONE_SECOND_BIT);
- s->ifr |= VIA1_IRQ_ONE_SECOND;
- mdc->update_irq(s);
+ /* Negative edge trigger */
+ qemu_irq_lower(irq);
+ qemu_irq_raise(irq);
via1_one_second_update(v1s);
}
-static void via1_irq_request(void *opaque, int irq, int level)
-{
- MOS6522Q800VIA1State *v1s = opaque;
- MOS6522State *s = MOS6522(v1s);
- MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
-
- if (level) {
- s->ifr |= 1 << irq;
- } else {
- s->ifr &= ~(1 << irq);
- }
-
- mdc->update_irq(s);
-}
-
-static void via2_irq_request(void *opaque, int irq, int level)
-{
- MOS6522Q800VIA2State *v2s = opaque;
- MOS6522State *s = MOS6522(v2s);
- MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
-
- if (level) {
- s->ifr |= 1 << irq;
- } else {
- s->ifr &= ~(1 << irq);
- }
-
- mdc->update_irq(s);
-}
-
static void pram_update(MOS6522Q800VIA1State *v1s)
{
@@ -938,9 +910,26 @@ static uint64_t mos6522_q800_via2_read(void *opaque, hwaddr addr, unsigned size)
{
MOS6522Q800VIA2State *s = MOS6522_Q800_VIA2(opaque);
MOS6522State *ms = MOS6522(s);
+ uint64_t val;
addr = (addr >> 9) & 0xf;
- return mos6522_read(ms, addr, size);
+ val = mos6522_read(ms, addr, size);
+
+ switch (addr) {
+ case VIA_REG_IFR:
+ /*
+ * On a Q800 an emulated VIA2 is integrated into the onboard logic. The
+ * expectation of most OSs is that the DRQ bit is live, rather than
+ * latched as it would be on a real VIA so do the same here.
+ *
+ * Note: DRQ is negative edge triggered
+ */
+ val &= ~VIA2_IRQ_SCSI_DATA;
+ val |= (~ms->last_irq_levels & VIA2_IRQ_SCSI_DATA);
+ break;
+ }
+
+ return val;
}
static void mos6522_q800_via2_write(void *opaque, hwaddr addr, uint64_t val,
@@ -1061,8 +1050,6 @@ static void mos6522_q800_via1_init(Object *obj)
qbus_init((BusState *)&v1s->adb_bus, sizeof(v1s->adb_bus),
TYPE_ADB_BUS, DEVICE(v1s), "adb.0");
- qdev_init_gpio_in(DEVICE(obj), via1_irq_request, VIA1_IRQ_NB);
-
/* A/UX mode */
qdev_init_gpio_out(DEVICE(obj), &v1s->auxmode_irq, 1);
}
@@ -1110,9 +1097,11 @@ static Property mos6522_q800_via1_properties[] = {
static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
+ MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
dc->realize = mos6522_q800_via1_realize;
- dc->reset = mos6522_q800_via1_reset;
+ device_class_set_parent_reset(dc, mos6522_q800_via1_reset,
+ &mdc->parent_reset);
dc->vmsd = &vmstate_q800_via1;
device_class_set_props(dc, mos6522_q800_via1_properties);
}
@@ -1150,22 +1139,21 @@ static void mos6522_q800_via2_reset(DeviceState *dev)
ms->a = 0x7f;
}
-static void via2_nubus_irq_request(void *opaque, int irq, int level)
+static void via2_nubus_irq_request(void *opaque, int n, int level)
{
MOS6522Q800VIA2State *v2s = opaque;
MOS6522State *s = MOS6522(v2s);
- MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(s), VIA2_IRQ_NUBUS_BIT);
if (level) {
/* Port A nubus IRQ inputs are active LOW */
- s->a &= ~(1 << irq);
- s->ifr |= 1 << VIA2_IRQ_NUBUS_BIT;
+ s->a &= ~(1 << n);
} else {
- s->a |= (1 << irq);
- s->ifr &= ~(1 << VIA2_IRQ_NUBUS_BIT);
+ s->a |= (1 << n);
}
- mdc->update_irq(s);
+ /* Negative edge trigger */
+ qemu_set_irq(irq, !level);
}
static void mos6522_q800_via2_init(Object *obj)
@@ -1177,8 +1165,6 @@ static void mos6522_q800_via2_init(Object *obj)
"via2", VIA_SIZE);
sysbus_init_mmio(sbd, &v2s->via_mem);
- qdev_init_gpio_in(DEVICE(obj), via2_irq_request, VIA2_IRQ_NB);
-
qdev_init_gpio_in_named(DEVICE(obj), via2_nubus_irq_request, "nubus-irq",
VIA2_NUBUS_IRQ_NB);
}
@@ -1199,7 +1185,8 @@ static void mos6522_q800_via2_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
- dc->reset = mos6522_q800_via2_reset;
+ device_class_set_parent_reset(dc, mos6522_q800_via2_reset,
+ &mdc->parent_reset);
dc->vmsd = &vmstate_q800_via2;
mdc->portB_write = mos6522_q800_via2_portB_write;
}
diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c
index 233daf1405..1498113cfc 100644
--- a/hw/misc/macio/cuda.c
+++ b/hw/misc/macio/cuda.c
@@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
+#include "hw/irq.h"
#include "hw/ppc/mac.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
@@ -96,9 +97,9 @@ static void cuda_set_sr_int(void *opaque)
CUDAState *s = opaque;
MOS6522CUDAState *mcs = &s->mos6522_cuda;
MOS6522State *ms = MOS6522(mcs);
- MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT);
- mdc->set_sr_int(ms);
+ qemu_set_irq(irq, 1);
}
static void cuda_delay_set_sr_int(CUDAState *s)
@@ -605,7 +606,8 @@ static void mos6522_cuda_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
- dc->reset = mos6522_cuda_reset;
+ device_class_set_parent_reset(dc, mos6522_cuda_reset,
+ &mdc->parent_reset);
mdc->portB_write = mos6522_cuda_portB_write;
mdc->get_timer1_counter_value = cuda_get_counter_value;
mdc->get_timer2_counter_value = cuda_get_counter_value;
diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c
index 76c608ee19..336502a84b 100644
--- a/hw/misc/macio/pmu.c
+++ b/hw/misc/macio/pmu.c
@@ -57,27 +57,14 @@
#define VIA_TIMER_FREQ (4700000 / 6)
-static void via_update_irq(PMUState *s)
-{
- MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu);
- MOS6522State *ms = MOS6522(mps);
-
- bool new_state = !!(ms->ifr & ms->ier & (SR_INT | T1_INT | T2_INT));
-
- if (new_state != s->via_irq_state) {
- s->via_irq_state = new_state;
- qemu_set_irq(s->via_irq, new_state);
- }
-}
-
static void via_set_sr_int(void *opaque)
{
PMUState *s = opaque;
MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu);
MOS6522State *ms = MOS6522(mps);
- MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(ms);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(ms), SR_INT_BIT);
- mdc->set_sr_int(ms);
+ qemu_set_irq(irq, 1);
}
static void pmu_update_extirq(PMUState *s)
@@ -808,28 +795,9 @@ static void mos6522_pmu_portB_write(MOS6522State *s)
MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj);
PMUState *ps = container_of(mps, PMUState, mos6522_pmu);
- if ((s->pcr & 0xe0) == 0x20 || (s->pcr & 0xe0) == 0x60) {
- s->ifr &= ~CB2_INT;
- }
- s->ifr &= ~CB1_INT;
-
- via_update_irq(ps);
pmu_update(ps);
}
-static void mos6522_pmu_portA_write(MOS6522State *s)
-{
- MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj);
- PMUState *ps = container_of(mps, PMUState, mos6522_pmu);
-
- if ((s->pcr & 0x0e) == 0x02 || (s->pcr & 0x0e) == 0x06) {
- s->ifr &= ~CA2_INT;
- }
- s->ifr &= ~CA1_INT;
-
- via_update_irq(ps);
-}
-
static void mos6522_pmu_reset(DeviceState *dev)
{
MOS6522State *ms = MOS6522(dev);
@@ -850,9 +818,9 @@ static void mos6522_pmu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
MOS6522DeviceClass *mdc = MOS6522_CLASS(oc);
- dc->reset = mos6522_pmu_reset;
+ device_class_set_parent_reset(dc, mos6522_pmu_reset,
+ &mdc->parent_reset);
mdc->portB_write = mos6522_pmu_portB_write;
- mdc->portA_write = mos6522_pmu_portA_write;
}
static const TypeInfo mos6522_pmu_type_info = {
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 1c57332b40..f9e646350e 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -30,12 +30,21 @@
#include "hw/misc/mos6522.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
+#include "monitor/monitor.h"
+#include "monitor/hmp.h"
+#include "qapi/type-helpers.h"
#include "qemu/timer.h"
#include "qemu/cutils.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "trace.h"
+
+static const char *mos6522_reg_names[MOS6522_NUM_REGS] = {
+ "ORB", "ORA", "DDRB", "DDRA", "T1CL", "T1CH", "T1LL", "T1LH",
+ "T2CL", "T2CH", "SR", "ACR", "PCR", "IFR", "IER", "ANH"
+};
+
/* XXX: implement all timer modes */
static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti,
@@ -52,6 +61,73 @@ static void mos6522_update_irq(MOS6522State *s)
}
}
+static void mos6522_set_irq(void *opaque, int n, int level)
+{
+ MOS6522State *s = MOS6522(opaque);
+ int last_level = !!(s->last_irq_levels & (1 << n));
+ uint8_t last_ifr = s->ifr;
+ bool positive_edge = true;
+ int ctrl;
+
+ /*
+ * SR_INT is managed by mos6522 instances and cleared upon SR
+ * read. It is only the external CA1/2 and CB1/2 lines that
+ * are edge-triggered and latched in IFR
+ */
+ if (n != SR_INT_BIT && level == last_level) {
+ return;
+ }
+
+ /* Detect negative edge trigger */
+ if (last_level == 1 && level == 0) {
+ positive_edge = false;
+ }
+
+ switch (n) {
+ case CA2_INT_BIT:
+ ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
+ if ((positive_edge && (ctrl & C2_POS)) ||
+ (!positive_edge && !(ctrl & C2_POS))) {
+ s->ifr |= 1 << n;
+ }
+ break;
+ case CA1_INT_BIT:
+ ctrl = (s->pcr & CA1_CTRL_MASK) >> CA1_CTRL_SHIFT;
+ if ((positive_edge && (ctrl & C1_POS)) ||
+ (!positive_edge && !(ctrl & C1_POS))) {
+ s->ifr |= 1 << n;
+ }
+ break;
+ case SR_INT_BIT:
+ s->ifr |= 1 << n;
+ break;
+ case CB2_INT_BIT:
+ ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
+ if ((positive_edge && (ctrl & C2_POS)) ||
+ (!positive_edge && !(ctrl & C2_POS))) {
+ s->ifr |= 1 << n;
+ }
+ break;
+ case CB1_INT_BIT:
+ ctrl = (s->pcr & CB1_CTRL_MASK) >> CB1_CTRL_SHIFT;
+ if ((positive_edge && (ctrl & C1_POS)) ||
+ (!positive_edge && !(ctrl & C1_POS))) {
+ s->ifr |= 1 << n;
+ }
+ break;
+ }
+
+ if (s->ifr != last_ifr) {
+ mos6522_update_irq(s);
+ }
+
+ if (level) {
+ s->last_irq_levels |= 1 << n;
+ } else {
+ s->last_irq_levels &= ~(1 << n);
+ }
+}
+
static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti)
{
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
@@ -195,13 +271,6 @@ static void mos6522_timer2(void *opaque)
mos6522_update_irq(s);
}
-static void mos6522_set_sr_int(MOS6522State *s)
-{
- trace_mos6522_set_sr_int();
- s->ifr |= SR_INT;
- mos6522_update_irq(s);
-}
-
static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti)
{
return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
@@ -229,6 +298,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
{
MOS6522State *s = opaque;
uint32_t val;
+ int ctrl;
int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
if (now >= s->timers[0].next_irq_time) {
@@ -242,12 +312,24 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
switch (addr) {
case VIA_REG_B:
val = s->b;
+ ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
+ if (!(ctrl & C2_IND)) {
+ s->ifr &= ~CB2_INT;
+ }
+ s->ifr &= ~CB1_INT;
+ mos6522_update_irq(s);
break;
case VIA_REG_A:
qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake");
/* fall through */
case VIA_REG_ANH:
val = s->a;
+ ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
+ if (!(ctrl & C2_IND)) {
+ s->ifr &= ~CA2_INT;
+ }
+ s->ifr &= ~CA1_INT;
+ mos6522_update_irq(s);
break;
case VIA_REG_DIRB:
val = s->dirb;
@@ -304,7 +386,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
}
if (addr != VIA_REG_IFR || val != 0) {
- trace_mos6522_read(addr, val);
+ trace_mos6522_read(addr, mos6522_reg_names[addr], val);
}
return val;
@@ -314,13 +396,20 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
{
MOS6522State *s = opaque;
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
+ int ctrl;
- trace_mos6522_write(addr, val);
+ trace_mos6522_write(addr, mos6522_reg_names[addr], val);
switch (addr) {
case VIA_REG_B:
s->b = (s->b & ~s->dirb) | (val & s->dirb);
mdc->portB_write(s);
+ ctrl = (s->pcr & CB2_CTRL_MASK) >> CB2_CTRL_SHIFT;
+ if (!(ctrl & C2_IND)) {
+ s->ifr &= ~CB2_INT;
+ }
+ s->ifr &= ~CB1_INT;
+ mos6522_update_irq(s);
break;
case VIA_REG_A:
qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake");
@@ -328,6 +417,12 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
case VIA_REG_ANH:
s->a = (s->a & ~s->dira) | (val & s->dira);
mdc->portA_write(s);
+ ctrl = (s->pcr & CA2_CTRL_MASK) >> CA2_CTRL_SHIFT;
+ if (!(ctrl & C2_IND)) {
+ s->ifr &= ~CA2_INT;
+ }
+ s->ifr &= ~CA1_INT;
+ mos6522_update_irq(s);
break;
case VIA_REG_DIRB:
s->dirb = val;
@@ -403,6 +498,106 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
}
}
+static int qmp_x_query_via_foreach(Object *obj, void *opaque)
+{
+ GString *buf = opaque;
+
+ if (object_dynamic_cast(obj, TYPE_MOS6522)) {
+ MOS6522State *s = MOS6522(obj);
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ uint16_t t1counter = get_counter(s, &s->timers[0]);
+ uint16_t t2counter = get_counter(s, &s->timers[1]);
+
+ g_string_append_printf(buf, "%s:\n", object_get_typename(obj));
+
+ g_string_append_printf(buf, " Registers:\n");
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[0], s->b);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[1], s->a);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[2], s->dirb);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[3], s->dira);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[4], t1counter & 0xff);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[5], t1counter >> 8);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[6],
+ s->timers[0].latch & 0xff);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[7],
+ s->timers[0].latch >> 8);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[8], t2counter & 0xff);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[9], t2counter >> 8);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[10], s->sr);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[11], s->acr);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[12], s->pcr);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[13], s->ifr);
+ g_string_append_printf(buf, " %-*s: 0x%x\n", 4,
+ mos6522_reg_names[14], s->ier);
+
+ g_string_append_printf(buf, " Timers:\n");
+ g_string_append_printf(buf, " Using current time now(ns)=%"PRId64
+ "\n", now);
+ g_string_append_printf(buf, " T1 freq(hz)=%"PRId64
+ " mode=%s"
+ " counter=0x%x"
+ " latch=0x%x\n"
+ " load_time(ns)=%"PRId64
+ " next_irq_time(ns)=%"PRId64 "\n",
+ s->timers[0].frequency,
+ ((s->acr & T1MODE) == T1MODE_CONT) ? "continuous"
+ : "one-shot",
+ t1counter,
+ s->timers[0].latch,
+ s->timers[0].load_time,
+ get_next_irq_time(s, &s->timers[0], now));
+ g_string_append_printf(buf, " T2 freq(hz)=%"PRId64
+ " mode=%s"
+ " counter=0x%x"
+ " latch=0x%x\n"
+ " load_time(ns)=%"PRId64
+ " next_irq_time(ns)=%"PRId64 "\n",
+ s->timers[1].frequency,
+ "one-shot",
+ t2counter,
+ s->timers[1].latch,
+ s->timers[1].load_time,
+ get_next_irq_time(s, &s->timers[1], now));
+ }
+
+ return 0;
+}
+
+static HumanReadableText *qmp_x_query_via(Error **errp)
+{
+ g_autoptr(GString) buf = g_string_new("");
+
+ object_child_foreach_recursive(object_get_root(),
+ qmp_x_query_via_foreach, buf);
+
+ return human_readable_text_from_str(buf);
+}
+
+void hmp_info_via(Monitor *mon, const QDict *qdict)
+{
+ Error *err = NULL;
+ g_autoptr(HumanReadableText) info = qmp_x_query_via(&err);
+
+ if (hmp_handle_error(mon, err)) {
+ return;
+ }
+ monitor_printf(mon, "%s", info->human_readable_text);
+}
+
static const MemoryRegionOps mos6522_ops = {
.read = mos6522_read,
.write = mos6522_write,
@@ -429,8 +624,8 @@ static const VMStateDescription vmstate_mos6522_timer = {
const VMStateDescription vmstate_mos6522 = {
.name = "mos6522",
- .version_id = 0,
- .minimum_version_id = 0,
+ .version_id = 1,
+ .minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT8(a, MOS6522State),
VMSTATE_UINT8(b, MOS6522State),
@@ -441,6 +636,7 @@ const VMStateDescription vmstate_mos6522 = {
VMSTATE_UINT8(pcr, MOS6522State),
VMSTATE_UINT8(ifr, MOS6522State),
VMSTATE_UINT8(ier, MOS6522State),
+ VMSTATE_UINT8(last_irq_levels, MOS6522State),
VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0,
vmstate_mos6522_timer, MOS6522Timer),
VMSTATE_END_OF_LIST()
@@ -478,7 +674,8 @@ static void mos6522_init(Object *obj)
MOS6522State *s = MOS6522(obj);
int i;
- memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10);
+ memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522",
+ MOS6522_NUM_REGS);
sysbus_init_mmio(sbd, &s->mem);
sysbus_init_irq(sbd, &s->irq);
@@ -488,6 +685,8 @@ static void mos6522_init(Object *obj)
s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s);
s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s);
+
+ qdev_init_gpio_in(DEVICE(obj), mos6522_set_irq, VIA_NUM_INTS);
}
static void mos6522_finalize(Object *obj)
@@ -511,11 +710,8 @@ static void mos6522_class_init(ObjectClass *oc, void *data)
dc->reset = mos6522_reset;
dc->vmsd = &vmstate_mos6522;
device_class_set_props(dc, mos6522_properties);
- mdc->parent_reset = dc->reset;
- mdc->set_sr_int = mos6522_set_sr_int;
mdc->portB_write = mos6522_portB_write;
mdc->portA_write = mos6522_portA_write;
- mdc->update_irq = mos6522_update_irq;
mdc->get_timer1_counter_value = mos6522_get_counter_value;
mdc->get_timer2_counter_value = mos6522_get_counter_value;
mdc->get_timer1_load_time = mos6522_get_load_time;
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index fb5a389780..bd52cfc110 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -95,8 +95,8 @@ imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08" PRIx64 "value 0x%08
mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"
mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d counter=0x%"PRId64 " delta_next=0x%"PRId64
mos6522_set_sr_int(void) "set sr_int"
-mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
-mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
+mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 " [%s] val=0x%"PRIx64
+mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 " [%s] val=0x%x"
# npcm7xx_clk.c
npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-23 18:31:18 +0000