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-rw-r--r--hw/isa/Makefile.objs1
-rw-r--r--hw/isa/isa-bus.c26
-rw-r--r--hw/isa/isa-superio.c214
-rw-r--r--hw/isa/pc87312.c178
-rw-r--r--hw/isa/smc37c669-superio.c115
-rw-r--r--hw/isa/trace-events10
-rw-r--r--hw/isa/vt82c686.c22
7 files changed, 435 insertions, 131 deletions
diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
index fb37c55cf2..83e06f6c04 100644
--- a/hw/isa/Makefile.objs
+++ b/hw/isa/Makefile.objs
@@ -1,4 +1,5 @@
common-obj-$(CONFIG_ISA_BUS) += isa-bus.o
+common-obj-$(CONFIG_ISA_BUS) += isa-superio.o smc37c669-superio.o
common-obj-$(CONFIG_APM) += apm.o
common-obj-$(CONFIG_I82378) += i82378.o
common-obj-$(CONFIG_PC87312) += pc87312.o
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index 0f2e426d02..63fa77effc 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -24,7 +24,6 @@
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "hw/isa/isa.h"
-#include "hw/i386/pc.h"
static ISABus *isabus;
@@ -288,28 +287,3 @@ MemoryRegion *isa_address_space_io(ISADevice *dev)
}
type_init(isabus_register_types)
-
-static void parallel_init(ISABus *bus, int index, Chardev *chr)
-{
- DeviceState *dev;
- ISADevice *isadev;
-
- isadev = isa_create(bus, "isa-parallel");
- dev = DEVICE(isadev);
- qdev_prop_set_uint32(dev, "index", index);
- qdev_prop_set_chr(dev, "chardev", chr);
- qdev_init_nofail(dev);
-}
-
-void parallel_hds_isa_init(ISABus *bus, int n)
-{
- int i;
-
- assert(n <= MAX_PARALLEL_PORTS);
-
- for (i = 0; i < n; i++) {
- if (parallel_hds[i]) {
- parallel_init(bus, i, parallel_hds[i]);
- }
- }
-}
diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c
new file mode 100644
index 0000000000..b95608a003
--- /dev/null
+++ b/hw/isa/isa-superio.c
@@ -0,0 +1,214 @@
+/*
+ * Generic ISA Super I/O
+ *
+ * Copyright (c) 2010-2012 Herve Poussineau
+ * Copyright (c) 2011-2012 Andreas Färber
+ * Copyright (c) 2018 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ * See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+#include "qemu/osdep.h"
+#include "qemu/error-report.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/block-backend.h"
+#include "sysemu/blockdev.h"
+#include "chardev/char.h"
+#include "hw/isa/superio.h"
+#include "hw/input/i8042.h"
+#include "hw/char/serial.h"
+#include "trace.h"
+
+static void isa_superio_realize(DeviceState *dev, Error **errp)
+{
+ ISASuperIODevice *sio = ISA_SUPERIO(dev);
+ ISASuperIOClass *k = ISA_SUPERIO_GET_CLASS(sio);
+ ISABus *bus = isa_bus_from_device(ISA_DEVICE(dev));
+ ISADevice *isa;
+ DeviceState *d;
+ Chardev *chr;
+ DriveInfo *drive;
+ char *name;
+ int i;
+
+ /* Parallel port */
+ for (i = 0; i < k->parallel.count; i++) {
+ if (i >= ARRAY_SIZE(sio->parallel)) {
+ warn_report("superio: ignoring %td parallel controllers",
+ k->parallel.count - ARRAY_SIZE(sio->parallel));
+ break;
+ }
+ if (!k->parallel.is_enabled || k->parallel.is_enabled(sio, i)) {
+ /* FIXME use a qdev chardev prop instead of parallel_hds[] */
+ chr = parallel_hds[i];
+ if (chr == NULL || chr->be) {
+ name = g_strdup_printf("discarding-parallel%d", i);
+ chr = qemu_chr_new(name, "null");
+ } else {
+ name = g_strdup_printf("parallel%d", i);
+ }
+ isa = isa_create(bus, "isa-parallel");
+ d = DEVICE(isa);
+ qdev_prop_set_uint32(d, "index", i);
+ if (k->parallel.get_iobase) {
+ qdev_prop_set_uint32(d, "iobase",
+ k->parallel.get_iobase(sio, i));
+ }
+ if (k->parallel.get_irq) {
+ qdev_prop_set_uint32(d, "irq", k->parallel.get_irq(sio, i));
+ }
+ qdev_prop_set_chr(d, "chardev", chr);
+ qdev_init_nofail(d);
+ sio->parallel[i] = isa;
+ trace_superio_create_parallel(i,
+ k->parallel.get_iobase ?
+ k->parallel.get_iobase(sio, i) : -1,
+ k->parallel.get_irq ?
+ k->parallel.get_irq(sio, i) : -1);
+ object_property_add_child(OBJECT(dev), name,
+ OBJECT(sio->parallel[i]), NULL);
+ g_free(name);
+ }
+ }
+
+ /* Serial */
+ for (i = 0; i < k->serial.count; i++) {
+ if (i >= ARRAY_SIZE(sio->serial)) {
+ warn_report("superio: ignoring %td serial controllers",
+ k->serial.count - ARRAY_SIZE(sio->serial));
+ break;
+ }
+ if (!k->serial.is_enabled || k->serial.is_enabled(sio, i)) {
+ /* FIXME use a qdev chardev prop instead of serial_hds[] */
+ chr = serial_hds[i];
+ if (chr == NULL || chr->be) {
+ name = g_strdup_printf("discarding-serial%d", i);
+ chr = qemu_chr_new(name, "null");
+ } else {
+ name = g_strdup_printf("serial%d", i);
+ }
+ isa = isa_create(bus, TYPE_ISA_SERIAL);
+ d = DEVICE(isa);
+ qdev_prop_set_uint32(d, "index", i);
+ if (k->serial.get_iobase) {
+ qdev_prop_set_uint32(d, "iobase",
+ k->serial.get_iobase(sio, i));
+ }
+ if (k->serial.get_irq) {
+ qdev_prop_set_uint32(d, "irq", k->serial.get_irq(sio, i));
+ }
+ qdev_prop_set_chr(d, "chardev", chr);
+ qdev_init_nofail(d);
+ sio->serial[i] = isa;
+ trace_superio_create_serial(i,
+ k->serial.get_iobase ?
+ k->serial.get_iobase(sio, i) : -1,
+ k->serial.get_irq ?
+ k->serial.get_irq(sio, i) : -1);
+ object_property_add_child(OBJECT(dev), name,
+ OBJECT(sio->serial[0]), NULL);
+ g_free(name);
+ }
+ }
+
+ /* Floppy disc */
+ if (!k->floppy.is_enabled || k->floppy.is_enabled(sio, 0)) {
+ isa = isa_create(bus, "isa-fdc");
+ d = DEVICE(isa);
+ if (k->floppy.get_iobase) {
+ qdev_prop_set_uint32(d, "iobase", k->floppy.get_iobase(sio, 0));
+ }
+ if (k->floppy.get_irq) {
+ qdev_prop_set_uint32(d, "irq", k->floppy.get_irq(sio, 0));
+ }
+ /* FIXME use a qdev drive property instead of drive_get() */
+ drive = drive_get(IF_FLOPPY, 0, 0);
+ if (drive != NULL) {
+ qdev_prop_set_drive(d, "driveA", blk_by_legacy_dinfo(drive),
+ &error_fatal);
+ }
+ /* FIXME use a qdev drive property instead of drive_get() */
+ drive = drive_get(IF_FLOPPY, 0, 1);
+ if (drive != NULL) {
+ qdev_prop_set_drive(d, "driveB", blk_by_legacy_dinfo(drive),
+ &error_fatal);
+ }
+ qdev_init_nofail(d);
+ sio->floppy = isa;
+ trace_superio_create_floppy(0,
+ k->floppy.get_iobase ?
+ k->floppy.get_iobase(sio, 0) : -1,
+ k->floppy.get_irq ?
+ k->floppy.get_irq(sio, 0) : -1);
+ }
+
+ /* Keyboard, mouse */
+ sio->kbc = isa_create_simple(bus, TYPE_I8042);
+
+ /* IDE */
+ if (k->ide.count && (!k->ide.is_enabled || k->ide.is_enabled(sio, 0))) {
+ isa = isa_create(bus, "isa-ide");
+ d = DEVICE(isa);
+ if (k->ide.get_iobase) {
+ qdev_prop_set_uint32(d, "iobase", k->ide.get_iobase(sio, 0));
+ }
+ if (k->ide.get_iobase) {
+ qdev_prop_set_uint32(d, "iobase2", k->ide.get_iobase(sio, 1));
+ }
+ if (k->ide.get_irq) {
+ qdev_prop_set_uint32(d, "irq", k->ide.get_irq(sio, 0));
+ }
+ qdev_init_nofail(d);
+ sio->ide = isa;
+ trace_superio_create_ide(0,
+ k->ide.get_iobase ?
+ k->ide.get_iobase(sio, 0) : -1,
+ k->ide.get_irq ?
+ k->ide.get_irq(sio, 0) : -1);
+ }
+}
+
+static void isa_superio_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = isa_superio_realize;
+ /* Reason: Uses parallel_hds[0] in realize(), so it can't be used twice */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo isa_superio_type_info = {
+ .name = TYPE_ISA_SUPERIO,
+ .parent = TYPE_ISA_DEVICE,
+ .abstract = true,
+ .class_size = sizeof(ISASuperIOClass),
+ .class_init = isa_superio_class_init,
+};
+
+/* SMS FDC37M817 Super I/O */
+static void fdc37m81x_class_init(ObjectClass *klass, void *data)
+{
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ sc->serial.count = 2; /* NS16C550A */
+ sc->parallel.count = 1;
+ sc->floppy.count = 1; /* SMSC 82077AA Compatible */
+ sc->ide.count = 0;
+}
+
+static const TypeInfo fdc37m81x_type_info = {
+ .name = TYPE_FDC37M81X_SUPERIO,
+ .parent = TYPE_ISA_SUPERIO,
+ .instance_size = sizeof(ISASuperIODevice),
+ .class_init = fdc37m81x_class_init,
+};
+
+static void isa_superio_register_types(void)
+{
+ type_register_static(&isa_superio_type_info);
+ type_register_static(&fdc37m81x_type_info);
+}
+
+type_init(isa_superio_register_types)
diff --git a/hw/isa/pc87312.c b/hw/isa/pc87312.c
index 48b29e3c3c..5cf64505fe 100644
--- a/hw/isa/pc87312.c
+++ b/hw/isa/pc87312.c
@@ -27,10 +27,6 @@
#include "hw/isa/pc87312.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
-#include "sysemu/block-backend.h"
-#include "sysemu/blockdev.h"
-#include "sysemu/sysemu.h"
-#include "chardev/char.h"
#include "trace.h"
@@ -64,22 +60,25 @@
/* Parallel port */
-static inline bool is_parallel_enabled(PC87312State *s)
+static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index)
{
- return s->regs[REG_FER] & FER_PARALLEL_EN;
+ PC87312State *s = PC87312(sio);
+ return index ? false : s->regs[REG_FER] & FER_PARALLEL_EN;
}
-static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
+static const uint16_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
-static inline uint32_t get_parallel_iobase(PC87312State *s)
+static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index)
{
+ PC87312State *s = PC87312(sio);
return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
}
-static const uint32_t parallel_irq[] = { 5, 7, 5, 0 };
+static const unsigned int parallel_irq[] = { 5, 7, 5, 0 };
-static inline uint32_t get_parallel_irq(PC87312State *s)
+static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index)
{
+ PC87312State *s = PC87312(sio);
int idx;
idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
if (idx == 0) {
@@ -92,13 +91,14 @@ static inline uint32_t get_parallel_irq(PC87312State *s)
/* UARTs */
-static const uint32_t uart_base[2][4] = {
+static const uint16_t uart_base[2][4] = {
{ 0x3e8, 0x338, 0x2e8, 0x220 },
{ 0x2e8, 0x238, 0x2e0, 0x228 }
};
-static inline uint32_t get_uart_iobase(PC87312State *s, int i)
+static uint16_t get_uart_iobase(ISASuperIODevice *sio, uint8_t i)
{
+ PC87312State *s = PC87312(sio);
int idx;
idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
if (idx == 0) {
@@ -110,44 +110,68 @@ static inline uint32_t get_uart_iobase(PC87312State *s, int i)
}
}
-static inline uint32_t get_uart_irq(PC87312State *s, int i)
+static unsigned int get_uart_irq(ISASuperIODevice *sio, uint8_t i)
{
+ PC87312State *s = PC87312(sio);
int idx;
idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
return (idx & 1) ? 3 : 4;
}
-static inline bool is_uart_enabled(PC87312State *s, int i)
+static bool is_uart_enabled(ISASuperIODevice *sio, uint8_t i)
{
+ PC87312State *s = PC87312(sio);
return s->regs[REG_FER] & (FER_UART1_EN << i);
}
/* Floppy controller */
-static inline bool is_fdc_enabled(PC87312State *s)
+static bool is_fdc_enabled(ISASuperIODevice *sio, uint8_t index)
{
+ PC87312State *s = PC87312(sio);
+ assert(!index);
return s->regs[REG_FER] & FER_FDC_EN;
}
-static inline uint32_t get_fdc_iobase(PC87312State *s)
+static uint16_t get_fdc_iobase(ISASuperIODevice *sio, uint8_t index)
{
+ PC87312State *s = PC87312(sio);
+ assert(!index);
return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0;
}
+static unsigned int get_fdc_irq(ISASuperIODevice *sio, uint8_t index)
+{
+ assert(!index);
+ return 6;
+}
+
/* IDE controller */
-static inline bool is_ide_enabled(PC87312State *s)
+static bool is_ide_enabled(ISASuperIODevice *sio, uint8_t index)
{
+ PC87312State *s = PC87312(sio);
+
return s->regs[REG_FER] & FER_IDE_EN;
}
-static inline uint32_t get_ide_iobase(PC87312State *s)
+static uint16_t get_ide_iobase(ISASuperIODevice *sio, uint8_t index)
{
+ PC87312State *s = PC87312(sio);
+
+ if (index == 1) {
+ return get_ide_iobase(sio, 0) + 0x206;
+ }
return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0;
}
+static unsigned int get_ide_irq(ISASuperIODevice *sio, uint8_t index)
+{
+ assert(index == 0);
+ return 14;
+}
static void reconfigure_devices(PC87312State *s)
{
@@ -265,90 +289,18 @@ static void pc87312_reset(DeviceState *d)
static void pc87312_realize(DeviceState *dev, Error **errp)
{
PC87312State *s;
- DeviceState *d;
ISADevice *isa;
- ISABus *bus;
- Chardev *chr;
- DriveInfo *drive;
- char name[5];
- int i;
+ Error *local_err = NULL;
s = PC87312(dev);
isa = ISA_DEVICE(dev);
- bus = isa_bus_from_device(isa);
isa_register_ioport(isa, &s->io, s->iobase);
pc87312_hard_reset(s);
- if (is_parallel_enabled(s)) {
- /* FIXME use a qdev chardev prop instead of parallel_hds[] */
- chr = parallel_hds[0];
- if (chr == NULL) {
- chr = qemu_chr_new("par0", "null");
- }
- isa = isa_create(bus, "isa-parallel");
- d = DEVICE(isa);
- qdev_prop_set_uint32(d, "index", 0);
- qdev_prop_set_uint32(d, "iobase", get_parallel_iobase(s));
- qdev_prop_set_uint32(d, "irq", get_parallel_irq(s));
- qdev_prop_set_chr(d, "chardev", chr);
- qdev_init_nofail(d);
- s->parallel.dev = isa;
- trace_pc87312_info_parallel(get_parallel_iobase(s),
- get_parallel_irq(s));
- }
-
- for (i = 0; i < 2; i++) {
- if (is_uart_enabled(s, i)) {
- /* FIXME use a qdev chardev prop instead of serial_hds[] */
- chr = serial_hds[i];
- if (chr == NULL) {
- snprintf(name, sizeof(name), "ser%d", i);
- chr = qemu_chr_new(name, "null");
- }
- isa = isa_create(bus, "isa-serial");
- d = DEVICE(isa);
- qdev_prop_set_uint32(d, "index", i);
- qdev_prop_set_uint32(d, "iobase", get_uart_iobase(s, i));
- qdev_prop_set_uint32(d, "irq", get_uart_irq(s, i));
- qdev_prop_set_chr(d, "chardev", chr);
- qdev_init_nofail(d);
- s->uart[i].dev = isa;
- trace_pc87312_info_serial(i, get_uart_iobase(s, i),
- get_uart_irq(s, i));
- }
- }
-
- if (is_fdc_enabled(s)) {
- isa = isa_create(bus, "isa-fdc");
- d = DEVICE(isa);
- qdev_prop_set_uint32(d, "iobase", get_fdc_iobase(s));
- qdev_prop_set_uint32(d, "irq", 6);
- /* FIXME use a qdev drive property instead of drive_get() */
- drive = drive_get(IF_FLOPPY, 0, 0);
- if (drive != NULL) {
- qdev_prop_set_drive(d, "driveA", blk_by_legacy_dinfo(drive),
- &error_fatal);
- }
- /* FIXME use a qdev drive property instead of drive_get() */
- drive = drive_get(IF_FLOPPY, 0, 1);
- if (drive != NULL) {
- qdev_prop_set_drive(d, "driveB", blk_by_legacy_dinfo(drive),
- &error_fatal);
- }
- qdev_init_nofail(d);
- s->fdc.dev = isa;
- trace_pc87312_info_floppy(get_fdc_iobase(s));
- }
-
- if (is_ide_enabled(s)) {
- isa = isa_create(bus, "isa-ide");
- d = DEVICE(isa);
- qdev_prop_set_uint32(d, "iobase", get_ide_iobase(s));
- qdev_prop_set_uint32(d, "iobase2", get_ide_iobase(s) + 0x206);
- qdev_prop_set_uint32(d, "irq", 14);
- qdev_init_nofail(d);
- s->ide.dev = isa;
- trace_pc87312_info_ide(get_ide_iobase(s));
+ ISA_SUPERIO_GET_CLASS(dev)->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
}
}
@@ -373,7 +325,7 @@ static const VMStateDescription vmstate_pc87312 = {
};
static Property pc87312_properties[] = {
- DEFINE_PROP_UINT32("iobase", PC87312State, iobase, 0x398),
+ DEFINE_PROP_UINT16("iobase", PC87312State, iobase, 0x398),
DEFINE_PROP_UINT8("config", PC87312State, config, 1),
DEFINE_PROP_END_OF_LIST()
};
@@ -381,21 +333,47 @@ static Property pc87312_properties[] = {
static void pc87312_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+ sc->parent_realize = dc->realize;
dc->realize = pc87312_realize;
dc->reset = pc87312_reset;
dc->vmsd = &vmstate_pc87312;
dc->props = pc87312_properties;
- /* Reason: Uses parallel_hds[0] in realize(), so it can't be used twice */
- dc->user_creatable = false;
+
+ sc->parallel = (ISASuperIOFuncs){
+ .count = 1,
+ .is_enabled = is_parallel_enabled,
+ .get_iobase = get_parallel_iobase,
+ .get_irq = get_parallel_irq,
+ };
+ sc->serial = (ISASuperIOFuncs){
+ .count = 2,
+ .is_enabled = is_uart_enabled,
+ .get_iobase = get_uart_iobase,
+ .get_irq = get_uart_irq,
+ };
+ sc->floppy = (ISASuperIOFuncs){
+ .count = 1,
+ .is_enabled = is_fdc_enabled,
+ .get_iobase = get_fdc_iobase,
+ .get_irq = get_fdc_irq,
+ };
+ sc->ide = (ISASuperIOFuncs){
+ .count = 1,
+ .is_enabled = is_ide_enabled,
+ .get_iobase = get_ide_iobase,
+ .get_irq = get_ide_irq,
+ };
}
static const TypeInfo pc87312_type_info = {
- .name = TYPE_PC87312,
- .parent = TYPE_ISA_DEVICE,
+ .name = TYPE_PC87312_SUPERIO,
+ .parent = TYPE_ISA_SUPERIO,
.instance_size = sizeof(PC87312State),
.instance_init = pc87312_initfn,
.class_init = pc87312_class_init,
+ /* FIXME use a qdev drive property instead of drive_get() */
};
static void pc87312_register_types(void)
diff --git a/hw/isa/smc37c669-superio.c b/hw/isa/smc37c669-superio.c
new file mode 100644
index 0000000000..aa233c6967
--- /dev/null
+++ b/hw/isa/smc37c669-superio.c
@@ -0,0 +1,115 @@
+/*
+ * SMC FDC37C669 Super I/O controller
+ *
+ * Copyright (c) 2018 Philippe Mathieu-Daudé
+ *
+ * This code is licensed under the GNU GPLv2 and later.
+ * See the COPYING file in the top-level directory.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/isa/superio.h"
+
+/* UARTs (compatible with NS16450 or PC16550) */
+
+static bool is_serial_enabled(ISASuperIODevice *sio, uint8_t index)
+{
+ return index < 2;
+}
+
+static uint16_t get_serial_iobase(ISASuperIODevice *sio, uint8_t index)
+{
+ return index ? 0x2f8 : 0x3f8;
+}
+
+static unsigned int get_serial_irq(ISASuperIODevice *sio, uint8_t index)
+{
+ return index ? 3 : 4;
+}
+
+/* Parallel port */
+
+static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index)
+{
+ return index < 1;
+}
+
+static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index)
+{
+ return 0x3bc;
+}
+
+static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index)
+{
+ return 7;
+}
+
+static unsigned int get_parallel_dma(ISASuperIODevice *sio, uint8_t index)
+{
+ return 3;
+}
+
+/* Diskette controller (Software compatible with the Intel PC8477) */
+
+static bool is_fdc_enabled(ISASuperIODevice *sio, uint8_t index)
+{
+ return index < 1;
+}
+
+static uint16_t get_fdc_iobase(ISASuperIODevice *sio, uint8_t index)
+{
+ return 0x3f0;
+}
+
+static unsigned int get_fdc_irq(ISASuperIODevice *sio, uint8_t index)
+{
+ return 6;
+}
+
+static unsigned int get_fdc_dma(ISASuperIODevice *sio, uint8_t index)
+{
+ return 2;
+}
+
+static void smc37c669_class_init(ObjectClass *klass, void *data)
+{
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ sc->parallel = (ISASuperIOFuncs){
+ .count = 1,
+ .is_enabled = is_parallel_enabled,
+ .get_iobase = get_parallel_iobase,
+ .get_irq = get_parallel_irq,
+ .get_dma = get_parallel_dma,
+ };
+ sc->serial = (ISASuperIOFuncs){
+ .count = 2,
+ .is_enabled = is_serial_enabled,
+ .get_iobase = get_serial_iobase,
+ .get_irq = get_serial_irq,
+ };
+ sc->floppy = (ISASuperIOFuncs){
+ .count = 1,
+ .is_enabled = is_fdc_enabled,
+ .get_iobase = get_fdc_iobase,
+ .get_irq = get_fdc_irq,
+ .get_dma = get_fdc_dma,
+ };
+ sc->ide.count = 0;
+}
+
+static const TypeInfo smc37c669_type_info = {
+ .name = TYPE_SMC37C669_SUPERIO,
+ .parent = TYPE_ISA_SUPERIO,
+ .instance_size = sizeof(ISASuperIODevice),
+ .class_size = sizeof(ISASuperIOClass),
+ .class_init = smc37c669_class_init,
+};
+
+static void smc37c669_register_types(void)
+{
+ type_register_static(&smc37c669_type_info);
+}
+
+type_init(smc37c669_register_types)
diff --git a/hw/isa/trace-events b/hw/isa/trace-events
index a4ab4e3634..80ac6175d6 100644
--- a/hw/isa/trace-events
+++ b/hw/isa/trace-events
@@ -1,9 +1,11 @@
# See docs/devel/tracing.txt for syntax documentation.
+# hw/isa/isa-superio.c
+superio_create_parallel(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
+superio_create_serial(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
+superio_create_floppy(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
+superio_create_ide(int id, uint16_t base, unsigned int irq) "id=%d, base 0x%03x, irq %u"
+
# hw/isa/pc87312.c
pc87312_io_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
pc87312_io_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
-pc87312_info_floppy(uint32_t base) "base 0x%x"
-pc87312_info_ide(uint32_t base) "base 0x%x"
-pc87312_info_parallel(uint32_t base, uint32_t irq) "base 0x%x, irq %u"
-pc87312_info_serial(int n, uint32_t base, uint32_t irq) "id=%d, base 0x%x, irq %u"
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 070cc1889f..cff1946232 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -17,6 +17,7 @@
#include "hw/i2c/smbus.h"
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
+#include "hw/isa/superio.h"
#include "hw/sysbus.h"
#include "hw/mips/mips.h"
#include "hw/isa/apm.h"
@@ -478,7 +479,7 @@ static void vt82c686b_realize(PCIDevice *d, Error **errp)
qemu_register_reset(vt82c686b_reset, d);
}
-ISABus *vt82c686b_init(PCIBus *bus, int devfn)
+ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn)
{
PCIDevice *d;
@@ -519,11 +520,30 @@ static const TypeInfo via_info = {
},
};
+static void vt82c686b_superio_class_init(ObjectClass *klass, void *data)
+{
+ ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
+
+ sc->serial.count = 2;
+ sc->parallel.count = 1;
+ sc->ide.count = 0;
+ sc->floppy.count = 1;
+}
+
+static const TypeInfo via_superio_info = {
+ .name = TYPE_VT82C686B_SUPERIO,
+ .parent = TYPE_ISA_SUPERIO,
+ .instance_size = sizeof(ISASuperIODevice),
+ .class_size = sizeof(ISASuperIOClass),
+ .class_init = vt82c686b_superio_class_init,
+};
+
static void vt82c686b_register_types(void)
{
type_register_static(&via_ac97_info);
type_register_static(&via_mc97_info);
type_register_static(&via_pm_info);
+ type_register_static(&via_superio_info);
type_register_static(&via_info);
}
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-01 19:24:54 +0000