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-rw-r--r--hw/intc/apic.c1
-rw-r--r--hw/intc/arm_gic_kvm.c6
-rw-r--r--hw/intc/arm_gicv2m.c6
-rw-r--r--hw/intc/arm_gicv3_its_kvm.c6
-rw-r--r--hw/intc/arm_gicv3_kvm.c6
-rw-r--r--hw/intc/etraxfs_pic.c1
-rw-r--r--hw/intc/exynos4210_combiner.c6
-rw-r--r--hw/intc/exynos4210_gic.c11
-rw-r--r--hw/intc/grlib_irqmp.c6
-rw-r--r--hw/intc/i8259.c6
-rw-r--r--hw/intc/lm32_pic.c3
-rw-r--r--hw/intc/loongson_liointc.c1
-rw-r--r--hw/intc/nios2_iic.c6
-rw-r--r--hw/intc/ompic.c3
-rw-r--r--hw/intc/openpic_kvm.c6
-rw-r--r--hw/intc/pl190.c6
-rw-r--r--hw/intc/puv3_intc.c6
-rw-r--r--hw/intc/s390_flic_kvm.c6
-rw-r--r--hw/intc/slavio_intctl.c6
-rw-r--r--hw/intc/xilinx_intc.c1
20 files changed, 67 insertions, 32 deletions
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 38aabd60cd..e055bb3af2 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -28,6 +28,7 @@
#include "trace.h"
#include "hw/i386/apic-msidef.h"
#include "qapi/error.h"
+#include "qom/object.h"
#define MAX_APICS 255
#define MAX_APIC_WORDS 8
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 07b95143c9..6e5a2b8fe0 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -29,8 +29,10 @@
#include "kvm_arm.h"
#include "gic_internal.h"
#include "vgic_common.h"
+#include "qom/object.h"
#define TYPE_KVM_ARM_GIC "kvm-arm-gic"
+typedef struct KVMARMGICClass KVMARMGICClass;
#define KVM_ARM_GIC(obj) \
OBJECT_CHECK(GICState, (obj), TYPE_KVM_ARM_GIC)
#define KVM_ARM_GIC_CLASS(klass) \
@@ -38,11 +40,11 @@
#define KVM_ARM_GIC_GET_CLASS(obj) \
OBJECT_GET_CLASS(KVMARMGICClass, (obj), TYPE_KVM_ARM_GIC)
-typedef struct KVMARMGICClass {
+struct KVMARMGICClass {
ARMGICCommonClass parent_class;
DeviceRealize parent_realize;
void (*parent_reset)(DeviceState *dev);
-} KVMARMGICClass;
+};
void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
{
diff --git a/hw/intc/arm_gicv2m.c b/hw/intc/arm_gicv2m.c
index 0b7e2b4f84..8fb566d187 100644
--- a/hw/intc/arm_gicv2m.c
+++ b/hw/intc/arm_gicv2m.c
@@ -34,8 +34,10 @@
#include "sysemu/kvm.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "qom/object.h"
#define TYPE_ARM_GICV2M "arm-gicv2m"
+typedef struct ARMGICv2mState ARMGICv2mState;
#define ARM_GICV2M(obj) OBJECT_CHECK(ARMGICv2mState, (obj), TYPE_ARM_GICV2M)
#define GICV2M_NUM_SPI_MAX 128
@@ -48,7 +50,7 @@
#define PRODUCT_ID_QEMU 0x51 /* ASCII code Q */
-typedef struct ARMGICv2mState {
+struct ARMGICv2mState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@@ -56,7 +58,7 @@ typedef struct ARMGICv2mState {
uint32_t base_spi;
uint32_t num_spi;
-} ARMGICv2mState;
+};
static void gicv2m_set_irq(void *opaque, int irq)
{
diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c
index 46835ed085..631adc34b6 100644
--- a/hw/intc/arm_gicv3_its_kvm.c
+++ b/hw/intc/arm_gicv3_its_kvm.c
@@ -27,18 +27,20 @@
#include "sysemu/kvm.h"
#include "kvm_arm.h"
#include "migration/blocker.h"
+#include "qom/object.h"
#define TYPE_KVM_ARM_ITS "arm-its-kvm"
+typedef struct KVMARMITSClass KVMARMITSClass;
#define KVM_ARM_ITS(obj) OBJECT_CHECK(GICv3ITSState, (obj), TYPE_KVM_ARM_ITS)
#define KVM_ARM_ITS_CLASS(klass) \
OBJECT_CLASS_CHECK(KVMARMITSClass, (klass), TYPE_KVM_ARM_ITS)
#define KVM_ARM_ITS_GET_CLASS(obj) \
OBJECT_GET_CLASS(KVMARMITSClass, (obj), TYPE_KVM_ARM_ITS)
-typedef struct KVMARMITSClass {
+struct KVMARMITSClass {
GICv3ITSCommonClass parent_class;
void (*parent_reset)(DeviceState *dev);
-} KVMARMITSClass;
+};
static int kvm_its_send_msi(GICv3ITSState *s, uint32_t value, uint16_t devid)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index eddd07c743..5733936334 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -31,6 +31,7 @@
#include "gicv3_internal.h"
#include "vgic_common.h"
#include "migration/blocker.h"
+#include "qom/object.h"
#ifdef DEBUG_GICV3_KVM
#define DPRINTF(fmt, ...) \
@@ -41,6 +42,7 @@
#endif
#define TYPE_KVM_ARM_GICV3 "kvm-arm-gicv3"
+typedef struct KVMARMGICv3Class KVMARMGICv3Class;
#define KVM_ARM_GICV3(obj) \
OBJECT_CHECK(GICv3State, (obj), TYPE_KVM_ARM_GICV3)
#define KVM_ARM_GICV3_CLASS(klass) \
@@ -74,11 +76,11 @@
#define ICC_IGRPEN1_EL1 \
KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 7)
-typedef struct KVMARMGICv3Class {
+struct KVMARMGICv3Class {
ARMGICv3CommonClass parent_class;
DeviceRealize parent_realize;
void (*parent_reset)(DeviceState *dev);
-} KVMARMGICv3Class;
+};
static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
{
diff --git a/hw/intc/etraxfs_pic.c b/hw/intc/etraxfs_pic.c
index 12988c7aa9..cf4b3c5850 100644
--- a/hw/intc/etraxfs_pic.c
+++ b/hw/intc/etraxfs_pic.c
@@ -27,6 +27,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "qom/object.h"
#define D(x)
diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c
index 59dd27fb16..8e54f156c4 100644
--- a/hw/intc/exynos4210_combiner.c
+++ b/hw/intc/exynos4210_combiner.c
@@ -36,6 +36,7 @@
#include "hw/hw.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "qom/object.h"
//#define DEBUG_COMBINER
@@ -63,10 +64,11 @@ typedef struct CombinerGroupState {
} CombinerGroupState;
#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner"
+typedef struct Exynos4210CombinerState Exynos4210CombinerState;
#define EXYNOS4210_COMBINER(obj) \
OBJECT_CHECK(Exynos4210CombinerState, (obj), TYPE_EXYNOS4210_COMBINER)
-typedef struct Exynos4210CombinerState {
+struct Exynos4210CombinerState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@@ -77,7 +79,7 @@ typedef struct Exynos4210CombinerState {
uint32_t external; /* 1 means that this combiner is external */
qemu_irq output_irq[IIC_NGRP];
-} Exynos4210CombinerState;
+};
static const VMStateDescription vmstate_exynos4210_combiner_group_state = {
.name = "exynos4210.combiner.groupstate",
diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index 0aa3b843a9..ded31466ce 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -28,6 +28,7 @@
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/arm/exynos4210.h"
+#include "qom/object.h"
enum ExtGicId {
EXT_GIC_ID_MDMA_LCD0 = 66,
@@ -264,10 +265,11 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
/********* GIC part *********/
#define TYPE_EXYNOS4210_GIC "exynos4210.gic"
+typedef struct Exynos4210GicState Exynos4210GicState;
#define EXYNOS4210_GIC(obj) \
OBJECT_CHECK(Exynos4210GicState, (obj), TYPE_EXYNOS4210_GIC)
-typedef struct {
+struct Exynos4210GicState {
SysBusDevice parent_obj;
MemoryRegion cpu_container;
@@ -276,7 +278,7 @@ typedef struct {
MemoryRegion dist_alias[EXYNOS4210_NCPUS];
uint32_t num_cpu;
DeviceState *gic;
-} Exynos4210GicState;
+};
static void exynos4210_gic_set_irq(void *opaque, int irq, int level)
{
@@ -382,16 +384,17 @@ type_init(exynos4210_gic_register_types)
*/
#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
+typedef struct Exynos4210IRQGateState Exynos4210IRQGateState;
#define EXYNOS4210_IRQ_GATE(obj) \
OBJECT_CHECK(Exynos4210IRQGateState, (obj), TYPE_EXYNOS4210_IRQ_GATE)
-typedef struct Exynos4210IRQGateState {
+struct Exynos4210IRQGateState {
SysBusDevice parent_obj;
uint32_t n_in; /* inputs amount */
uint32_t *level; /* input levels */
qemu_irq out; /* output IRQ */
-} Exynos4210IRQGateState;
+};
static Property exynos4210_irq_gate_properties[] = {
DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c
index 794c643af2..5a60396390 100644
--- a/hw/intc/grlib_irqmp.c
+++ b/hw/intc/grlib_irqmp.c
@@ -35,6 +35,7 @@
#include "trace.h"
#include "qapi/error.h"
#include "qemu/module.h"
+#include "qom/object.h"
#define IRQMP_MAX_CPU 16
#define IRQMP_REG_SIZE 256 /* Size of memory mapped registers */
@@ -50,18 +51,19 @@
#define FORCE_OFFSET 0x80
#define EXTENDED_OFFSET 0xC0
+typedef struct IRQMP IRQMP;
#define GRLIB_IRQMP(obj) OBJECT_CHECK(IRQMP, (obj), TYPE_GRLIB_IRQMP)
typedef struct IRQMPState IRQMPState;
-typedef struct IRQMP {
+struct IRQMP {
SysBusDevice parent_obj;
MemoryRegion iomem;
IRQMPState *state;
qemu_irq irq;
-} IRQMP;
+};
struct IRQMPState {
uint32_t level;
diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c
index 51b27f6a34..9663207d34 100644
--- a/hw/intc/i8259.c
+++ b/hw/intc/i8259.c
@@ -30,6 +30,7 @@
#include "qemu/log.h"
#include "hw/isa/i8259_internal.h"
#include "trace.h"
+#include "qom/object.h"
/* debug PIC */
//#define DEBUG_PIC
@@ -37,6 +38,7 @@
//#define DEBUG_IRQ_LATENCY
#define TYPE_I8259 "isa-i8259"
+typedef struct PICClass PICClass;
#define PIC_CLASS(class) OBJECT_CLASS_CHECK(PICClass, (class), TYPE_I8259)
#define PIC_GET_CLASS(obj) OBJECT_GET_CLASS(PICClass, (obj), TYPE_I8259)
@@ -44,11 +46,11 @@
* PICClass:
* @parent_realize: The parent's realizefn.
*/
-typedef struct PICClass {
+struct PICClass {
PICCommonClass parent_class;
DeviceRealize parent_realize;
-} PICClass;
+};
#ifdef DEBUG_IRQ_LATENCY
static int64_t irq_time[16];
diff --git a/hw/intc/lm32_pic.c b/hw/intc/lm32_pic.c
index 36de670c9e..b08d9822ab 100644
--- a/hw/intc/lm32_pic.c
+++ b/hw/intc/lm32_pic.c
@@ -27,8 +27,10 @@
#include "hw/lm32/lm32_pic.h"
#include "hw/intc/intc.h"
#include "hw/irq.h"
+#include "qom/object.h"
#define TYPE_LM32_PIC "lm32-pic"
+typedef struct LM32PicState LM32PicState;
#define LM32_PIC(obj) OBJECT_CHECK(LM32PicState, (obj), TYPE_LM32_PIC)
struct LM32PicState {
@@ -42,7 +44,6 @@ struct LM32PicState {
/* statistics */
uint64_t stats_irq_count[32];
};
-typedef struct LM32PicState LM32PicState;
static void update_irq(LM32PicState *s)
{
diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c
index 23ca51cc2e..e11ca68647 100644
--- a/hw/intc/loongson_liointc.c
+++ b/hw/intc/loongson_liointc.c
@@ -23,6 +23,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "qom/object.h"
#define D(x)
diff --git a/hw/intc/nios2_iic.c b/hw/intc/nios2_iic.c
index 86d088f9b5..2594381a95 100644
--- a/hw/intc/nios2_iic.c
+++ b/hw/intc/nios2_iic.c
@@ -25,16 +25,18 @@
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "cpu.h"
+#include "qom/object.h"
#define TYPE_ALTERA_IIC "altera,iic"
+typedef struct AlteraIIC AlteraIIC;
#define ALTERA_IIC(obj) \
OBJECT_CHECK(AlteraIIC, (obj), TYPE_ALTERA_IIC)
-typedef struct AlteraIIC {
+struct AlteraIIC {
SysBusDevice parent_obj;
void *cpu;
qemu_irq parent_irq;
-} AlteraIIC;
+};
static void update_irq(AlteraIIC *pv)
{
diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c
index c354427a61..8dd763d6c5 100644
--- a/hw/intc/ompic.c
+++ b/hw/intc/ompic.c
@@ -15,8 +15,10 @@
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "exec/memory.h"
+#include "qom/object.h"
#define TYPE_OR1K_OMPIC "or1k-ompic"
+typedef struct OR1KOMPICState OR1KOMPICState;
#define OR1K_OMPIC(obj) OBJECT_CHECK(OR1KOMPICState, (obj), TYPE_OR1K_OMPIC)
#define OMPIC_CTRL_IRQ_ACK (1 << 31)
@@ -37,7 +39,6 @@
#define OMPIC_MAX_CPUS 4 /* Real max is much higher, but dont waste memory */
#define OMPIC_ADDRSPACE_SZ (OMPIC_MAX_CPUS * 2 * 4) /* 2 32-bit regs per cpu */
-typedef struct OR1KOMPICState OR1KOMPICState;
typedef struct OR1KOMPICCPUState OR1KOMPICCPUState;
struct OR1KOMPICCPUState {
diff --git a/hw/intc/openpic_kvm.c b/hw/intc/openpic_kvm.c
index e4bf47d885..3f5891a8a1 100644
--- a/hw/intc/openpic_kvm.c
+++ b/hw/intc/openpic_kvm.c
@@ -35,13 +35,15 @@
#include "sysemu/kvm.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "qom/object.h"
#define GCR_RESET 0x80000000
+typedef struct KVMOpenPICState KVMOpenPICState;
#define KVM_OPENPIC(obj) \
OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC)
-typedef struct KVMOpenPICState {
+struct KVMOpenPICState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@@ -51,7 +53,7 @@ typedef struct KVMOpenPICState {
uint32_t fd;
uint32_t model;
hwaddr mapped;
-} KVMOpenPICState;
+};
static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
{
diff --git a/hw/intc/pl190.c b/hw/intc/pl190.c
index e3bd3dd121..4f2aa58642 100644
--- a/hw/intc/pl190.c
+++ b/hw/intc/pl190.c
@@ -13,6 +13,7 @@
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "qom/object.h"
/* The number of virtual priority levels. 16 user vectors plus the
unvectored IRQ. Chained interrupts would require an additional level
@@ -21,9 +22,10 @@
#define PL190_NUM_PRIO 17
#define TYPE_PL190 "pl190"
+typedef struct PL190State PL190State;
#define PL190(obj) OBJECT_CHECK(PL190State, (obj), TYPE_PL190)
-typedef struct PL190State {
+struct PL190State {
SysBusDevice parent_obj;
MemoryRegion iomem;
@@ -41,7 +43,7 @@ typedef struct PL190State {
int prev_prio[PL190_NUM_PRIO];
qemu_irq irq;
qemu_irq fiq;
-} PL190State;
+};
static const unsigned char pl190_id[] =
{ 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };
diff --git a/hw/intc/puv3_intc.c b/hw/intc/puv3_intc.c
index 090d4839d1..3a8bc154ba 100644
--- a/hw/intc/puv3_intc.c
+++ b/hw/intc/puv3_intc.c
@@ -12,6 +12,7 @@
#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
+#include "qom/object.h"
#undef DEBUG_PUV3
#include "hw/unicore32/puv3.h"
@@ -19,9 +20,10 @@
#include "qemu/log.h"
#define TYPE_PUV3_INTC "puv3_intc"
+typedef struct PUV3INTCState PUV3INTCState;
#define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
-typedef struct PUV3INTCState {
+struct PUV3INTCState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@@ -29,7 +31,7 @@ typedef struct PUV3INTCState {
uint32_t reg_ICMR;
uint32_t reg_ICPR;
-} PUV3INTCState;
+};
/* Update interrupt status after enabled or pending bits have been changed. */
static void puv3_intc_update(PUV3INTCState *s)
diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c
index dbd4e682ce..c4ae10d978 100644
--- a/hw/intc/s390_flic_kvm.c
+++ b/hw/intc/s390_flic_kvm.c
@@ -24,6 +24,7 @@
#include "hw/s390x/css.h"
#include "migration/qemu-file-types.h"
#include "trace.h"
+#include "qom/object.h"
#define FLIC_SAVE_INITIAL_SIZE qemu_real_host_page_size
#define FLIC_FAILED (-1UL)
@@ -569,10 +570,11 @@ static const VMStateDescription kvm_s390_flic_vmstate = {
}
};
-typedef struct KVMS390FLICStateClass {
+struct KVMS390FLICStateClass {
S390FLICStateClass parent_class;
DeviceRealize parent_realize;
-} KVMS390FLICStateClass;
+};
+typedef struct KVMS390FLICStateClass KVMS390FLICStateClass;
#define KVM_S390_FLIC_GET_CLASS(obj) \
OBJECT_GET_CLASS(KVMS390FLICStateClass, (obj), TYPE_KVM_S390_FLIC)
diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c
index c4cf9096eb..7675556868 100644
--- a/hw/intc/slavio_intctl.c
+++ b/hw/intc/slavio_intctl.c
@@ -30,6 +30,7 @@
#include "hw/intc/intc.h"
#include "hw/irq.h"
#include "trace.h"
+#include "qom/object.h"
//#define DEBUG_IRQ_COUNT
@@ -58,10 +59,11 @@ typedef struct SLAVIO_CPUINTCTLState {
} SLAVIO_CPUINTCTLState;
#define TYPE_SLAVIO_INTCTL "slavio_intctl"
+typedef struct SLAVIO_INTCTLState SLAVIO_INTCTLState;
#define SLAVIO_INTCTL(obj) \
OBJECT_CHECK(SLAVIO_INTCTLState, (obj), TYPE_SLAVIO_INTCTL)
-typedef struct SLAVIO_INTCTLState {
+struct SLAVIO_INTCTLState {
SysBusDevice parent_obj;
MemoryRegion iomem;
@@ -73,7 +75,7 @@ typedef struct SLAVIO_INTCTLState {
uint32_t intregm_pending;
uint32_t intregm_disabled;
uint32_t target_cpu;
-} SLAVIO_INTCTLState;
+};
#define INTCTL_MAXADDR 0xf
#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 3e65e68619..ed1c2bcfb8 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -27,6 +27,7 @@
#include "qemu/module.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
+#include "qom/object.h"
#define D(x)
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-30 06:31:41 +0000