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-rw-r--r--hw/intc/apic.c6
-rw-r--r--hw/intc/openpic.c14
-rw-r--r--hw/intc/slavio_intctl.c2
-rw-r--r--hw/intc/xilinx_intc.c3
4 files changed, 13 insertions, 12 deletions
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index 361ae90b65..b8c061bdaa 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -201,12 +201,12 @@ static void apic_external_nmi(APICCommonState *s)
#define foreach_apic(apic, deliver_bitmask, code) \
{\
- int __i, __j, __mask;\
+ int __i, __j;\
for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
- __mask = deliver_bitmask[__i];\
+ uint32_t __mask = deliver_bitmask[__i];\
if (__mask) {\
for(__j = 0; __j < 32; __j++) {\
- if (__mask & (1 << __j)) {\
+ if (__mask & (1U << __j)) {\
apic = local_apics[__i * 32 + __j];\
if (apic) {\
code;\
diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c
index 7df72f44f0..be76fbd78f 100644
--- a/hw/intc/openpic.c
+++ b/hw/intc/openpic.c
@@ -123,7 +123,7 @@ static FslMpicInfo fsl_mpic_42 = {
#define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
#define IDR_EP_SHIFT 31
-#define IDR_EP_MASK (1 << IDR_EP_SHIFT)
+#define IDR_EP_MASK (1U << IDR_EP_SHIFT)
#define IDR_CI0_SHIFT 30
#define IDR_CI1_SHIFT 29
#define IDR_P1_SHIFT 1
@@ -220,17 +220,17 @@ typedef struct IRQSource {
} IRQSource;
#define IVPR_MASK_SHIFT 31
-#define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT)
+#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT)
#define IVPR_ACTIVITY_SHIFT 30
-#define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT)
+#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT)
#define IVPR_MODE_SHIFT 29
-#define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT)
+#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT)
#define IVPR_POLARITY_SHIFT 23
-#define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT)
+#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT)
#define IVPR_SENSE_SHIFT 22
-#define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT)
+#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT)
-#define IVPR_PRIORITY_MASK (0xF << 16)
+#define IVPR_PRIORITY_MASK (0xFU << 16)
#define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
#define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c
index 41a1672800..b10fb66b8d 100644
--- a/hw/intc/slavio_intctl.c
+++ b/hw/intc/slavio_intctl.c
@@ -272,7 +272,7 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
CPU_IRQ_TIMER_IN;
if (i == s->target_cpu) {
for (j = 0; j < 32; j++) {
- if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) {
+ if ((s->intregm_pending & (1U << j)) && intbit_to_level[j]) {
s->slaves[i].intreg_pending |= 1 << intbit_to_level[j];
}
}
diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 4a103988f3..1b228ff4e0 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -71,8 +71,9 @@ static void update_irq(struct xlx_pic *p)
/* Update the vector register. */
for (i = 0; i < 32; i++) {
- if (p->regs[R_IPR] & (1 << i))
+ if (p->regs[R_IPR] & (1U << i)) {
break;
+ }
}
if (i == 32)
i = ~0;