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-rw-r--r--hw/i386/kvm/ioapic.c12
-rw-r--r--hw/i386/pc.c4
-rw-r--r--hw/i386/x86.c1
3 files changed, 2 insertions, 15 deletions
diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c
index 8703f19b43..973e2b2af1 100644
--- a/hw/i386/kvm/ioapic.c
+++ b/hw/i386/kvm/ioapic.c
@@ -48,18 +48,6 @@ void kvm_pc_setup_irq_routing(bool pci_enabled)
}
}
-void kvm_pc_gsi_handler(void *opaque, int n, int level)
-{
- GSIState *s = opaque;
-
- if (n < ISA_NUM_IRQS) {
- /* Kernel will forward to both PIC and IOAPIC */
- qemu_set_irq(s->i8259_irq[n], level);
- } else {
- qemu_set_irq(s->ioapic_irq[n], level);
- }
-}
-
typedef struct KVMIOAPICState KVMIOAPICState;
struct KVMIOAPICState {
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index dff09e473a..ea7320b91b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -344,10 +344,8 @@ GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled)
s = g_new0(GSIState, 1);
if (kvm_ioapic_in_kernel()) {
kvm_pc_setup_irq_routing(pci_enabled);
- *irqs = qemu_allocate_irqs(kvm_pc_gsi_handler, s, GSI_NUM_PINS);
- } else {
- *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
}
+ *irqs = qemu_allocate_irqs(gsi_handler, s, GSI_NUM_PINS);
return s;
}
diff --git a/hw/i386/x86.c b/hw/i386/x86.c
index 80e33be1a2..d18a3ef03d 100644
--- a/hw/i386/x86.c
+++ b/hw/i386/x86.c
@@ -295,6 +295,7 @@ void gsi_handler(void *opaque, int n, int level)
trace_x86_gsi_interrupt(n, level);
if (n < ISA_NUM_IRQS) {
+ /* Under KVM, Kernel will forward to both PIC and IOAPIC */
qemu_set_irq(s->i8259_irq[n], level);
}
qemu_set_irq(s->ioapic_irq[n], level);