diff options
Diffstat (limited to 'hw/display')
| -rw-r--r-- | hw/display/ati.c | 10 | ||||
| -rw-r--r-- | hw/display/ati_int.h | 1 | ||||
| -rw-r--r-- | hw/display/ati_regs.h | 2 |
3 files changed, 12 insertions, 1 deletions
diff --git a/hw/display/ati.c b/hw/display/ati.c index f24c23fa89..cceb45b34a 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -90,7 +90,9 @@ static void ati_vga_switch_mode(ATIVGAState *s) DPRINTF("Switching to %dx%d %d %d @ %x\n", h, v, stride, bpp, offs); vbe_ioport_write_index(&s->vga, 0, VBE_DISPI_INDEX_ENABLE); vbe_ioport_write_data(&s->vga, 0, VBE_DISPI_DISABLED); - s->vga.big_endian_fb = false; + s->vga.big_endian_fb = (s->regs.config_cntl & APER_0_ENDIAN || + s->regs.config_cntl & APER_1_ENDIAN ? + true : false); /* reset VBE regs then set up mode */ s->vga.vbe_regs[VBE_DISPI_INDEX_XRES] = h; s->vga.vbe_regs[VBE_DISPI_INDEX_YRES] = v; @@ -310,6 +312,9 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) case PALETTE_DATA: val = vga_ioport_read(&s->vga, VGA_PEL_D); break; + case CNFG_CNTL: + val = s->regs.config_cntl; + break; case CNFG_MEMSIZE: val = s->vga.vram_size; break; @@ -604,6 +609,9 @@ static void ati_mm_write(void *opaque, hwaddr addr, data >>= 8; vga_ioport_write(&s->vga, VGA_PEL_D, data & 0xff); break; + case CNFG_CNTL: + s->regs.config_cntl = data; + break; case CRTC_H_TOTAL_DISP: s->regs.crtc_h_total_disp = data & 0x07ff07ff; break; diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h index 31a1927b3e..5b4d3be1e6 100644 --- a/hw/display/ati_int.h +++ b/hw/display/ati_int.h @@ -39,6 +39,7 @@ typedef struct ATIVGARegs { uint32_t gpio_vga_ddc; uint32_t gpio_dvi_ddc; uint32_t gpio_monid; + uint32_t config_cntl; uint32_t crtc_h_total_disp; uint32_t crtc_h_sync_strt_wid; uint32_t crtc_v_total_disp; diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h index 91947ab1e7..02046e97c2 100644 --- a/hw/display/ati_regs.h +++ b/hw/display/ati_regs.h @@ -317,6 +317,8 @@ #define X_MPLL_REF_DIV_MASK 0x000000FF /* Config control values (CONFIG_CNTL) */ +#define APER_0_ENDIAN 0x00000003 +#define APER_1_ENDIAN 0x0000000c #define CFG_VGA_IO_DIS 0x00000400 /* CRTC control values (CRTC_GEN_CNTL) */ |