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-rw-r--r--hw/char/omap_uart.c2
-rw-r--r--hw/char/serial-isa.c12
-rw-r--r--hw/char/serial-pci-multi.c55
-rw-r--r--hw/char/serial-pci.c18
-rw-r--r--hw/char/serial.c186
5 files changed, 212 insertions, 61 deletions
diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c
index 13e4f43c4c..e8da933378 100644
--- a/hw/char/omap_uart.c
+++ b/hw/char/omap_uart.c
@@ -27,7 +27,7 @@
struct omap_uart_s {
MemoryRegion iomem;
hwaddr base;
- SerialState *serial; /* TODO */
+ SerialMM *serial; /* TODO */
struct omap_target_agent_s *ta;
omap_clk fclk;
qemu_irq irq;
diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c
index 9e31c51bb6..db8644551e 100644
--- a/hw/char/serial-isa.c
+++ b/hw/char/serial-isa.c
@@ -73,9 +73,8 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp)
}
index++;
- s->baudbase = 115200;
isa_init_irq(isadev, &s->irq, isa->isairq);
- serial_realize_core(s, errp);
+ object_property_set_bool(OBJECT(s), true, "realized", errp);
qdev_set_legacy_instance_id(dev, isa->iobase, 3);
memory_region_init_io(&s->io, OBJECT(isa), &serial_io_ops, s, "serial", 8);
@@ -111,10 +110,19 @@ static void serial_isa_class_initfn(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
+static void serial_isa_initfn(Object *o)
+{
+ ISASerialState *self = ISA_SERIAL(o);
+
+ object_initialize_child(o, "serial", &self->state, sizeof(self->state),
+ TYPE_SERIAL, &error_abort, NULL);
+}
+
static const TypeInfo serial_isa_info = {
.name = TYPE_ISA_SERIAL,
.parent = TYPE_ISA_DEVICE,
.instance_size = sizeof(ISASerialState),
+ .instance_init = serial_isa_initfn,
.class_init = serial_isa_class_initfn,
};
diff --git a/hw/char/serial-pci-multi.c b/hw/char/serial-pci-multi.c
index 5f13b5663b..e343a1235c 100644
--- a/hw/char/serial-pci-multi.c
+++ b/hw/char/serial-pci-multi.c
@@ -56,7 +56,7 @@ static void multi_serial_pci_exit(PCIDevice *dev)
for (i = 0; i < pci->ports; i++) {
s = pci->state + i;
- serial_exit_core(s);
+ object_property_set_bool(OBJECT(s), false, "realized", NULL);
memory_region_del_subregion(&pci->iobar, &s->io);
g_free(pci->name[i]);
}
@@ -77,43 +77,43 @@ static void multi_serial_irq_mux(void *opaque, int n, int level)
pci_set_irq(&pci->dev, pending);
}
+static size_t multi_serial_get_port_count(PCIDeviceClass *pc)
+{
+ switch (pc->device_id) {
+ case 0x0003:
+ return 2;
+ case 0x0004:
+ return 4;
+ }
+
+ g_assert_not_reached();
+}
+
+
static void multi_serial_pci_realize(PCIDevice *dev, Error **errp)
{
PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
PCIMultiSerialState *pci = DO_UPCAST(PCIMultiSerialState, dev, dev);
SerialState *s;
Error *err = NULL;
- int i, nr_ports = 0;
-
- switch (pc->device_id) {
- case 0x0003:
- nr_ports = 2;
- break;
- case 0x0004:
- nr_ports = 4;
- break;
- }
- assert(nr_ports > 0);
- assert(nr_ports <= PCI_SERIAL_MAX_PORTS);
+ size_t i, nports = multi_serial_get_port_count(pc);
pci->dev.config[PCI_CLASS_PROG] = pci->prog_if;
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
- memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nr_ports);
+ memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * nports);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
- pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
- nr_ports);
+ pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci, nports);
- for (i = 0; i < nr_ports; i++) {
+ for (i = 0; i < nports; i++) {
s = pci->state + i;
- s->baudbase = 115200;
- serial_realize_core(s, &err);
+ object_property_set_bool(OBJECT(s), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
multi_serial_pci_exit(dev);
return;
}
s->irq = pci->irqs[i];
- pci->name[i] = g_strdup_printf("uart #%d", i + 1);
+ pci->name[i] = g_strdup_printf("uart #%zu", i + 1);
memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
pci->name[i], 8);
memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
@@ -180,10 +180,24 @@ static void multi_4x_serial_pci_class_initfn(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
+static void multi_serial_init(Object *o)
+{
+ PCIDevice *dev = PCI_DEVICE(o);
+ PCIMultiSerialState *pms = DO_UPCAST(PCIMultiSerialState, dev, dev);
+ size_t i, nports = multi_serial_get_port_count(PCI_DEVICE_GET_CLASS(dev));
+
+ for (i = 0; i < nports; i++) {
+ object_initialize_child(o, "serial[*]", &pms->state[i],
+ sizeof(pms->state[i]),
+ TYPE_SERIAL, &error_abort, NULL);
+ }
+}
+
static const TypeInfo multi_2x_serial_pci_info = {
.name = "pci-serial-2x",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIMultiSerialState),
+ .instance_init = multi_serial_init,
.class_init = multi_2x_serial_pci_class_initfn,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
@@ -195,6 +209,7 @@ static const TypeInfo multi_4x_serial_pci_info = {
.name = "pci-serial-4x",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCIMultiSerialState),
+ .instance_init = multi_serial_init,
.class_init = multi_4x_serial_pci_class_initfn,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
diff --git a/hw/char/serial-pci.c b/hw/char/serial-pci.c
index cb9b76e22b..b6a73c65a9 100644
--- a/hw/char/serial-pci.c
+++ b/hw/char/serial-pci.c
@@ -40,6 +40,8 @@ typedef struct PCISerialState {
uint8_t prog_if;
} PCISerialState;
+#define TYPE_PCI_SERIAL "pci-serial"
+#define PCI_SERIAL(s) OBJECT_CHECK(PCISerialState, (s), TYPE_PCI_SERIAL)
static void serial_pci_realize(PCIDevice *dev, Error **errp)
{
@@ -47,8 +49,7 @@ static void serial_pci_realize(PCIDevice *dev, Error **errp)
SerialState *s = &pci->state;
Error *err = NULL;
- s->baudbase = 115200;
- serial_realize_core(s, &err);
+ object_property_set_bool(OBJECT(s), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
@@ -67,7 +68,7 @@ static void serial_pci_exit(PCIDevice *dev)
PCISerialState *pci = DO_UPCAST(PCISerialState, dev, dev);
SerialState *s = &pci->state;
- serial_exit_core(s);
+ object_property_set_bool(OBJECT(s), false, "realized", NULL);
qemu_free_irq(s->irq);
}
@@ -103,10 +104,19 @@ static void serial_pci_class_initfn(ObjectClass *klass, void *data)
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
}
+static void serial_pci_init(Object *o)
+{
+ PCISerialState *ps = PCI_SERIAL(o);
+
+ object_initialize_child(o, "serial", &ps->state, sizeof(ps->state),
+ TYPE_SERIAL, &error_abort, NULL);
+}
+
static const TypeInfo serial_pci_info = {
- .name = "pci-serial",
+ .name = TYPE_PCI_SERIAL,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PCISerialState),
+ .instance_init = serial_pci_init,
.class_init = serial_pci_class_initfn,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
diff --git a/hw/char/serial.c b/hw/char/serial.c
index b4aa250950..6c327183c7 100644
--- a/hw/char/serial.c
+++ b/hw/char/serial.c
@@ -34,6 +34,7 @@
#include "sysemu/runstate.h"
#include "qemu/error-report.h"
#include "trace.h"
+#include "hw/qdev-properties.h"
//#define DEBUG_SERIAL
@@ -933,8 +934,10 @@ static int serial_be_change(void *opaque)
return 0;
}
-void serial_realize_core(SerialState *s, Error **errp)
+static void serial_realize(DeviceState *dev, Error **errp)
{
+ SerialState *s = SERIAL(dev);
+
s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
@@ -947,8 +950,10 @@ void serial_realize_core(SerialState *s, Error **errp)
serial_reset(s);
}
-void serial_exit_core(SerialState *s)
+static void serial_unrealize(DeviceState *dev, Error **errp)
{
+ SerialState *s = SERIAL(dev);
+
qemu_chr_fe_deinit(&s->chr, false);
timer_del(s->modem_status_poll);
@@ -980,40 +985,89 @@ const MemoryRegionOps serial_io_ops = {
.endianness = DEVICE_LITTLE_ENDIAN,
};
-SerialState *serial_init(int base, qemu_irq irq, int baudbase,
- Chardev *chr, MemoryRegion *system_io)
+static void serial_io_realize(DeviceState *dev, Error **errp)
{
- SerialState *s;
+ SerialIO *sio = SERIAL_IO(dev);
+ SerialState *s = &sio->serial;
+ Error *local_err = NULL;
+
+ object_property_set_bool(OBJECT(s), true, "realized", &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
+ sysbus_init_mmio(SYS_BUS_DEVICE(sio), &s->io);
+ sysbus_init_irq(SYS_BUS_DEVICE(sio), &s->irq);
+}
- s = g_malloc0(sizeof(SerialState));
+static void serial_io_class_init(ObjectClass *klass, void* data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
- s->irq = irq;
- s->baudbase = baudbase;
- qemu_chr_fe_init(&s->chr, chr, &error_abort);
- serial_realize_core(s, &error_fatal);
+ dc->realize = serial_io_realize;
+ /* No dc->vmsd: class has no migratable state */
+}
- vmstate_register(NULL, base, &vmstate_serial, s);
+static void serial_io_instance_init(Object *o)
+{
+ SerialIO *sio = SERIAL_IO(o);
- memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
- memory_region_add_subregion(system_io, base, &s->io);
+ object_initialize_child(o, "serial", &sio->serial, sizeof(sio->serial),
+ TYPE_SERIAL, &error_abort, NULL);
- return s;
+ qdev_alias_all_properties(DEVICE(&sio->serial), o);
}
+
+static const TypeInfo serial_io_info = {
+ .name = TYPE_SERIAL_IO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(SerialIO),
+ .instance_init = serial_io_instance_init,
+ .class_init = serial_io_class_init,
+};
+
+static Property serial_properties[] = {
+ DEFINE_PROP_CHR("chardev", SerialState, chr),
+ DEFINE_PROP_UINT32("baudbase", SerialState, baudbase, 115200),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void serial_class_init(ObjectClass *klass, void* data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ /* internal device for serialio/serialmm, not user-creatable */
+ dc->user_creatable = false;
+ dc->realize = serial_realize;
+ dc->unrealize = serial_unrealize;
+ dc->vmsd = &vmstate_serial;
+ dc->props = serial_properties;
+}
+
+static const TypeInfo serial_info = {
+ .name = TYPE_SERIAL,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(SerialState),
+ .class_init = serial_class_init,
+};
+
/* Memory mapped interface */
static uint64_t serial_mm_read(void *opaque, hwaddr addr,
unsigned size)
{
- SerialState *s = opaque;
- return serial_ioport_read(s, addr >> s->it_shift, 1);
+ SerialMM *s = SERIAL_MM(opaque);
+ return serial_ioport_read(&s->serial, addr >> s->regshift, 1);
}
static void serial_mm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- SerialState *s = opaque;
+ SerialMM *s = SERIAL_MM(opaque);
value &= 255;
- serial_ioport_write(s, addr >> s->it_shift, value, 1);
+ serial_ioport_write(&s->serial, addr >> s->regshift, value, 1);
}
static const MemoryRegionOps serial_mm_ops[3] = {
@@ -1040,25 +1094,89 @@ static const MemoryRegionOps serial_mm_ops[3] = {
},
};
-SerialState *serial_mm_init(MemoryRegion *address_space,
- hwaddr base, int it_shift,
- qemu_irq irq, int baudbase,
- Chardev *chr, enum device_endian end)
+static void serial_mm_realize(DeviceState *dev, Error **errp)
{
- SerialState *s;
+ SerialMM *smm = SERIAL_MM(dev);
+ SerialState *s = &smm->serial;
+ Error *local_err = NULL;
- s = g_malloc0(sizeof(SerialState));
+ object_property_set_bool(OBJECT(s), true, "realized", &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ memory_region_init_io(&s->io, NULL, &serial_mm_ops[smm->endianness], smm,
+ "serial", 8 << smm->regshift);
+ sysbus_init_mmio(SYS_BUS_DEVICE(smm), &s->io);
+ sysbus_init_irq(SYS_BUS_DEVICE(smm), &smm->serial.irq);
+}
+
+SerialMM *serial_mm_init(MemoryRegion *address_space,
+ hwaddr base, int regshift,
+ qemu_irq irq, int baudbase,
+ Chardev *chr, enum device_endian end)
+{
+ SerialMM *smm = SERIAL_MM(qdev_create(NULL, TYPE_SERIAL_MM));
+ MemoryRegion *mr;
- s->it_shift = it_shift;
- s->irq = irq;
- s->baudbase = baudbase;
- qemu_chr_fe_init(&s->chr, chr, &error_abort);
+ qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift);
+ qdev_prop_set_uint32(DEVICE(smm), "baudbase", baudbase);
+ qdev_prop_set_chr(DEVICE(smm), "chardev", chr);
+ qdev_set_legacy_instance_id(DEVICE(smm), base, 2);
+ qdev_prop_set_uint8(DEVICE(smm), "endianness", end);
+ qdev_init_nofail(DEVICE(smm));
- serial_realize_core(s, &error_fatal);
- vmstate_register(NULL, base, &vmstate_serial, s);
+ sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq);
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0);
+ memory_region_add_subregion(address_space, base, mr);
- memory_region_init_io(&s->io, NULL, &serial_mm_ops[end], s,
- "serial", 8 << it_shift);
- memory_region_add_subregion(address_space, base, &s->io);
- return s;
+ return smm;
}
+
+static void serial_mm_instance_init(Object *o)
+{
+ SerialMM *smm = SERIAL_MM(o);
+
+ object_initialize_child(o, "serial", &smm->serial, sizeof(smm->serial),
+ TYPE_SERIAL, &error_abort, NULL);
+
+ qdev_alias_all_properties(DEVICE(&smm->serial), o);
+}
+
+static Property serial_mm_properties[] = {
+ /*
+ * Set the spacing between adjacent memory-mapped UART registers.
+ * Each register will be at (1 << regshift) bytes after the
+ * previous one.
+ */
+ DEFINE_PROP_UINT8("regshift", SerialMM, regshift, 0),
+ DEFINE_PROP_UINT8("endianness", SerialMM, endianness, DEVICE_NATIVE_ENDIAN),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void serial_mm_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->props = serial_mm_properties;
+ dc->realize = serial_mm_realize;
+}
+
+static const TypeInfo serial_mm_info = {
+ .name = TYPE_SERIAL_MM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .class_init = serial_mm_class_init,
+ .instance_init = serial_mm_instance_init,
+ .instance_size = sizeof(SerialMM),
+ .class_init = serial_mm_class_init,
+};
+
+static void serial_register_types(void)
+{
+ type_register_static(&serial_info);
+ type_register_static(&serial_io_info);
+ type_register_static(&serial_mm_info);
+}
+
+type_init(serial_register_types)