aboutsummaryrefslogtreecommitdiff
path: root/hw/arm
diff options
context:
space:
mode:
Diffstat (limited to 'hw/arm')
-rw-r--r--hw/arm/allwinner-a10.c3
-rw-r--r--hw/arm/cubieboard.c3
-rw-r--r--hw/arm/digic.c3
-rw-r--r--hw/arm/exynos4_boards.c4
-rw-r--r--hw/arm/fsl-imx25.c4
-rw-r--r--hw/arm/fsl-imx31.c4
-rw-r--r--hw/arm/fsl-imx6.c3
-rw-r--r--hw/arm/fsl-imx6ul.c2
-rw-r--r--hw/arm/mcimx7d-sabre.c9
-rw-r--r--hw/arm/mps2-tz.c15
-rw-r--r--hw/arm/musca.c9
-rw-r--r--hw/arm/smmuv3-internal.h1
-rw-r--r--hw/arm/smmuv3.c18
-rw-r--r--hw/arm/xlnx-zynqmp.c8
14 files changed, 49 insertions, 37 deletions
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 73810a4440..118032c8c7 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -30,7 +30,8 @@ static void aw_a10_init(Object *obj)
AwA10State *s = AW_A10(obj);
object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
- "cortex-a8-" TYPE_ARM_CPU, &error_abort, NULL);
+ ARM_CPU_TYPE_NAME("cortex-a8"),
+ &error_abort, NULL);
sysbus_init_child_obj(obj, "intc", &s->intc, sizeof(s->intc),
TYPE_AW_A10_PIC);
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 1bef3cb9af..6dc2f1d6b6 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -78,7 +78,8 @@ static void cubieboard_init(MachineState *machine)
static void cubieboard_machine_init(MachineClass *mc)
{
- mc->desc = "cubietech cubieboard";
+ mc->desc = "cubietech cubieboard (Cortex-A9)";
+ mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
mc->init = cubieboard_init;
mc->block_default_type = IF_IDE;
mc->units_per_default_bus = 1;
diff --git a/hw/arm/digic.c b/hw/arm/digic.c
index 4f52465875..22434a65a2 100644
--- a/hw/arm/digic.c
+++ b/hw/arm/digic.c
@@ -37,7 +37,8 @@ static void digic_init(Object *obj)
int i;
object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
- "arm946-" TYPE_ARM_CPU, &error_abort, NULL);
+ ARM_CPU_TYPE_NAME("arm946"),
+ &error_abort, NULL);
for (i = 0; i < DIGIC4_NB_TIMERS; i++) {
#define DIGIC_TIMER_NAME_MLEN 11
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index be21f50387..09da52876d 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -128,8 +128,8 @@ exynos4_boards_init_common(MachineState *machine,
exynos4_boards_init_ram(s, get_system_memory(),
exynos4_board_ram_size[board_type]);
- object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
- qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
+ sysbus_init_child_obj(OBJECT(machine), "soc",
+ &s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
object_property_set_bool(OBJECT(&s->soc), true, "realized",
&error_fatal);
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index 532d088298..3cb5a8fdfd 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -36,7 +36,9 @@ static void fsl_imx25_init(Object *obj)
FslIMX25State *s = FSL_IMX25(obj);
int i;
- object_initialize(&s->cpu, sizeof(s->cpu), "arm926-" TYPE_ARM_CPU);
+ object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
+ ARM_CPU_TYPE_NAME("arm926"),
+ &error_abort, NULL);
sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
TYPE_IMX_AVIC);
diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index 1a37a7b997..55e90d104b 100644
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -33,7 +33,9 @@ static void fsl_imx31_init(Object *obj)
FslIMX31State *s = FSL_IMX31(obj);
int i;
- object_initialize(&s->cpu, sizeof(s->cpu), "arm1136-" TYPE_ARM_CPU);
+ object_initialize_child(obj, "cpu", &s->cpu, sizeof(s->cpu),
+ ARM_CPU_TYPE_NAME("arm1136"),
+ &error_abort, NULL);
sysbus_init_child_obj(obj, "avic", &s->avic, sizeof(s->avic),
TYPE_IMX_AVIC);
diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index 8c397ef04b..552145b24e 100644
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -43,7 +43,8 @@ static void fsl_imx6_init(Object *obj)
for (i = 0; i < MIN(ms->smp.cpus, FSL_IMX6_NUM_CPUS); i++) {
snprintf(name, NAME_SIZE, "cpu%d", i);
object_initialize_child(obj, name, &s->cpu[i], sizeof(s->cpu[i]),
- "cortex-a9-" TYPE_ARM_CPU, &error_abort, NULL);
+ ARM_CPU_TYPE_NAME("cortex-a9"),
+ &error_abort, NULL);
}
sysbus_init_child_obj(obj, "a9mpcore", &s->a9mpcore, sizeof(s->a9mpcore),
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
index b074177a71..c405b68d1d 100644
--- a/hw/arm/fsl-imx6ul.c
+++ b/hw/arm/fsl-imx6ul.c
@@ -34,7 +34,7 @@ static void fsl_imx6ul_init(Object *obj)
int i;
object_initialize_child(obj, "cpu0", &s->cpu, sizeof(s->cpu),
- "cortex-a7-" TYPE_ARM_CPU, &error_abort, NULL);
+ ARM_CPU_TYPE_NAME("cortex-a7"), &error_abort, NULL);
/*
* A7MPCORE
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 2df2223611..0d1f62d30a 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -30,7 +30,6 @@ static void mcimx7d_sabre_init(MachineState *machine)
{
static struct arm_boot_info boot_info;
MCIMX7Sabre *s = g_new0(MCIMX7Sabre, 1);
- Object *soc;
int i;
if (machine->ram_size > FSL_IMX7_MMDC_SIZE) {
@@ -46,10 +45,10 @@ static void mcimx7d_sabre_init(MachineState *machine)
.nb_cpus = machine->smp.cpus,
};
- object_initialize(&s->soc, sizeof(s->soc), TYPE_FSL_IMX7);
- soc = OBJECT(&s->soc);
- object_property_add_child(OBJECT(machine), "soc", soc, &error_fatal);
- object_property_set_bool(soc, true, "realized", &error_fatal);
+ object_initialize_child(OBJECT(machine), "soc",
+ &s->soc, sizeof(s->soc),
+ TYPE_FSL_IMX7, &error_fatal, NULL);
+ object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal);
memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram",
machine->ram_size);
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index d85dc2c4bd..6b24aaacde 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -427,10 +427,10 @@ static void mps2tz_common_init(MachineState *machine)
/* The sec_resp_cfg output from the IoTKit must be split into multiple
* lines, one for each of the PPCs we create here, plus one per MSC.
*/
- object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
- TYPE_SPLIT_IRQ);
- object_property_add_child(OBJECT(machine), "sec-resp-splitter",
- OBJECT(&mms->sec_resp_splitter), &error_abort);
+ object_initialize_child(OBJECT(machine), "sec-resp-splitter",
+ &mms->sec_resp_splitter,
+ sizeof(mms->sec_resp_splitter),
+ TYPE_SPLIT_IRQ, &error_abort, NULL);
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
ARRAY_SIZE(mms->ppc) + ARRAY_SIZE(mms->msc),
"num-lines", &error_fatal);
@@ -465,10 +465,9 @@ static void mps2tz_common_init(MachineState *machine)
* Tx, Rx and "combined" IRQs are sent to the NVIC separately.
* Create the OR gate for this.
*/
- object_initialize(&mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
- TYPE_OR_IRQ);
- object_property_add_child(OBJECT(mms), "uart-irq-orgate",
- OBJECT(&mms->uart_irq_orgate), &error_abort);
+ object_initialize_child(OBJECT(mms), "uart-irq-orgate",
+ &mms->uart_irq_orgate, sizeof(mms->uart_irq_orgate),
+ TYPE_OR_IRQ, &error_abort, NULL);
object_property_set_int(OBJECT(&mms->uart_irq_orgate), 10, "num-lines",
&error_fatal);
object_property_set_bool(OBJECT(&mms->uart_irq_orgate), true,
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index ddd8842732..68db4b5b38 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -424,10 +424,11 @@ static void musca_init(MachineState *machine)
* The sec_resp_cfg output from the SSE-200 must be split into multiple
* lines, one for each of the PPCs we create here.
*/
- object_initialize(&mms->sec_resp_splitter, sizeof(mms->sec_resp_splitter),
- TYPE_SPLIT_IRQ);
- object_property_add_child(OBJECT(machine), "sec-resp-splitter",
- OBJECT(&mms->sec_resp_splitter), &error_fatal);
+ object_initialize_child(OBJECT(machine), "sec-resp-splitter",
+ &mms->sec_resp_splitter,
+ sizeof(mms->sec_resp_splitter),
+ TYPE_SPLIT_IRQ, &error_fatal, NULL);
+
object_property_set_int(OBJECT(&mms->sec_resp_splitter),
ARRAY_SIZE(mms->ppc), "num-lines", &error_fatal);
object_property_set_bool(OBJECT(&mms->sec_resp_splitter), true,
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index b160289cd1..d190181ef1 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -381,6 +381,7 @@ typedef struct SMMUEventInfo {
uint32_t sid;
bool recorded;
bool record_trans_faults;
+ bool inval_ste_allowed;
union {
struct {
uint32_t ssid;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 2eaf07fb5f..db051dcac8 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -320,6 +320,9 @@ static int decode_ste(SMMUv3State *s, SMMUTransCfg *cfg,
uint32_t config;
if (!STE_VALID(ste)) {
+ if (!event->inval_ste_allowed) {
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid STE\n");
+ }
goto bad_ste;
}
@@ -406,8 +409,10 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste,
if (!span) {
/* l2ptr is not valid */
- qemu_log_mask(LOG_GUEST_ERROR,
- "invalid sid=%d (L1STD span=0)\n", sid);
+ if (!event->inval_ste_allowed) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "invalid sid=%d (L1STD span=0)\n", sid);
+ }
event->type = SMMU_EVT_C_BAD_STREAMID;
return -EINVAL;
}
@@ -602,7 +607,9 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
SMMUv3State *s = sdev->smmu;
uint32_t sid = smmu_get_sid(sdev);
- SMMUEventInfo event = {.type = SMMU_EVT_NONE, .sid = sid};
+ SMMUEventInfo event = {.type = SMMU_EVT_NONE,
+ .sid = sid,
+ .inval_ste_allowed = false};
SMMUPTWEventInfo ptw_info = {};
SMMUTranslationStatus status;
SMMUState *bs = ARM_SMMU(s);
@@ -795,16 +802,13 @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,
dma_addr_t iova)
{
SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);
- SMMUEventInfo event = {};
+ SMMUEventInfo event = {.inval_ste_allowed = true};
SMMUTransTableInfo *tt;
SMMUTransCfg *cfg;
IOMMUTLBEntry entry;
cfg = smmuv3_get_config(sdev, &event);
if (!cfg) {
- qemu_log_mask(LOG_GUEST_ERROR,
- "%s error decoding the configuration for iommu mr=%s\n",
- __func__, mr->parent_obj.name);
return;
}
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 0f587e63d3..fb03c60ebb 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -196,8 +196,8 @@ static void xlnx_zynqmp_create_rpu(MachineState *ms, XlnxZynqMPState *s,
object_initialize_child(OBJECT(&s->rpu_cluster), "rpu-cpu[*]",
&s->rpu_cpu[i], sizeof(s->rpu_cpu[i]),
- "cortex-r5f-" TYPE_ARM_CPU, &error_abort,
- NULL);
+ ARM_CPU_TYPE_NAME("cortex-r5f"),
+ &error_abort, NULL);
name = object_get_canonical_path_component(OBJECT(&s->rpu_cpu[i]));
if (strcmp(name, boot_cpu)) {
@@ -237,8 +237,8 @@ static void xlnx_zynqmp_init(Object *obj)
for (i = 0; i < num_apus; i++) {
object_initialize_child(OBJECT(&s->apu_cluster), "apu-cpu[*]",
&s->apu_cpu[i], sizeof(s->apu_cpu[i]),
- "cortex-a53-" TYPE_ARM_CPU, &error_abort,
- NULL);
+ ARM_CPU_TYPE_NAME("cortex-a53"),
+ &error_abort, NULL);
}
sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-02 13:59:00 +0000