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-rw-r--r--hw/arm/exynos4210.c6
1 files changed, 1 insertions, 5 deletions
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index ee1438a0f4..e8e1d81e62 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -169,15 +169,11 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
Exynos4210State *s = g_new(Exynos4210State, 1);
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
SysBusDevice *busdev;
- ObjectClass *cpu_oc;
DeviceState *dev;
int i, n;
- cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, "cortex-a9");
- assert(cpu_oc);
-
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
- Object *cpuobj = object_new(object_class_get_name(cpu_oc));
+ Object *cpuobj = object_new(ARM_CPU_TYPE_NAME("cortex-a9"));
/* By default A9 CPUs have EL3 enabled. This board does not currently
* support EL3 so the CPU EL3 property is disabled before realization.