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-rw-r--r--fpu/softfloat-specialize.c.inc26
1 files changed, 26 insertions, 0 deletions
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
index efbd163a2b..dc4ea33c09 100644
--- a/fpu/softfloat-specialize.c.inc
+++ b/fpu/softfloat-specialize.c.inc
@@ -586,6 +586,32 @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
} else {
return 1;
}
+#elif defined(TARGET_XTENSA)
+ /*
+ * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
+ * an input NaN if we have one (ie c).
+ */
+ if (infzero) {
+ float_raise(float_flag_invalid, status);
+ return 2;
+ }
+ if (status->use_first_nan) {
+ if (is_nan(a_cls)) {
+ return 0;
+ } else if (is_nan(b_cls)) {
+ return 1;
+ } else {
+ return 2;
+ }
+ } else {
+ if (is_nan(c_cls)) {
+ return 2;
+ } else if (is_nan(b_cls)) {
+ return 1;
+ } else {
+ return 0;
+ }
+ }
#else
/* A default implementation: prefer a to b to c.
* This is unlikely to actually match any real implementation.