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-rw-r--r--cputlb.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/cputlb.c b/cputlb.c
index 0eb1801cc2..6b2cdb201a 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -106,7 +106,7 @@ void tlb_flush_page(CPUArchState *env, target_ulong addr)
tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
}
- tb_flush_jmp_cache(env, addr);
+ tb_flush_jmp_cache(cpu, addr);
}
/* update the TLBs so that writes to code in the virtual page 'addr'