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-rw-r--r--accel/tcg/cputlb.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 6c83878f73..f64c6b1c75 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -906,7 +906,8 @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
- r = memory_region_dispatch_read(mr, mr_offset, &val, size_memop(size),
+ r = memory_region_dispatch_read(mr, mr_offset, &val,
+ size_memop(size) | MO_TE,
iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
@@ -947,7 +948,8 @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
qemu_mutex_lock_iothread();
locked = true;
}
- r = memory_region_dispatch_write(mr, mr_offset, val, size_memop(size),
+ r = memory_region_dispatch_write(mr, mr_offset, val,
+ size_memop(size) | MO_TE,
iotlbentry->attrs);
if (r != MEMTX_OK) {
hwaddr physaddr = mr_offset +
@@ -1305,6 +1307,7 @@ load_helper(CPUArchState *env, target_ulong addr, TCGMemOpIdx oi,
}
}
+ /* TODO: Merge bswap into io_readx -> memory_region_dispatch_read. */
res = io_readx(env, &env_tlb(env)->d[mmu_idx].iotlb[index],
mmu_idx, addr, retaddr, access_type, size);
return handle_bswap(res, size, big_endian);
@@ -1553,6 +1556,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
}
}
+ /* TODO: Merge bswap into io_writex -> memory_region_dispatch_write. */
io_writex(env, &env_tlb(env)->d[mmu_idx].iotlb[index], mmu_idx,
handle_bswap(val, size, big_endian),
addr, retaddr, size);