+#

+# Emacs: you need https://github.com/10sr/editorconfig-custom-majormode-el

+# to automatically enable the appropriate major-mode for your files

+# that aren't already caught by your existing config.

+#

+emacs_mode = makefile

+emacs_mode = makefile

+emacs_mode = c

+emacs_mode = asm

+emacs_mode = glsl

+emacs_mode = python

+ - if test -n "$LD_JOBS";

+ then

+ meson configure . -Dbackend_max_links="$LD_JOBS" ;

+ fi || exit 1;

+# Set LD_JOBS=1 because this requires LTO and ld consumes a large amount of memory.

+# On gitlab runners, default value sometimes end up calling 2 lds concurrently and

+# triggers an Out-Of-Memory error

+#

+# Since slirp callbacks are used in QEMU Timers, slirp needs to be compiled together

+# with QEMU and linked as a static library to avoid false positives in CFI checks.

+# This can be accomplished by using -enable-slirp=git, which avoids the use of

+# a system-wide version of the library

+#

+# Split in three sets of build/check/acceptance to limit the execution time of each

+# job

+build-cfi-aarch64:

+ <<: *native_build_job_definition

+ needs:

+ - job: amd64-fedora-container

+ variables:

+ LD_JOBS: 1

+ AR: llvm-ar

+ IMAGE: fedora

+ CONFIGURE_ARGS: --cc=clang --cxx=clang++ --enable-cfi --enable-cfi-debug

+ --enable-safe-stack --enable-slirp=git

+ TARGETS: aarch64-softmmu

+ MAKE_CHECK_ARGS: check-build

+ artifacts:

+ expire_in: 2 days

+ paths:

+ - build

+

+check-cfi-aarch64:

+ <<: *native_test_job_definition

+ needs:

+ - job: build-cfi-aarch64

+ artifacts: true

+ variables:

+ IMAGE: fedora

+ MAKE_CHECK_ARGS: check

+

+acceptance-cfi-aarch64:

+ <<: *native_test_job_definition

+ needs:

+ - job: build-cfi-aarch64

+ artifacts: true

+ variables:

+ IMAGE: fedora

+ MAKE_CHECK_ARGS: check-acceptance

+ <<: *acceptance_definition

+

+build-cfi-ppc64-s390x:

+ <<: *native_build_job_definition

+ needs:

+ - job: amd64-fedora-container

+ variables:

+ LD_JOBS: 1

+ AR: llvm-ar

+ IMAGE: fedora

+ CONFIGURE_ARGS: --cc=clang --cxx=clang++ --enable-cfi --enable-cfi-debug

+ --enable-safe-stack --enable-slirp=git

+ TARGETS: ppc64-softmmu s390x-softmmu

+ MAKE_CHECK_ARGS: check-build

+ artifacts:

+ expire_in: 2 days

+ paths:

+ - build

+

+check-cfi-ppc64-s390x:

+ <<: *native_test_job_definition

+ needs:

+ - job: build-cfi-ppc64-s390x

+ artifacts: true

+ variables:

+ IMAGE: fedora

+ MAKE_CHECK_ARGS: check

+

+acceptance-cfi-ppc64-s390x:

+ <<: *native_test_job_definition

+ needs:

+ - job: build-cfi-ppc64-s390x

+ artifacts: true

+ variables:

+ IMAGE: fedora

+ MAKE_CHECK_ARGS: check-acceptance

+ <<: *acceptance_definition

+

+build-cfi-x86_64:

+ <<: *native_build_job_definition

+ needs:

+ - job: amd64-fedora-container

+ variables:

+ LD_JOBS: 1

+ AR: llvm-ar

+ IMAGE: fedora

+ CONFIGURE_ARGS: --cc=clang --cxx=clang++ --enable-cfi --enable-cfi-debug

+ --enable-safe-stack --enable-slirp=git

+ TARGETS: x86_64-softmmu

+ MAKE_CHECK_ARGS: check-build

+ artifacts:

+ expire_in: 2 days

+ paths:

+ - build

+

+check-cfi-x86_64:

+ <<: *native_test_job_definition

+ needs:

+ - job: build-cfi-x86_64

+ artifacts: true

+ variables:

+ IMAGE: fedora

+ MAKE_CHECK_ARGS: check

+

+acceptance-cfi-x86_64:

+ <<: *native_test_job_definition

+ needs:

+ - job: build-cfi-x86_64

+ artifacts: true

+ variables:

+ IMAGE: fedora

+ MAKE_CHECK_ARGS: check-acceptance

+ <<: *acceptance_definition

+

+source semihosting/Kconfig

+F: docs/tools/virtfs-proxy-helper.rst

+F: docs/tools/virtiofsd.rst

+F: docs/system/generic-loader.rst

+

+Guest Loader

+M: Alex Bennée <alex.bennee@linaro.org>

+S: Maintained

+F: hw/core/guest-loader.c

+F: docs/system/guest-loader.rst

+F: tests/acceptance/boot_xen.py

+F: docs/tools/qemu-img.rst

+F: docs/tools/qemu-trace-stap.rst

+M: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>

+F: docs/tools/qemu-nbd.rst

+T: git https://src.openvz.org/scm/~vsementsov/qemu.git nbd

+F: semihosting/

+F: include/semihosting/

+ } else if (mc->kvm_type) {

+ type = mc->kvm_type(ms, NULL);

+static void xen_change_state_handler(void *opaque, bool running,

+static void audio_vm_change_state_handler (void *opaque, bool running,

+ if (bytes_read != len) {

+ error_report("%s: Short read", __func__);

+ return -1;

+ }

+ ret = bdrv_set_backing_hd(bs, backing_hd, errp);

+ if (ret < 0) {

+ false, errp);

+ if (!bs->file) {

+ errp);

+ if (!bs->file) {

+ BDRV_CHILD_METADATA, false, errp);

+ if (!s->log_file) {

+ false, errp);

+ if (!bs->file) {

+ false, errp);

+ if (!bs->file) {

+ false, errp);

+ if (!s->test_file) {

+static void blk_vm_state_changed(void *opaque, bool running, RunState state)

+ BlockJob *job;

+ job = mirror_start_job(

+ errp);

+ if (!job) {

+ return job;

+/*

+ * Return true on success, false on failure.

+ * If header_updated is not NULL then it is set appropriately regardless of

+ * the return value.

+bool qcow2_load_dirty_bitmaps(BlockDriverState *bs, bool *header_updated,

+ Error **errp)

+ if (header_updated) {

+ *header_updated = false;

+ }

+

+ return true;

+ if (header_updated) {

+ *header_updated = true;

+ }

+ return true;

+ * On success return true with info_list set (note, that if there are no

+ * bitmaps, info_list is set to NULL).

+ * On failure return false with errp set.

+bool qcow2_get_bitmap_info_list(BlockDriverState *bs,

+ Qcow2BitmapInfoList **info_list, Error **errp)

+ Qcow2BitmapInfoList **tail;

+ *info_list = NULL;

+ return true;

+ if (!bm_list) {

+ return false;

+ *info_list = NULL;

+ tail = info_list;

+

+ return true;

+bool qcow2_store_persistent_dirty_bitmaps(BlockDriverState *bs,

+ ERRP_GUARD();

+ return false;

+ return true;

+ return false;

+ if (!qcow2_store_persistent_dirty_bitmaps(bs, false, errp)) {

+static bool read_cache_sizes(BlockDriverState *bs, QemuOpts *opts,

+ return false;

+ return false;

+ return false;

+ return false;

+

+ return true;

+ if (!read_cache_sizes(bs, opts, &l2_cache_size, &l2_cache_entry_size,

+ &refcount_cache_size, errp)) {

+ if (!r->crypto_opts) {

+ ret = -EINVAL;

+ goto fail;

+ }

+ if (!r->crypto_opts) {

+ ret = -EINVAL;

+ goto fail;

+ }

+ ERRP_GUARD();

+ true, errp);

+ if (*errp) {

+ bool header_updated;

+ if (!qcow2_load_dirty_bitmaps(bs, &header_updated, errp)) {

+ ERRP_GUARD();

+ ret = qcow2_do_open(bs, options, flags, errp);

+ if (ret < 0) {

+ error_prepend(errp, "Could not reopen qcow2 layer: ");

+ encrypt_info = qcrypto_block_get_info(s->crypto, errp);

+ if (!encrypt_info) {

+ if (!qcow2_get_bitmap_info_list(bs, &bitmaps, errp)) {

+bool qcow2_load_dirty_bitmaps(BlockDriverState *bs, bool *header_updated,

+ Error **errp);

+bool qcow2_get_bitmap_info_list(BlockDriverState *bs,

+ Qcow2BitmapInfoList **info_list, Error **errp);

+bool qcow2_store_persistent_dirty_bitmaps(BlockDriverState *bs,

+ error_setg(errp, "Failed to read QED header");

+ error_setg(errp, "QED cluster size is invalid");

+ error_setg(errp, "Failed to get file length");

+ error_setg(errp, "QED table size is invalid");

+ error_setg(errp, "QED image size is invalid");

+ error_setg(errp, "QED table offset is invalid");

+ error_setg(errp, "QED header size is too large");

+ error_setg(errp, "QED backing filename offset is invalid");

+ error_setg(errp, "Failed to read backing filename");

+ error_setg(errp, "Failed to update header");

+ error_setg(errp, "Failed to read L1 table");

+ error_setg(errp, "Image corrupted");

+ ret = bdrv_qed_do_open(bs, NULL, bs->open_flags, errp);

+ if (ret < 0) {

+ error_prepend(errp, "Could not reopen qed layer: ");

+ errp);

+ if (!s->children[i]) {

+ if (bdrv_set_backing_hd(target_bs, source, errp) < 0) {

+bool block_job_set_speed(BlockJob *job, int64_t speed, Error **errp)

+ if (job_apply_verb(&job->job, JOB_VERB_SET_SPEED, errp) < 0) {

+ return false;

+ return false;

+ return true;

+

+ return true;

+ if (!block_job_set_speed(job, speed, errp)) {

+CONFIG_LM32_EVR=y

+ dis = "ASE attribute mismatch";

+ * Tachometer

+- XRAM (4MB of on chip Accelerator RAM)

+hexadecimal sizes with scaling multipliers (since 6.0)

+''''''''''''''''''''''''''''''''''''''''''''''''''''''

+

+Input parameters that take a size value should only use a size suffix

+(such as 'k' or 'M') when the base is written in decimal, and not when

+the value is hexadecimal. That is, '0x20M' is deprecated, and should

+be written either as '32M' or as '0x2000000'.

+

+..

+ Copyright (c) 2016, Xilinx Inc.

+

+This work is licensed under the terms of the GNU GPL, version 2 or later. See

+the COPYING file in the top-level directory.

+

+Generic Loader

+--------------

+

+The 'loader' device allows the user to load multiple images or values into

+QEMU at startup.

+

+Loading Data into Memory Values

+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

+The loader device allows memory values to be set from the command line. This

+can be done by following the syntax below::

+

+ -device loader,addr=<addr>,data=<data>,data-len=<data-len> \

+ [,data-be=<data-be>][,cpu-num=<cpu-num>]

+

+``<addr>``

+ The address to store the data in.

+

+``<data>``

+ The value to be written to the address. The maximum size of the data

+ is 8 bytes.

+

+``<data-len>``

+ The length of the data in bytes. This argument must be included if

+ the data argument is.

+

+``<data-be>``

+ Set to true if the data to be stored on the guest should be written

+ as big endian data. The default is to write little endian data.

+

+``<cpu-num>``

+ The number of the CPU's address space where the data should be

+ loaded. If not specified the address space of the first CPU is used.

+

+All values are parsed using the standard QemuOps parsing. This allows the user

+to specify any values in any format supported. By default the values

+will be parsed as decimal. To use hex values the user should prefix the number

+with a '0x'.

+

+An example of loading value 0x8000000e to address 0xfd1a0104 is::

+

+ -device loader,addr=0xfd1a0104,data=0x8000000e,data-len=4

+

+Setting a CPU's Program Counter

+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

+

+The loader device allows the CPU's PC to be set from the command line. This

+can be done by following the syntax below::

+

+ -device loader,addr=<addr>,cpu-num=<cpu-num>

+

+``<addr>``

+ The value to use as the CPU's PC.

+

+``<cpu-num>``

+ The number of the CPU whose PC should be set to the specified value.

+

+All values are parsed using the standard QemuOpts parsing. This allows the user

+to specify any values in any format supported. By default the values

+will be parsed as decimal. To use hex values the user should prefix the number

+with a '0x'.

+

+An example of setting CPU 0's PC to 0x8000 is::

+

+ -device loader,addr=0x8000,cpu-num=0

+

+Loading Files

+^^^^^^^^^^^^^

+

+The loader device also allows files to be loaded into memory. It can load ELF,

+U-Boot, and Intel HEX executable formats as well as raw images. The syntax is

+shown below:

+

+ -device loader,file=<file>[,addr=<addr>][,cpu-num=<cpu-num>][,force-raw=<raw>]

+

+``<file>``

+ A file to be loaded into memory

+

+``<addr>``

+ The memory address where the file should be loaded. This is required

+ for raw images and ignored for non-raw files.

+

+``<cpu-num>``

+ This specifies the CPU that should be used. This is an

+ optional argument and will cause the CPU's PC to be set to the

+ memory address where the raw file is loaded or the entry point

+ specified in the executable format header. This option should only

+ be used for the boot image. This will also cause the image to be

+ written to the specified CPU's address space. If not specified, the

+ default is CPU 0. <force-raw> - Setting force-raw=on forces the file

+ to be treated as a raw image. This can be used to load supported

+ executable formats as if they were raw.

+

+All values are parsed using the standard QemuOpts parsing. This allows the user

+to specify any values in any format supported. By default the values

+will be parsed as decimal. To use hex values the user should prefix the number

+with a '0x'.

+

+An example of loading an ELF file which CPU0 will boot is shown below::

+

+ -device loader,file=./images/boot.elf,cpu-num=0

+

+Restrictions and ToDos

+^^^^^^^^^^^^^^^^^^^^^^

+

+At the moment it is just assumed that if you specify a cpu-num then

+you want to set the PC as well. This might not always be the case. In

+future the internal state 'set_pc' (which exists in the generic loader

+now) should be exposed to the user so that they can choose if the PC

+is set or not.

+

+

+..

+ Copyright (c) 2020, Linaro

+

+Guest Loader

+------------

+

+The guest loader is similar to the `generic-loader` although it is

+aimed at a particular use case of loading hypervisor guests. This is

+useful for debugging hypervisors without having to jump through the

+hoops of firmware and boot-loaders.

+

+The guest loader does two things:

+

+ - load blobs (kernels and initial ram disks) into memory

+ - sets platform FDT data so hypervisors can find and boot them

+

+This is what is typically done by a boot-loader like grub using it's

+multi-boot capability. A typical example would look like:

+

+.. parsed-literal::

+

+ |qemu_system| -kernel ~/xen.git/xen/xen \

+ -append "dom0_mem=1G,max:1G loglvl=all guest_loglvl=all" \

+ -device guest-loader,addr=0x42000000,kernel=Image,bootargs="root=/dev/sda2 ro console=hvc0 earlyprintk=xen" \

+ -device guest-loader,addr=0x47000000,initrd=rootfs.cpio

+

+In the above example the Xen hypervisor is loaded by the -kernel

+parameter and passed it's boot arguments via -append. The Dom0 guest

+is loaded into the areas of memory. Each blob will get

+`/chosen/module@<addr>` entry in the FDT to indicate it's location and

+size. Additional information can be passed with by using additional

+arguments.

+

+Currently the only supported machines which use FDT data to boot are

+the ARM and RiscV `virt` machines.

+

+Arguments

+^^^^^^^^^

+

+The full syntax of the guest-loader is::

+

+ -device guest-loader,addr=<addr>[,kernel=<file>,[bootargs=<args>]][,initrd=<file>]

+

+``addr=<addr>``

+ This is mandatory and indicates the start address of the blob.

+

+``kernel|initrd=<file>``

+ Indicates the filename of the kernel or initrd blob. Both blobs will

+ have the "multiboot,module" compatibility string as well as

+ "multiboot,kernel" or "multiboot,ramdisk" as appropriate.

+

+``bootargs=<args>``

+ This is an optional field for kernel blobs which will pass command

+ like via the `/chosen/module@<addr>/bootargs` node.

+ generic-loader

+ guest-loader

+Embedded family boards

+======================

+

+- ``bamboo`` bamboo

+- ``mpc8544ds`` mpc8544ds

+- ``ppce500`` generic paravirt e500 platform

+- ``ref405ep`` ref405ep

+- ``sam460ex`` aCube Sam460ex

+- ``taihu`` taihu

+- ``virtex-ml507`` Xilinx Virtex ML507 reference design

+PowerMac family boards (``g3beige``, ``mac99``)

+==================================================================

+

+Use the executable ``qemu-system-ppc`` to simulate a complete PowerMac

+PowerPC system.

+

+- ``g3beige`` Heathrow based PowerMAC

+- ``mac99`` Mac99 based PowerMAC

+

+Supported devices

+-----------------

+

+QEMU emulates the following PowerMac peripherals:

+

+ * UniNorth or Grackle PCI Bridge

+ * PCI VGA compatible card with VESA Bochs Extensions

+ * 2 PMAC IDE interfaces with hard disk and CD-ROM support

+ * NE2000 PCI adapters

+ * Non Volatile RAM

+ * VIA-CUDA with ADB keyboard and mouse.

+

+

+Missing devices

+---------------

+

+ * To be identified

+

+Firmware

+--------

+

+Since version 0.9.1, QEMU uses OpenBIOS https://www.openbios.org/ for

+the g3beige and mac99 PowerMac and the 40p machines. OpenBIOS is a free

+(GPL v2) portable firmware implementation. The goal is to implement a

+100% IEEE 1275-1994 (referred to as Open Firmware) compliant firmware.

+PowerNV family boards (``powernv8``, ``powernv9``)

+==================================================================

+

+PowerNV (as Non-Virtualized) is the "baremetal" platform using the

+OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can

+be used as an hypervisor OS, running KVM guests, or simply as a host

+OS.

+

+The PowerNV QEMU machine tries to emulate a PowerNV system at the

+level of the skiboot firmware, which loads the OS and provides some

+runtime services. Power Systems have a lower firmware (HostBoot) that

+does low level system initialization, like DRAM training. This is

+beyond the scope of what QEMU addresses today.

+

+Supported devices

+-----------------

+

+ * Multi processor support for POWER8, POWER8NVL and POWER9.

+ * XSCOM, serial communication sideband bus to configure chiplets

+ * Simple LPC Controller

+ * Processor Service Interface (PSI) Controller

+ * Interrupt Controller, XICS (POWER8) and XIVE (POWER9)

+ * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge

+ * Simple OCC is an on-chip microcontroller used for power management

+ tasks

+ * iBT device to handle BMC communication, with the internal BMC

+ simulator provided by QEMU or an external BMC such as an Aspeed

+ QEMU machine.

+ * PNOR containing the different firmware partitions.

+

+Missing devices

+---------------

+

+A lot is missing, among which :

+

+ * POWER10 processor

+ * XIVE2 (POWER10) interrupt controller

+ * I2C controllers (yet to be merged)

+ * NPU/NPU2/NPU3 controllers

+ * EEH support for PCIe Host bridge controllers

+ * NX controller

+ * VAS controller

+ * chipTOD (Time Of Day)

+ * Self Boot Engine (SBE).

+ * FSI bus

+

+Firmware

+--------

+

+The OPAL firmware (OpenPower Abstraction Layer) for OpenPower systems

+includes the runtime services `skiboot` and the bootloader kernel and

+initramfs `skiroot`. Source code can be found on GitHub:

+

+ https://github.com/open-power.

+

+Prebuilt images of `skiboot` and `skiboot` are made available on the `OpenPOWER <https://openpower.xyz/job/openpower/job/openpower-op-build/>`__ site. To boot a POWER9 machine, use the `witherspoon <https://openpower.xyz/job/openpower/job/openpower-op-build/label=slave,target=witherspoon/lastSuccessfulBuild/>`__ images. For POWER8, use

+the `palmetto <https://openpower.xyz/job/openpower/job/openpower-op-build/label=slave,target=palmetto/lastSuccessfulBuild/>`__ images.

+

+QEMU includes a prebuilt image of `skiboot` which is updated when a

+more recent version is required by the models.

+

+Boot options

+------------

+

+Here is a simple setup with one e1000e NIC :

+

+.. code-block:: bash

+

+ $ qemu-system-ppc64 -m 2G -machine powernv9 -smp 2,cores=2,threads=1 \

+ -accel tcg,thread=single \

+ -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0 \

+ -netdev user,id=net0,hostfwd=::20022-:22,hostname=pnv \

+ -kernel ./zImage.epapr \

+ -initrd ./rootfs.cpio.xz \

+ -nographic

+

+and a SATA disk :

+

+.. code-block:: bash

+

+ -device ich9-ahci,id=sata0,bus=pcie.1,addr=0x0 \

+ -drive file=./ubuntu-ppc64le.qcow2,if=none,id=drive0,format=qcow2,cache=none \

+ -device ide-hd,bus=sata0.0,unit=0,drive=drive0,id=ide,bootindex=1 \

+

+Complex PCIe configuration

+~~~~~~~~~~~~~~~~~~~~~~~~~~

+Six PHBs are defined per chip (POWER9) but no default PCI layout is

+provided (to be compatible with libvirt). One PCI device can be added

+on any of the available PCIe slots using command line options such as:

+

+.. code-block:: bash

+

+ -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=pcie.0,addr=0x0

+ -netdev bridge,id=net0,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=hostnet0

+

+ -device megasas,id=scsi0,bus=pcie.0,addr=0x0

+ -drive file=./ubuntu-ppc64le.qcow2,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none

+ -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2

+

+Here is a full example with two different storage controllers on

+different PHBs, each with a disk, the second PHB is empty :

+

+.. code-block:: bash

+

+ $ qemu-system-ppc64 -m 2G -machine powernv9 -smp 2,cores=2,threads=1 -accel tcg,thread=single \

+ -kernel ./zImage.epapr -initrd ./rootfs.cpio.xz -bios ./skiboot.lid \

+ \

+ -device megasas,id=scsi0,bus=pcie.0,addr=0x0 \

+ -drive file=./rhel7-ppc64le.qcow2,if=none,id=drive-scsi0-0-0-0,format=qcow2,cache=none \

+ -device scsi-hd,bus=scsi0.0,channel=0,scsi-id=0,lun=0,drive=drive-scsi0-0-0-0,id=scsi0-0-0-0,bootindex=2 \

+ \

+ -device pcie-pci-bridge,id=bridge1,bus=pcie.1,addr=0x0 \

+ \

+ -device ich9-ahci,id=sata0,bus=bridge1,addr=0x1 \

+ -drive file=./ubuntu-ppc64le.qcow2,if=none,id=drive0,format=qcow2,cache=none \

+ -device ide-hd,bus=sata0.0,unit=0,drive=drive0,id=ide,bootindex=1 \

+ -device e1000e,netdev=net0,mac=C0:FF:EE:00:00:02,bus=bridge1,addr=0x2 \

+ -netdev bridge,helper=/usr/libexec/qemu-bridge-helper,br=virbr0,id=net0 \

+ -device nec-usb-xhci,bus=bridge1,addr=0x7 \

+ \

+ -serial mon:stdio -nographic

+

+You can also use VIRTIO devices :

+

+.. code-block:: bash

+

+ -drive file=./fedora-ppc64le.qcow2,if=none,snapshot=on,id=drive0 \

+ -device virtio-blk-pci,drive=drive0,id=blk0,bus=pcie.0 \

+ \

+ -netdev tap,helper=/usr/lib/qemu/qemu-bridge-helper,br=virbr0,id=netdev0 \

+ -device virtio-net-pci,netdev=netdev0,id=net0,bus=pcie.1 \

+ \

+ -fsdev local,id=fsdev0,path=$HOME,security_model=passthrough \

+ -device virtio-9p-pci,fsdev=fsdev0,mount_tag=host,bus=pcie.2

+

+Multi sockets

+~~~~~~~~~~~~~

+

+The number of sockets is deduced from the number of CPUs and the

+number of cores. ``-smp 2,cores=1`` will define a machine with 2

+sockets of 1 core, whereas ``-smp 2,cores=2`` will define a machine

+with 1 socket of 2 cores. ``-smp 8,cores=2``, 4 sockets of 2 cores.

+

+BMC configuration

+~~~~~~~~~~~~~~~~~

+

+OpenPOWER systems negotiate the shutdown and reboot with their

+BMC. The QEMU PowerNV machine embeds an IPMI BMC simulator using the

+iBT interface and should offer the same power features.

+

+If you want to define your own BMC, use ``-nodefaults`` and specify

+one on the command line :

+

+.. code-block:: bash

+

+ -device ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10

+

+The files `palmetto-SDR.bin <http://www.kaod.org/qemu/powernv/palmetto-SDR.bin>`__

+and `palmetto-FRU.bin <http://www.kaod.org/qemu/powernv/palmetto-FRU.bin>`__

+define a Sensor Data Record repository and a Field Replaceable Unit

+inventory for a palmetto BMC. They can be used to extend the QEMU BMC

+simulator.

+

+.. code-block:: bash

+

+ -device ipmi-bmc-sim,sdrfile=./palmetto-SDR.bin,fruareasize=256,frudatafile=./palmetto-FRU.bin,id=bmc0 \

+ -device isa-ipmi-bt,bmc=bmc0,irq=10

+

+The PowerNV machine can also be run with an external IPMI BMC device

+connected to a remote QEMU machine acting as BMC, using these options

+:

+

+.. code-block:: bash

+

+ -chardev socket,id=ipmi0,host=localhost,port=9002,reconnect=10 \

+ -device ipmi-bmc-extern,id=bmc0,chardev=ipmi0 \

+ -device isa-ipmi-bt,bmc=bmc0,irq=10 \

+ -nodefaults

+

+NVRAM

+~~~~~

+

+Use a MTD drive to add a PNOR to the machine, and get a NVRAM :

+

+.. code-block:: bash

+

+ -drive file=./witherspoon.pnor,format=raw,if=mtd

+

+CAVEATS

+-------

+

+ * No support for multiple HW threads (SMT=1). Same as pseries.

+ * CPU can hang when doing intensive I/Os. Use ``-append powersave=off`` in that case.

+Prep machine (``40p``)

+==================================================================

+

+Use the executable ``qemu-system-ppc`` to simulate a complete 40P (PREP)

+

+Supported devices

+-----------------

+

+QEMU emulates the following 40P (PREP) peripherals:

+

+ * PCI Bridge

+ * PCI VGA compatible card with VESA Bochs Extensions

+ * 2 IDE interfaces with hard disk and CD-ROM support

+ * Floppy disk

+ * PCnet network adapters

+ * Serial port

+ * PREP Non Volatile RAM

+ * PC compatible keyboard and mouse.

+pSeries family boards (``pseries``)

+===================================

+

+Supported devices

+-----------------

+

+Missing devices

+---------------

+

+

+Firmware

+--------

+

+Users should be aware the above example elides a lot of the complexity

+of setting up a VM with x86_64 specific defaults and assumes the

+first non switch argument is a PC compatible disk image with a boot

+sector. For a non-x86 system where we emulate a broad range of machine

+types, the command lines are generally more explicit in defining the

+machine and boot behaviour. You will find more example command lines

+in the :ref:`system-targets-ref` section of the manual.

+``-show-cursor`` option (removed in 6.0)

+''''''''''''''''''''''''''''''''''''''''

+Board-specific documentation

+============================

+You can get a complete list by running ``qemu-system-ppc64 --machine

+help``.

+..

+ This table of contents should be kept sorted alphabetically

+ by the title text of each file, which isn't the same ordering

+ as an alphabetical sort by filename.

+.. toctree::

+ :maxdepth: 1

+ ppc/embedded

+ ppc/powermac

+ ppc/powernv

+ ppc/prep

+ ppc/pseries

+.. _system-targets-ref:

+

+#include "semihosting/semihost.h"

+static void gdb_vm_state_change(void *opaque, bool running, RunState state)

+ NPCM7XX_MFT0_IRQ = 96, /* MFT module 0 */

+ NPCM7XX_MFT1_IRQ, /* MFT module 1 */

+ NPCM7XX_MFT2_IRQ, /* MFT module 2 */

+ NPCM7XX_MFT3_IRQ, /* MFT module 3 */

+ NPCM7XX_MFT4_IRQ, /* MFT module 4 */

+ NPCM7XX_MFT5_IRQ, /* MFT module 5 */

+ NPCM7XX_MFT6_IRQ, /* MFT module 6 */

+ NPCM7XX_MFT7_IRQ, /* MFT module 7 */

+/* Register base address for each MFT Module */

+static const hwaddr npcm7xx_mft_addr[] = {

+ 0xf0180000,

+ 0xf0181000,

+ 0xf0182000,

+ 0xf0183000,

+ 0xf0184000,

+ 0xf0185000,

+ 0xf0186000,

+ 0xf0187000,

+};

+

+ for (i = 0; i < ARRAY_SIZE(s->mft); i++) {

+ object_initialize_child(obj, "mft[*]", &s->mft[i], TYPE_NPCM7XX_MFT);

+ }

+

+ /* MFT Modules. Cannot fail. */

+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_mft_addr) != ARRAY_SIZE(s->mft));

+ for (i = 0; i < ARRAY_SIZE(s->mft); i++) {

+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->mft[i]);

+

+ qdev_connect_clock_in(DEVICE(&s->mft[i]), "clock-in",

+ qdev_get_clock_out(DEVICE(&s->clk),

+ "apb4-clock"));

+ sysbus_realize(sbd, &error_abort);

+ sysbus_mmio_map(sbd, 0, npcm7xx_mft_addr[i]);

+ sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, NPCM7XX_MFT0_IRQ + i));

+ }

+

+#include "hw/qdev-core.h"

+static void npcm7xx_init_pwm_splitter(NPCM7xxMachine *machine,

+ NPCM7xxState *soc, const int *fan_counts)

+{

+ SplitIRQ *splitters = machine->fan_splitter;

+

+ /*

+ * PWM 0~3 belong to module 0 output 0~3.

+ * PWM 4~7 belong to module 1 output 0~3.

+ */

+ for (int i = 0; i < NPCM7XX_NR_PWM_MODULES; ++i) {

+ for (int j = 0; j < NPCM7XX_PWM_PER_MODULE; ++j) {

+ int splitter_no = i * NPCM7XX_PWM_PER_MODULE + j;

+ DeviceState *splitter;

+

+ if (fan_counts[splitter_no] < 1) {

+ continue;

+ }

+ object_initialize_child(OBJECT(machine), "fan-splitter[*]",

+ &splitters[splitter_no], TYPE_SPLIT_IRQ);

+ splitter = DEVICE(&splitters[splitter_no]);

+ qdev_prop_set_uint16(splitter, "num-lines",

+ fan_counts[splitter_no]);

+ qdev_realize(splitter, NULL, &error_abort);

+ qdev_connect_gpio_out_named(DEVICE(&soc->pwm[i]), "duty-gpio-out",

+ j, qdev_get_gpio_in(splitter, 0));

+ }

+ }

+}

+

+static void npcm7xx_connect_pwm_fan(NPCM7xxState *soc, SplitIRQ *splitter,

+ int fan_no, int output_no)

+{

+ DeviceState *fan;

+ int fan_input;

+ qemu_irq fan_duty_gpio;

+

+ g_assert(fan_no >= 0 && fan_no <= NPCM7XX_MFT_MAX_FAN_INPUT);

+ /*

+ * Fan 0~1 belong to module 0 input 0~1.

+ * Fan 2~3 belong to module 1 input 0~1.

+ * ...

+ * Fan 14~15 belong to module 7 input 0~1.

+ * Fan 16~17 belong to module 0 input 2~3.

+ * Fan 18~19 belong to module 1 input 2~3.

+ */

+ if (fan_no < 16) {

+ fan = DEVICE(&soc->mft[fan_no / 2]);

+ fan_input = fan_no % 2;

+ } else {

+ fan = DEVICE(&soc->mft[(fan_no - 16) / 2]);

+ fan_input = fan_no % 2 + 2;

+ }

+

+ /* Connect the Fan to PWM module */

+ fan_duty_gpio = qdev_get_gpio_in_named(fan, "duty", fan_input);

+ qdev_connect_gpio_out(DEVICE(splitter), output_no, fan_duty_gpio);

+}

+

+static void npcm750_evb_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)

+{

+ SplitIRQ *splitter = machine->fan_splitter;

+ static const int fan_counts[] = {2, 2, 2, 2, 2, 2, 2, 2};

+

+ npcm7xx_init_pwm_splitter(machine, soc, fan_counts);

+ npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x06, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[3], 0x07, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x08, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[4], 0x09, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0a, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[5], 0x0b, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0c, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[6], 0x0d, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0e, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[7], 0x0f, 1);

+}

+

+static void quanta_gsj_fan_init(NPCM7xxMachine *machine, NPCM7xxState *soc)

+{

+ SplitIRQ *splitter = machine->fan_splitter;

+ static const int fan_counts[] = {2, 2, 2, 0, 0, 0, 0, 0};

+

+ npcm7xx_init_pwm_splitter(machine, soc, fan_counts);

+ npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x00, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[0], 0x01, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x02, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[1], 0x03, 1);

+ npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x04, 0);

+ npcm7xx_connect_pwm_fan(soc, &splitter[2], 0x05, 1);

+}

+

+ npcm750_evb_fan_init(NPCM7XX_MACHINE(machine), soc);

+ quanta_gsj_fan_init(NPCM7XX_MACHINE(machine), soc);

+ /* if tg is not set we use 4KB range invalidation */

+ uint8_t granule = tg ? tg * 2 + 10 : 12;

+

+ if (ttl && (num_pages == 1) && (asid >= 0)) {

+ if (g_hash_table_remove(s->iotlb, &key)) {

+ return;

+ }

+ /*

+ * if the entry is not found, let's see if it does not

+ * belong to a larger IOTLB entry

+ */

+ }

+ SMMUIOTLBPageInvInfo info = {

+ .asid = asid, .iova = iova,

+ .mask = (num_pages * 1 << granule) - 1};

+ g_hash_table_foreach_remove(s->iotlb,

+ smmu_hash_remove_by_asid_iova,

+ &info);

+typedef struct SMMUSIDRange {

+ uint32_t start;

+ uint32_t end;

+} SMMUSIDRange;

+

+#include "smmu-internal.h"

+ uint64_t first_page = 0, last_page;

+ uint64_t num_pages = 1;

+

+ /* Split invalidations into ^2 range invalidations */

+ last_page = num_pages - 1;

+ while (num_pages) {

+ uint8_t granule = tg * 2 + 10;

+ uint64_t mask, count;

+

+ mask = dma_aligned_pow2_mask(first_page, last_page, 64 - granule);

+ count = mask + 1;

+

+ trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, count, ttl, leaf);

+ smmuv3_inv_notifiers_iova(s, asid, addr, tg, count);

+ smmu_iotlb_inv_iova(s, asid, addr, tg, count, ttl);

+

+ num_pages -= count;

+ first_page += count;

+ addr += count * BIT_ULL(granule);

+ }

+}

+

+static gboolean

+smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)

+{

+ SMMUDevice *sdev = (SMMUDevice *)key;

+ uint32_t sid = smmu_get_sid(sdev);

+ SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;

+

+ if (sid < sid_range->start || sid > sid_range->end) {

+ return false;

+ }

+ trace_smmuv3_config_cache_inv(sid);

+ return true;

+ uint32_t start = CMD_SID(&cmd);

+ uint64_t end = start + (1ULL << (range + 1)) - 1;

+ SMMUSIDRange sid_range = {start, end};

+ g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,

+ &sid_range);

+smmuv3_record_event(const char *type, uint32_t sid) "%s sid=0x%x"

+smmuv3_find_ste(uint16_t sid, uint32_t features, uint16_t sid_split) "sid=0x%x features:0x%x, sid_split:0x%x"

+smmuv3_translate_disable(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x bypass (smmu disabled) iova:0x%"PRIx64" is_write=%d"

+smmuv3_translate_bypass(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x STE bypass iova:0x%"PRIx64" is_write=%d"

+smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x abort on iova:0x%"PRIx64" is_write=%d"

+smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=0x%x iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"

+smmuv3_cmdq_cfgi_ste(int streamid) "streamid= 0x%x"

+smmuv3_cmdq_cfgi_cd(uint32_t sid) "sid=0x%x"

+smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"

+smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid=0x%x (hits=%d, misses=%d, hit rate=%d)"

+smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid=%d asid=%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"

+smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"

+static void create_kaslr_seed(MachineState *ms, const char *node)

+ qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed);

+ ms->fdt = fdt;

+ create_kaslr_seed(ms, "/chosen");

+ create_kaslr_seed(ms, "/secure-chosen");

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, "/timer");

+ qemu_fdt_setprop(ms->fdt, "/timer", "compatible",

+ qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",

+ qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);

+ qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",

+ qemu_fdt_add_subnode(ms->fdt, "/cpus");

+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);

+ qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",

+ qemu_fdt_setprop_string(ms->fdt, nodename,

+ qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",

+ MachineState *ms = MACHINE(vms);

+ vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",

+ qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);

+ MachineState *ms = MACHINE(vms);

+ vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",

+ qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);

+ MachineState *ms = MACHINE(vms);

+ vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);

+ qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);

+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);

+ qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",

+ qemu_fdt_setprop_cell(ms->fdt, nodename,

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, "/pmu");

+ qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",

+ qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop(ms->fdt, nodename, "compatible",

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",

+ qemu_fdt_setprop(ms->fdt, nodename, "clock-names",

+ qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");

+ qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");

+ qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");

+static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,

+ qemu_fdt_add_subnode(fdt, "/gpio-keys");

+ qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");

+ qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#size-cells", 0);

+ qemu_fdt_setprop_cell(fdt, "/gpio-keys", "#address-cells", 1);

+ qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");

+ qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",

+ qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",

+ qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",

+static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,

+ qemu_fdt_add_subnode(fdt, "/gpio-poweroff");

+ qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",

+ qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",

+ qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");

+ qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",

+ qemu_fdt_add_subnode(fdt, "/gpio-restart");

+ qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",

+ qemu_fdt_setprop_cells(fdt, "/gpio-restart",

+ qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");

+ qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",

+ MachineState *ms = MACHINE(vms);

+ uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);

+ qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");

+ qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");

+ create_gpio_keys(ms->fdt, pl061_dev, phandle);

+ create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename,

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",

+ qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");

+ qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename,

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);

+static void create_pcie_irq_map(const MachineState *ms,

+ qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, node);

+ qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));

+ qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);

+ qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",

+ qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,

+ qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);

+ qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");

+ qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);

+ qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);

+ qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);

+ MachineState *ms = MACHINE(vms);

+ vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);

+ qemu_fdt_add_subnode(ms->fdt, node);

+ qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));

+ qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",

+ qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);

+ qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);

+ qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename,

+ qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,

+ qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",

+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);

+ create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);

+ vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);

+ qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",

+ MachineState *ms = MACHINE(vms);

+ qemu_fdt_add_subnode(ms->fdt, nodename);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");

+ qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);

+ qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");

+ qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");

+ MachineState *ms = MACHINE(board);

+

+ return ms->fdt;

+ platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",

+ int max_vm_pa_size, requested_pa_size;

+ bool fixed_ipa;

+

+ max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);

+ /*

+ * KVM requires the IPA size to be at least 32 bits.

+ */

+ if (requested_pa_size < 32) {

+ requested_pa_size = 32;

+ }

+

+ exit(1);

+ * We return the requested PA log size, unless KVM only supports

+ * the implicit legacy 40b IPA setting, in which case the kvm_type

+ * must be 0.

+ return fixed_ipa ? 0 : requested_pa_size;

+#include "qemu/units.h"

+static void versal_create_xrams(Versal *s, qemu_irq *pic)

+{

+ int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);

+ DeviceState *orgate;

+ int i;

+

+ /* XRAM IRQs get ORed into a single line. */

+ object_initialize_child(OBJECT(s), "xram-irq-orgate",

+ &s->lpd.xram.irq_orgate, TYPE_OR_IRQ);

+ orgate = DEVICE(&s->lpd.xram.irq_orgate);

+ object_property_set_int(OBJECT(orgate),

+ "num-lines", nr_xrams, &error_fatal);

+ qdev_realize(orgate, NULL, &error_fatal);

+ qdev_connect_gpio_out(orgate, 0, pic[VERSAL_XRAM_IRQ_0]);

+

+ for (i = 0; i < ARRAY_SIZE(s->lpd.xram.ctrl); i++) {

+ SysBusDevice *sbd;

+ MemoryRegion *mr;

+

+ object_initialize_child(OBJECT(s), "xram[*]", &s->lpd.xram.ctrl[i],

+ TYPE_XLNX_XRAM_CTRL);

+ sbd = SYS_BUS_DEVICE(&s->lpd.xram.ctrl[i]);

+ sysbus_realize(sbd, &error_fatal);

+

+ mr = sysbus_mmio_get_region(sbd, 0);

+ memory_region_add_subregion(&s->mr_ps,

+ MM_XRAMC + i * MM_XRAMC_SIZE, mr);

+ mr = sysbus_mmio_get_region(sbd, 1);

+ memory_region_add_subregion(&s->mr_ps, MM_XRAM + i * MiB, mr);

+

+ sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(orgate, i));

+ }

+}

+

+ versal_create_xrams(s, pic);

+static void postload_update_cb(void *opaque, bool running, RunState state)

+static void virtio_blk_dma_restart_cb(void *opaque, bool running,

+softmmu_ss.add(when: 'CONFIG_LM32_DEVICES', if_true: files('lm32_juart.c'))

+softmmu_ss.add(when: 'CONFIG_LM32_DEVICES', if_true: files('lm32_uart.c'))

+/*

+ * Guest Loader

+ *

+ * Copyright (C) 2020 Linaro

+ * Written by Alex Bennée <alex.bennee@linaro.org>

+ * (based on the generic-loader by Li Guang <lig.fnst@cn.fujitsu.com>)

+ *

+ * SPDX-License-Identifier: GPL-2.0-or-later

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+/*

+ * Much like the generic-loader this is treated as a special device

+ * inside QEMU. However unlike the generic-loader this device is used

+ * to load guest images for hypervisors. As part of that process the

+ * hypervisor needs to have platform information passed to it by the

+ * lower levels of the stack (e.g. firmware/bootloader). If you boot

+ * the hypervisor directly you use the guest-loader to load the Dom0

+ * or equivalent guest images in the right place in the same way a

+ * boot loader would.

+ *

+ * This is only relevant for full system emulation.

+ */

+

+#include "qemu/osdep.h"

+#include "hw/core/cpu.h"

+#include "hw/sysbus.h"

+#include "sysemu/dma.h"

+#include "hw/loader.h"

+#include "hw/qdev-properties.h"

+#include "qapi/error.h"

+#include "qemu/module.h"

+#include "guest-loader.h"

+#include "sysemu/device_tree.h"

+#include "hw/boards.h"

+

+/*

+ * Insert some FDT nodes for the loaded blob.

+ */

+static void loader_insert_platform_data(GuestLoaderState *s, int size,

+ Error **errp)

+{

+ MachineState *machine = MACHINE(qdev_get_machine());

+ void *fdt = machine->fdt;

+ g_autofree char *node = g_strdup_printf("/chosen/module@0x%08" PRIx64,

+ s->addr);

+ uint64_t reg_attr[2] = {cpu_to_be64(s->addr), cpu_to_be64(size)};

+

+ if (!fdt) {

+ error_setg(errp, "Cannot modify FDT fields if the machine has none");

+ return;

+ }

+

+ qemu_fdt_add_subnode(fdt, node);

+ qemu_fdt_setprop(fdt, node, "reg", &reg_attr, sizeof(reg_attr));

+

+ if (s->kernel) {

+ const char *compat[2] = { "multiboot,module", "multiboot,kernel" };

+ if (qemu_fdt_setprop_string_array(fdt, node, "compatible",

+ (char **) &compat,

+ ARRAY_SIZE(compat)) < 0) {

+ error_setg(errp, "couldn't set %s/compatible", node);

+ return;

+ }

+ if (s->args) {

+ if (qemu_fdt_setprop_string(fdt, node, "bootargs", s->args) < 0) {

+ error_setg(errp, "couldn't set %s/bootargs", node);

+ }

+ }

+ } else if (s->initrd) {

+ const char *compat[2] = { "multiboot,module", "multiboot,ramdisk" };

+ if (qemu_fdt_setprop_string_array(fdt, node, "compatible",

+ (char **) &compat,

+ ARRAY_SIZE(compat)) < 0) {

+ error_setg(errp, "couldn't set %s/compatible", node);

+ return;

+ }

+ }

+}

+

+static void guest_loader_realize(DeviceState *dev, Error **errp)

+{

+ GuestLoaderState *s = GUEST_LOADER(dev);

+ char *file = s->kernel ? s->kernel : s->initrd;

+ int size = 0;

+

+ /* Perform some error checking on the user's options */

+ if (s->kernel && s->initrd) {

+ error_setg(errp, "Cannot specify a kernel and initrd in same stanza");

+ return;

+ } else if (!s->kernel && !s->initrd) {

+ error_setg(errp, "Need to specify a kernel or initrd image");

+ return;

+ } else if (!s->addr) {

+ error_setg(errp, "Need to specify the address of guest blob");

+ return;

+ } else if (s->args && !s->kernel) {

+ error_setg(errp, "Boot args only relevant to kernel blobs");

+ }

+

+ /* Default to the maximum size being the machine's ram size */

+ size = load_image_targphys_as(file, s->addr, current_machine->ram_size,

+ NULL);

+ if (size < 0) {

+ error_setg(errp, "Cannot load specified image %s", file);

+ return;

+ }

+

+ /* Now the image is loaded we need to update the platform data */

+ loader_insert_platform_data(s, size, errp);

+}

+

+static Property guest_loader_props[] = {

+ DEFINE_PROP_UINT64("addr", GuestLoaderState, addr, 0),

+ DEFINE_PROP_STRING("kernel", GuestLoaderState, kernel),

+ DEFINE_PROP_STRING("bootargs", GuestLoaderState, args),

+ DEFINE_PROP_STRING("initrd", GuestLoaderState, initrd),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+static void guest_loader_class_init(ObjectClass *klass, void *data)

+{

+ DeviceClass *dc = DEVICE_CLASS(klass);

+

+ dc->realize = guest_loader_realize;

+ device_class_set_props(dc, guest_loader_props);

+ dc->desc = "Guest Loader";

+ set_bit(DEVICE_CATEGORY_MISC, dc->categories);

+}

+

+static TypeInfo guest_loader_info = {

+ .name = TYPE_GUEST_LOADER,

+ .parent = TYPE_DEVICE,

+ .instance_size = sizeof(GuestLoaderState),

+ .class_init = guest_loader_class_init,

+};

+

+static void guest_loader_register_type(void)

+{

+ type_register_static(&guest_loader_info);

+}

+

+type_init(guest_loader_register_type)

+/*

+ * Guest Loader

+ *

+ * Copyright (C) 2020 Linaro

+ * Written by Alex Bennée <alex.bennee@linaro.org>

+ * (based on the generic-loader by Li Guang <lig.fnst@cn.fujitsu.com>)

+ *

+ * SPDX-License-Identifier: GPL-2.0-or-later

+ *

+ * This work is licensed under the terms of the GNU GPL, version 2 or later.

+ * See the COPYING file in the top-level directory.

+ */

+

+#ifndef GUEST_LOADER_H

+#define GUEST_LOADER_H

+

+#include "hw/qdev-core.h"

+#include "qom/object.h"

+

+struct GuestLoaderState {

+ /* <private> */

+ DeviceState parent_obj;

+

+ /* <public> */

+ uint64_t addr;

+ char *kernel;

+ char *args;

+ char *initrd;

+};

+

+#define TYPE_GUEST_LOADER "guest-loader"

+OBJECT_DECLARE_SIMPLE_TYPE(GuestLoaderState, GUEST_LOADER)

+

+#endif

+softmmu_ss.add(when: 'CONFIG_TCG', if_true: files('guest-loader.c'))

+

+#define COPY_PIXEL(to, from) do { *(uint32_t *)to = from; to += 4; } while (0)

+

+#undef RGB

+#define BORDER bgr

+#define ORDER 0

+#include "pl110_template.h"

+#define ORDER 1

+#define ORDER 2

+#undef BORDER

+#define RGB

+#define BORDER rgb

+#define ORDER 0

+#define ORDER 1

+#define ORDER 2

+#undef BORDER

+

+#undef COPY_PIXEL

+

+static drawfn pl110_draw_fn_32[48] = {

+ pl110_draw_line1_lblp_bgr,

+ pl110_draw_line2_lblp_bgr,

+ pl110_draw_line4_lblp_bgr,

+ pl110_draw_line8_lblp_bgr,

+ pl110_draw_line16_555_lblp_bgr,

+ pl110_draw_line32_lblp_bgr,

+ pl110_draw_line16_lblp_bgr,

+ pl110_draw_line12_lblp_bgr,

+

+ pl110_draw_line1_bbbp_bgr,

+ pl110_draw_line2_bbbp_bgr,

+ pl110_draw_line4_bbbp_bgr,

+ pl110_draw_line8_bbbp_bgr,

+ pl110_draw_line16_555_bbbp_bgr,

+ pl110_draw_line32_bbbp_bgr,

+ pl110_draw_line16_bbbp_bgr,

+ pl110_draw_line12_bbbp_bgr,

+

+ pl110_draw_line1_lbbp_bgr,

+ pl110_draw_line2_lbbp_bgr,

+ pl110_draw_line4_lbbp_bgr,

+ pl110_draw_line8_lbbp_bgr,

+ pl110_draw_line16_555_lbbp_bgr,

+ pl110_draw_line32_lbbp_bgr,

+ pl110_draw_line16_lbbp_bgr,

+ pl110_draw_line12_lbbp_bgr,

+

+ pl110_draw_line1_lblp_rgb,

+ pl110_draw_line2_lblp_rgb,

+ pl110_draw_line4_lblp_rgb,

+ pl110_draw_line8_lblp_rgb,

+ pl110_draw_line16_555_lblp_rgb,

+ pl110_draw_line32_lblp_rgb,

+ pl110_draw_line16_lblp_rgb,

+ pl110_draw_line12_lblp_rgb,

+

+ pl110_draw_line1_bbbp_rgb,

+ pl110_draw_line2_bbbp_rgb,

+ pl110_draw_line4_bbbp_rgb,

+ pl110_draw_line8_bbbp_rgb,

+ pl110_draw_line16_555_bbbp_rgb,

+ pl110_draw_line32_bbbp_rgb,

+ pl110_draw_line16_bbbp_rgb,

+ pl110_draw_line12_bbbp_rgb,

+

+ pl110_draw_line1_lbbp_rgb,

+ pl110_draw_line2_lbbp_rgb,

+ pl110_draw_line4_lbbp_rgb,

+ pl110_draw_line8_lbbp_rgb,

+ pl110_draw_line16_555_lbbp_rgb,

+ pl110_draw_line32_lbbp_rgb,

+ pl110_draw_line16_lbbp_rgb,

+ pl110_draw_line12_lbbp_rgb,

+};

+ if (s->cr & PL110_CR_BEBO) {

+ fn = pl110_draw_fn_32[s->bpp + 8 + bpp_offset];

+ } else if (s->cr & PL110_CR_BEPO) {

+ fn = pl110_draw_fn_32[s->bpp + 16 + bpp_offset];

+ } else {

+ fn = pl110_draw_fn_32[s->bpp + bpp_offset];

+ }

+ src_width, s->cols * 4, 0,

+#error "pl110_template.h is only for inclusion by pl110.c"

+#define NAME glue(lblp_, BORDER)

+#define NAME glue(bbbp_, BORDER)

+#define NAME glue(lbbp_, BORDER)

+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));

+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));

+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));

+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));

+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));

+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));

+ COPY_PIXEL(d, rgb_to_pixel32(r, g, b));

+/* Size of a pixel in the QEMU UI output surface, in bytes */

+#define DEST_PIXEL_WIDTH 4

+

+/* Line drawing code to handle the various possible guest pixel formats */

+

+# define SKIP_PIXEL(to) do { to += deststep; } while (0)

+# define COPY_PIXEL(to, from) \

+ do { \

+ *(uint32_t *) to = from; \

+ SKIP_PIXEL(to); \

+ } while (0)

+

+#ifdef HOST_WORDS_BIGENDIAN

+# define SWAP_WORDS 1

+#endif

+

+#define FN_2(x) FN(x + 1) FN(x)

+#define FN_4(x) FN_2(x + 2) FN_2(x)

+

+static void pxa2xx_draw_line2(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t *palette = opaque;

+ uint32_t data;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 2)) & 3]);

+#ifdef SWAP_WORDS

+ FN_4(12)

+ FN_4(8)

+ FN_4(4)

+ FN_4(0)

+#else

+ FN_4(0)

+ FN_4(4)

+ FN_4(8)

+ FN_4(12)

+#endif

+#undef FN

+ width -= 16;

+ src += 4;

+ }

+}

+

+static void pxa2xx_draw_line4(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t *palette = opaque;

+ uint32_t data;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#define FN(x) COPY_PIXEL(dest, palette[(data >> ((x) * 4)) & 0xf]);

+#ifdef SWAP_WORDS

+ FN_2(6)

+ FN_2(4)

+ FN_2(2)

+ FN_2(0)

+#else

+ FN_2(0)

+ FN_2(2)

+ FN_2(4)

+ FN_2(6)

+#endif

+#undef FN

+ width -= 8;

+ src += 4;

+ }

+}

+

+static void pxa2xx_draw_line8(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t *palette = opaque;

+ uint32_t data;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#define FN(x) COPY_PIXEL(dest, palette[(data >> (x)) & 0xff]);

+#ifdef SWAP_WORDS

+ FN(24)

+ FN(16)

+ FN(8)

+ FN(0)

+#else

+ FN(0)

+ FN(8)

+ FN(16)

+ FN(24)

+#endif

+#undef FN

+ width -= 4;

+ src += 4;

+ }

+}

+

+static void pxa2xx_draw_line16(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data;

+ unsigned int r, g, b;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#ifdef SWAP_WORDS

+ data = bswap32(data);

+#endif

+ b = (data & 0x1f) << 3;

+ data >>= 5;

+ g = (data & 0x3f) << 2;

+ data >>= 6;

+ r = (data & 0x1f) << 3;

+ data >>= 5;

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ b = (data & 0x1f) << 3;

+ data >>= 5;

+ g = (data & 0x3f) << 2;

+ data >>= 6;

+ r = (data & 0x1f) << 3;

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ width -= 2;

+ src += 4;

+ }

+}

+

+static void pxa2xx_draw_line16t(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data;

+ unsigned int r, g, b;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#ifdef SWAP_WORDS

+ data = bswap32(data);

+#endif

+ b = (data & 0x1f) << 3;

+ data >>= 5;

+ g = (data & 0x1f) << 3;

+ data >>= 5;

+ r = (data & 0x1f) << 3;

+ data >>= 5;

+ if (data & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ data >>= 1;

+ b = (data & 0x1f) << 3;

+ data >>= 5;

+ g = (data & 0x1f) << 3;

+ data >>= 5;

+ r = (data & 0x1f) << 3;

+ data >>= 5;

+ if (data & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ width -= 2;

+ src += 4;

+ }

+}

+

+static void pxa2xx_draw_line18(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data;

+ unsigned int r, g, b;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#ifdef SWAP_WORDS

+ data = bswap32(data);

+#endif

+ b = (data & 0x3f) << 2;

+ data >>= 6;

+ g = (data & 0x3f) << 2;

+ data >>= 6;

+ r = (data & 0x3f) << 2;

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ width -= 1;

+ src += 4;

+ }

+}

+

+/* The wicked packed format */

+static void pxa2xx_draw_line18p(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data[3];

+ unsigned int r, g, b;

+ while (width > 0) {

+ data[0] = *(uint32_t *) src;

+ src += 4;

+ data[1] = *(uint32_t *) src;

+ src += 4;

+ data[2] = *(uint32_t *) src;

+ src += 4;

+#ifdef SWAP_WORDS

+ data[0] = bswap32(data[0]);

+ data[1] = bswap32(data[1]);

+ data[2] = bswap32(data[2]);

+#endif

+ b = (data[0] & 0x3f) << 2;

+ data[0] >>= 6;

+ g = (data[0] & 0x3f) << 2;

+ data[0] >>= 6;

+ r = (data[0] & 0x3f) << 2;

+ data[0] >>= 12;

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ b = (data[0] & 0x3f) << 2;

+ data[0] >>= 6;

+ g = ((data[1] & 0xf) << 4) | (data[0] << 2);

+ data[1] >>= 4;

+ r = (data[1] & 0x3f) << 2;

+ data[1] >>= 12;

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ b = (data[1] & 0x3f) << 2;

+ data[1] >>= 6;

+ g = (data[1] & 0x3f) << 2;

+ data[1] >>= 6;

+ r = ((data[2] & 0x3) << 6) | (data[1] << 2);

+ data[2] >>= 8;

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ b = (data[2] & 0x3f) << 2;

+ data[2] >>= 6;

+ g = (data[2] & 0x3f) << 2;

+ data[2] >>= 6;

+ r = data[2] << 2;

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ width -= 4;

+ }

+}

+

+static void pxa2xx_draw_line19(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data;

+ unsigned int r, g, b;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#ifdef SWAP_WORDS

+ data = bswap32(data);

+#endif

+ b = (data & 0x3f) << 2;

+ data >>= 6;

+ g = (data & 0x3f) << 2;

+ data >>= 6;

+ r = (data & 0x3f) << 2;

+ data >>= 6;

+ if (data & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ width -= 1;

+ src += 4;

+ }

+}

+

+/* The wicked packed format */

+static void pxa2xx_draw_line19p(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data[3];

+ unsigned int r, g, b;

+ while (width > 0) {

+ data[0] = *(uint32_t *) src;

+ src += 4;

+ data[1] = *(uint32_t *) src;

+ src += 4;

+ data[2] = *(uint32_t *) src;

+ src += 4;

+# ifdef SWAP_WORDS

+ data[0] = bswap32(data[0]);

+ data[1] = bswap32(data[1]);

+ data[2] = bswap32(data[2]);

+# endif

+ b = (data[0] & 0x3f) << 2;

+ data[0] >>= 6;

+ g = (data[0] & 0x3f) << 2;

+ data[0] >>= 6;

+ r = (data[0] & 0x3f) << 2;

+ data[0] >>= 6;

+ if (data[0] & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ data[0] >>= 6;

+ b = (data[0] & 0x3f) << 2;

+ data[0] >>= 6;

+ g = ((data[1] & 0xf) << 4) | (data[0] << 2);

+ data[1] >>= 4;

+ r = (data[1] & 0x3f) << 2;

+ data[1] >>= 6;

+ if (data[1] & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ data[1] >>= 6;

+ b = (data[1] & 0x3f) << 2;

+ data[1] >>= 6;

+ g = (data[1] & 0x3f) << 2;

+ data[1] >>= 6;

+ r = ((data[2] & 0x3) << 6) | (data[1] << 2);

+ data[2] >>= 2;

+ if (data[2] & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ data[2] >>= 6;

+ b = (data[2] & 0x3f) << 2;

+ data[2] >>= 6;

+ g = (data[2] & 0x3f) << 2;

+ data[2] >>= 6;

+ r = data[2] << 2;

+ data[2] >>= 6;

+ if (data[2] & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ width -= 4;

+ }

+}

+

+static void pxa2xx_draw_line24(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data;

+ unsigned int r, g, b;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#ifdef SWAP_WORDS

+ data = bswap32(data);

+#endif

+ b = data & 0xff;

+ data >>= 8;

+ g = data & 0xff;

+ data >>= 8;

+ r = data & 0xff;

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ width -= 1;

+ src += 4;

+ }

+}

+

+static void pxa2xx_draw_line24t(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data;

+ unsigned int r, g, b;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#ifdef SWAP_WORDS

+ data = bswap32(data);

+#endif

+ b = (data & 0x7f) << 1;

+ data >>= 7;

+ g = data & 0xff;

+ data >>= 8;

+ r = data & 0xff;

+ data >>= 8;

+ if (data & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ width -= 1;

+ src += 4;

+ }

+}

+

+static void pxa2xx_draw_line25(void *opaque, uint8_t *dest, const uint8_t *src,

+ int width, int deststep)

+{

+ uint32_t data;

+ unsigned int r, g, b;

+ while (width > 0) {

+ data = *(uint32_t *) src;

+#ifdef SWAP_WORDS

+ data = bswap32(data);

+#endif

+ b = data & 0xff;

+ data >>= 8;

+ g = data & 0xff;

+ data >>= 8;

+ r = data & 0xff;

+ data >>= 8;

+ if (data & 1) {

+ SKIP_PIXEL(dest);

+ } else {

+ COPY_PIXEL(dest, rgb_to_pixel32(r, g, b));

+ }

+ width -= 1;

+ src += 4;

+ }

+}

+

+/* Overlay planes disabled, no transparency */

+static drawfn pxa2xx_draw_fn_32[16] = {

+ [0 ... 0xf] = NULL,

+ [pxa_lcdc_2bpp] = pxa2xx_draw_line2,

+ [pxa_lcdc_4bpp] = pxa2xx_draw_line4,

+ [pxa_lcdc_8bpp] = pxa2xx_draw_line8,

+ [pxa_lcdc_16bpp] = pxa2xx_draw_line16,

+ [pxa_lcdc_18bpp] = pxa2xx_draw_line18,

+ [pxa_lcdc_18pbpp] = pxa2xx_draw_line18p,

+ [pxa_lcdc_24bpp] = pxa2xx_draw_line24,

+};

+

+/* Overlay planes enabled, transparency used */

+static drawfn pxa2xx_draw_fn_32t[16] = {

+ [0 ... 0xf] = NULL,

+ [pxa_lcdc_4bpp] = pxa2xx_draw_line4,

+ [pxa_lcdc_8bpp] = pxa2xx_draw_line8,

+ [pxa_lcdc_16bpp] = pxa2xx_draw_line16t,

+ [pxa_lcdc_19bpp] = pxa2xx_draw_line19,

+ [pxa_lcdc_19pbpp] = pxa2xx_draw_line19p,

+ [pxa_lcdc_24bpp] = pxa2xx_draw_line24t,

+ [pxa_lcdc_25bpp] = pxa2xx_draw_line25,

+};

+

+#undef COPY_PIXEL

+#undef SKIP_PIXEL

+

+#ifdef SWAP_WORDS

+# undef SWAP_WORDS

+#endif

+

+static inline drawfn pxa2xx_drawfn(PXA2xxLCDState *s)

+{

+ if (s->transp) {

+ return pxa2xx_draw_fn_32t[s->bpp];

+ } else {

+ return pxa2xx_draw_fn_32[s->bpp];

+ }

+}

+

+ drawfn fn = pxa2xx_drawfn(s);

+ dest_width = s->xres * DEST_PIXEL_WIDTH;

+ src_width, dest_width, DEST_PIXEL_WIDTH,

+ drawfn fn = pxa2xx_drawfn(s);

+ dest_width = s->yres * DEST_PIXEL_WIDTH;

+ src_width, DEST_PIXEL_WIDTH, -dest_width,

+ drawfn fn = pxa2xx_drawfn(s);

+ dest_width = s->xres * DEST_PIXEL_WIDTH;

+ src_width, -dest_width, -DEST_PIXEL_WIDTH,

+ drawfn fn = pxa2xx_drawfn(s);

+ dest_width = s->yres * DEST_PIXEL_WIDTH;

+ src_width, -DEST_PIXEL_WIDTH, dest_width,

+static void qxl_vm_change_state_handler(void *opaque, bool running,

+static void draw_line8_32(uint8_t *d, const uint8_t *s, int width,

+ const uint32_t *pal)

+{

+ uint8_t v, r, g, b;

+ do {

+ v = ldub_p(s);

+ r = (pal[v] >> 16) & 0xff;

+ g = (pal[v] >> 8) & 0xff;

+ b = (pal[v] >> 0) & 0xff;

+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);

+ s++;

+ d += 4;

+ } while (--width != 0);

+}

+static void draw_line16_32(uint8_t *d, const uint8_t *s, int width,

+ const uint32_t *pal)

+{

+ uint16_t rgb565;

+ uint8_t r, g, b;

+

+ do {

+ rgb565 = lduw_le_p(s);

+ r = (rgb565 >> 8) & 0xf8;

+ g = (rgb565 >> 3) & 0xfc;

+ b = (rgb565 << 3) & 0xf8;

+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);

+ s += 2;

+ d += 4;

+ } while (--width != 0);

+}

+static void draw_line32_32(uint8_t *d, const uint8_t *s, int width,

+ const uint32_t *pal)

+{

+ uint8_t r, g, b;

+

+ do {

+ r = s[2];

+ g = s[1];

+ b = s[0];

+ *(uint32_t *)d = rgb_to_pixel32(r, g, b);

+ s += 4;

+ d += 4;

+ } while (--width != 0);

+}

+/**

+ * Draw hardware cursor image on the given line.

+ */

+static void draw_hwc_line_32(uint8_t *d, const uint8_t *s, int width,

+ const uint8_t *palette, int c_x, int c_y)

+ int i;

+ uint8_t r, g, b, v, bitset = 0;

+

+ /* get cursor position */

+ assert(0 <= c_y && c_y < SM501_HWC_HEIGHT);

+ s += SM501_HWC_WIDTH * c_y / 4; /* 4 pixels per byte */