diff options
| -rw-r--r-- | block.c | 2 | ||||
| -rw-r--r-- | block/qcow2-refcount.c | 2 | ||||
| -rw-r--r-- | cpu-all.h | 2 | ||||
| -rw-r--r-- | cpu-exec.c | 2 | ||||
| -rw-r--r-- | hw/bt.h | 2 | ||||
| -rw-r--r-- | hw/pcie.c | 2 | ||||
| -rw-r--r-- | hw/pcie.h | 2 | ||||
| -rw-r--r-- | hw/pflash_cfi02.c | 2 | ||||
| -rw-r--r-- | target-arm/translate.c | 6 | ||||
| -rw-r--r-- | target-m68k/helper.c | 2 |
10 files changed, 12 insertions, 12 deletions
@@ -747,7 +747,7 @@ DeviceState *bdrv_get_attached(BlockDriverState *bs) * Run consistency checks on an image * * Returns 0 if the check could be completed (it doesn't mean that the image is - * free of errors) or -errno when an internal error occured. The results of the + * free of errors) or -errno when an internal error occurred. The results of the * check are stored in res. */ int bdrv_check(BlockDriverState *bs, BdrvCheckResult *res) diff --git a/block/qcow2-refcount.c b/block/qcow2-refcount.c index 915d85acbf..d62dc1c091 100644 --- a/block/qcow2-refcount.c +++ b/block/qcow2-refcount.c @@ -1063,7 +1063,7 @@ fail: * Checks an image for refcount consistency. * * Returns 0 if no errors are found, the number of errors in case the image is - * detected as corrupted, and -errno when an internal error occured. + * detected as corrupted, and -errno when an internal error occurred. */ int qcow2_check_refcounts(BlockDriverState *bs, BdrvCheckResult *res) { @@ -792,7 +792,7 @@ extern CPUState *cpu_single_env; #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ -#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ +#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occurred. */ #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */ #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */ #define CPU_INTERRUPT_INIT 0x400 /* INIT pending. */ diff --git a/cpu-exec.c b/cpu-exec.c index 2cdcdc5e76..1b20f7b22b 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -509,7 +509,7 @@ int cpu_exec(CPUState *env1) jump normally, then does the exception return when the CPU tries to execute code at the magic address. This will cause the magic PC value to be pushed to - the stack if an interrupt occured at the wrong time. + the stack if an interrupt occurred at the wrong time. We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD @@ -1441,7 +1441,7 @@ typedef struct { #define EVT_FLUSH_OCCURRED 0x11 typedef struct { uint16_t handle; -} __attribute__ ((packed)) evt_flush_occured; +} __attribute__ ((packed)) evt_flush_occurred; #define EVT_FLUSH_OCCURRED_SIZE 2 #define EVT_ROLE_CHANGE 0x12 @@ -176,7 +176,7 @@ static void hotplug_event_notify(PCIDevice *dev) } /* - * A PCI Express Hot-Plug Event has occured, so update slot status register + * A PCI Express Hot-Plug Event has occurred, so update slot status register * and notify OS of the event if necessary. * * 6.7.3 PCI Express Hot-Plug Events @@ -40,7 +40,7 @@ typedef enum { * * Not all the bits of slot control register match with the ones of * slot status. Not some bits of slot status register is used to - * show status, not to report event occurence. + * show status, not to report event occurrence. * So such bits must be masked out when checking the software * notification condition. */ diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index 14bbc34e16..8fdafe6a62 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -367,7 +367,7 @@ static void pflash_write (pflash_t *pfl, target_phys_addr_t offset, case 4: switch (pfl->cmd) { case 0xA0: - /* Ignore writes while flash data write is occuring */ + /* Ignore writes while flash data write is occurring */ /* As we suppose write is immediate, this should never happen */ return; case 0x80: diff --git a/target-arm/translate.c b/target-arm/translate.c index 3119137beb..59190f64ca 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -1331,7 +1331,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest) return 0; } -/* Disassemble an iwMMXt instruction. Returns nonzero if an error occured +/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred (ie. an undefined instruction). */ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) { @@ -2335,7 +2335,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn) return 0; } -/* Disassemble an XScale DSP instruction. Returns nonzero if an error occured +/* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred (ie. an undefined instruction). */ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn) { @@ -2681,7 +2681,7 @@ static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size) return tmp; } -/* Disassemble a VFP instruction. Returns nonzero if an error occured +/* Disassemble a VFP instruction. Returns nonzero if an error occurred (ie. an undefined instruction). */ static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn) { diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 514b03904f..faa8c42ae8 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -714,7 +714,7 @@ void HELPER(macsats)(CPUState *env, uint32_t acc) if (env->macsr & MACSR_V) { env->macsr |= MACSR_PAV0 << acc; if (env->macsr & MACSR_OMC) { - /* The result is saturated to 32 bits, despite overflow occuring + /* The result is saturated to 32 bits, despite overflow occurring at 48 bits. Seems weird, but that's what the hardware docs say. */ result = (result >> 63) ^ 0x7fffffff; |