diff options
| -rw-r--r-- | linux-user/main.c | 1 | ||||
| -rw-r--r-- | target/arm/cpu.h | 1 | ||||
| -rw-r--r-- | target/arm/helper.c | 4 | ||||
| -rw-r--r-- | target/arm/translate.c | 8 |
4 files changed, 14 insertions, 0 deletions
diff --git a/linux-user/main.c b/linux-user/main.c index f5c85574f9..30049581ef 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -573,6 +573,7 @@ void cpu_loop(CPUARMState *env) switch(trapnr) { case EXCP_UDEF: + case EXCP_NOCP: { TaskState *ts = cs->opaque; uint32_t opcode; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4b062d20f3..39bff86daf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -53,6 +53,7 @@ #define EXCP_VIRQ 14 #define EXCP_VFIQ 15 #define EXCP_SEMIHOST 16 /* semihosting call */ +#define EXCP_NOCP 17 /* v7M NOCP UsageFault */ #define ARMV7M_EXCP_RESET 1 #define ARMV7M_EXCP_NMI 2 diff --git a/target/arm/helper.c b/target/arm/helper.c index e6b1c36a95..c23df1b133 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6074,6 +6074,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK; return; + case EXCP_NOCP: + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); + env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; + return; case EXCP_SWI: /* The PC already points to the next instruction. */ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); diff --git a/target/arm/translate.c b/target/arm/translate.c index a7c2abeffe..493c627bcf 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10217,6 +10217,14 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw break; case 6: case 7: case 14: case 15: /* Coprocessor. */ + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* We don't currently implement M profile FP support, + * so this entire space should give a NOCP fault. + */ + gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), + default_exception_el(s)); + break; + } if (((insn >> 24) & 3) == 3) { /* Translate into the equivalent ARM encoding. */ insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28); |