diff options
| -rw-r--r-- | tcg/hppa/tcg-target.c | 1 | ||||
| -rw-r--r-- | tcg/ppc/tcg-target.c | 2 | ||||
| -rw-r--r-- | tcg/sparc/tcg-target.c | 4 |
3 files changed, 4 insertions, 3 deletions
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c index ddce60c81f..4677971e7b 100644 --- a/tcg/hppa/tcg-target.c +++ b/tcg/hppa/tcg-target.c @@ -936,7 +936,6 @@ static const TCGTargetOpDef hppa_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L", "L" } }, - { INDEX_op_qemu_ld32s, { "r", "L", "L" } }, { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } }, { INDEX_op_qemu_st8, { "L", "L", "L" } }, diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 903b69ff01..15d8b851ec 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -1693,7 +1693,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L" } }, - { INDEX_op_qemu_ld32s, { "r", "L" } }, { INDEX_op_qemu_ld64, { "r", "r", "L" } }, { INDEX_op_qemu_st8, { "K", "K" } }, @@ -1706,7 +1705,6 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L", "L" } }, - { INDEX_op_qemu_ld32s, { "r", "L", "L" } }, { INDEX_op_qemu_ld64, { "r", "L", "L", "L" } }, { INDEX_op_qemu_st8, { "K", "K", "K" } }, diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 891b8c4d5c..d4ddaa79b3 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1319,9 +1319,11 @@ static inline void tcg_out_op(TCGContext *s, int opc, const TCGArg *args, case INDEX_op_qemu_ld32u: tcg_out_qemu_ld(s, args, 2); break; +#if TCG_TARGET_REG_BITS == 64 case INDEX_op_qemu_ld32s: tcg_out_qemu_ld(s, args, 2 | 4); break; +#endif case INDEX_op_qemu_st8: tcg_out_qemu_st(s, args, 0); break; @@ -1471,7 +1473,9 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "L" } }, { INDEX_op_qemu_ld16s, { "r", "L" } }, { INDEX_op_qemu_ld32u, { "r", "L" } }, +#if TCG_TARGET_REG_BITS == 64 { INDEX_op_qemu_ld32s, { "r", "L" } }, +#endif { INDEX_op_qemu_st8, { "L", "L" } }, { INDEX_op_qemu_st16, { "L", "L" } }, |