diff options
151 files changed, 1525 insertions, 1156 deletions
diff --git a/.travis.yml b/.travis.yml index 5887055951..f4020dcc6c 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,6 +1,7 @@ # The current Travis default is a VM based 16.04 Xenial on GCE # Additional builds with specific requirements for a full VM need to # be added as additional matrix: entries later on +os: linux dist: xenial language: c compiler: @@ -113,7 +114,7 @@ after_script: - if command -v ccache ; then ccache --show-stats ; fi -matrix: +jobs: include: - name: "GCC static (user)" env: @@ -297,8 +298,7 @@ matrix: - CONFIG="--target-list=x86_64-softmmu" - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" language: python - python: - - "3.5" + python: 3.5 - name: "GCC Python 3.6 (x86_64-softmmu)" @@ -306,8 +306,7 @@ matrix: - CONFIG="--target-list=x86_64-softmmu" - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" language: python - python: - - "3.6" + python: 3.6 # Acceptance (Functional) tests @@ -401,7 +400,7 @@ matrix: - name: "GCC check-tcg (some-softmmu)" env: - CONFIG="--enable-debug-tcg --target-list=xtensa-softmmu,arm-softmmu,aarch64-softmmu,alpha-softmmu" - - TEST_BUILD_CMD="make -j${JOBS} build-tcg" + - TEST_BUILD_CMD="make build-tcg" - TEST_CMD="make check-tcg" - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-debug-tcg" @@ -410,7 +409,7 @@ matrix: - name: "GCC plugins check-tcg (some-softmmu)" env: - CONFIG="--enable-plugins --enable-debug-tcg --target-list=xtensa-softmmu,arm-softmmu,aarch64-softmmu,alpha-softmmu" - - TEST_BUILD_CMD="make -j${JOBS} build-tcg" + - TEST_BUILD_CMD="make build-tcg" - TEST_CMD="make check-tcg" - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-debug-tcg" @@ -509,6 +508,16 @@ matrix: env: - TEST_CMD="make check check-tcg V=1" - CONFIG="--disable-containers --target-list=${MAIN_SOFTMMU_TARGETS},s390x-linux-user" + script: + - ( cd ${SRC_DIR} ; git submodule update --init roms/SLOF ) + - BUILD_RC=0 && make -j${JOBS} || BUILD_RC=$? + - | + if [ "$BUILD_RC" -eq 0 ] ; then + mv pc-bios/s390-ccw/*.img pc-bios/ ; + ${TEST_CMD} ; + else + $(exit $BUILD_RC); + fi # Release builds # The make-release script expect a QEMU version, so our tag must start with a 'v'. diff --git a/MAINTAINERS b/MAINTAINERS index ff06934bb5..df1786db32 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -404,6 +404,14 @@ S: Supported F: target/i386/kvm.c F: scripts/kvm/vmxcap +WHPX CPUs +M: Sunil Muthuswamy <sunilmut@microsoft.com> +S: Supported +F: target/i386/whpx-all.c +F: target/i386/whp-dispatch.h +F: accel/stubs/whpx-stub.c +F: include/sysemu/whpx.h + Guest CPU Cores (Xen) --------------------- X86 Xen CPUs diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index c111312dfd..439a4efe52 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -308,13 +308,23 @@ static int kvm_set_user_memory_region(KVMMemoryListener *kml, KVMSlot *slot, boo /* Set the slot size to 0 before setting the slot to the desired * value. This is needed based on KVM commit 75d61fbc. */ mem.memory_size = 0; - kvm_vm_ioctl(s, KVM_SET_USER_MEMORY_REGION, &mem); + ret = kvm_vm_ioctl(s, KVM_SET_USER_MEMORY_REGION, &mem); + if (ret < 0) { + goto err; + } } mem.memory_size = slot->memory_size; ret = kvm_vm_ioctl(s, KVM_SET_USER_MEMORY_REGION, &mem); slot->old_flags = mem.flags; +err: trace_kvm_set_user_memory(mem.slot, mem.flags, mem.guest_phys_addr, mem.memory_size, mem.userspace_addr, ret); + if (ret < 0) { + error_report("%s: KVM_SET_USER_MEMORY_REGION failed, slot=%d," + " start=0x%" PRIx64 ", size=0x%" PRIx64 ": %s", + __func__, mem.slot, slot->start_addr, + (uint64_t)mem.memory_size, strerror(errno)); + } return ret; } @@ -2178,9 +2188,9 @@ void kvm_flush_coalesced_mmio_buffer(void) ent = &ring->coalesced_mmio[ring->first]; if (ent->pio == 1) { - address_space_rw(&address_space_io, ent->phys_addr, - MEMTXATTRS_UNSPECIFIED, ent->data, - ent->len, true); + address_space_write(&address_space_io, ent->phys_addr, + MEMTXATTRS_UNSPECIFIED, ent->data, + ent->len); } else { cpu_physical_memory_write(ent->phys_addr, ent->data, ent->len); } diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c index be64020746..c8c355f5aa 100644 --- a/backends/hostmem-file.c +++ b/backends/hostmem-file.c @@ -18,13 +18,6 @@ #include "sysemu/sysemu.h" #include "qom/object_interfaces.h" -/* hostmem-file.c */ -/** - * @TYPE_MEMORY_BACKEND_FILE: - * name of backend that uses mmap on a file descriptor - */ -#define TYPE_MEMORY_BACKEND_FILE "memory-backend-file" - #define MEMORY_BACKEND_FILE(obj) \ OBJECT_CHECK(HostMemoryBackendFile, (obj), TYPE_MEMORY_BACKEND_FILE) @@ -58,7 +51,6 @@ file_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) return; } - backend->force_prealloc = mem_prealloc; name = host_memory_backend_get_name(backend); memory_region_init_ram_from_file(&backend->mr, OBJECT(backend), name, diff --git a/backends/hostmem-memfd.c b/backends/hostmem-memfd.c index 26070b425e..74ba9879c4 100644 --- a/backends/hostmem-memfd.c +++ b/backends/hostmem-memfd.c @@ -45,7 +45,6 @@ memfd_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) return; } - backend->force_prealloc = mem_prealloc; fd = qemu_memfd_create(TYPE_MEMORY_BACKEND_MEMFD, backend->size, m->hugetlb, m->hugetlbsize, m->seal ? F_SEAL_GROW | F_SEAL_SHRINK | F_SEAL_SEAL : 0, diff --git a/backends/hostmem-ram.c b/backends/hostmem-ram.c index 6aab8d3a73..5cc53e76c9 100644 --- a/backends/hostmem-ram.c +++ b/backends/hostmem-ram.c @@ -16,8 +16,6 @@ #include "qemu/module.h" #include "qom/object_interfaces.h" -#define TYPE_MEMORY_BACKEND_RAM "memory-backend-ram" - static void ram_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) { diff --git a/backends/hostmem.c b/backends/hostmem.c index e773bdfa6e..a70867b255 100644 --- a/backends/hostmem.c +++ b/backends/hostmem.c @@ -215,7 +215,7 @@ static bool host_memory_backend_get_prealloc(Object *obj, Error **errp) { HostMemoryBackend *backend = MEMORY_BACKEND(obj); - return backend->prealloc || backend->force_prealloc; + return backend->prealloc; } static void host_memory_backend_set_prealloc(Object *obj, bool value, @@ -223,15 +223,6 @@ static void host_memory_backend_set_prealloc(Object *obj, bool value, { Error *local_err = NULL; HostMemoryBackend *backend = MEMORY_BACKEND(obj); - MachineState *ms = MACHINE(qdev_get_machine()); - - if (backend->force_prealloc) { - if (value) { - error_setg(errp, - "remove -mem-prealloc to use the prealloc property"); - return; - } - } if (!host_memory_backend_mr_inited(backend)) { backend->prealloc = value; @@ -243,7 +234,7 @@ static void host_memory_backend_set_prealloc(Object *obj, bool value, void *ptr = memory_region_get_ram_ptr(&backend->mr); uint64_t sz = memory_region_size(&backend->mr); - os_mem_prealloc(fd, ptr, sz, ms->smp.cpus, &local_err); + os_mem_prealloc(fd, ptr, sz, backend->prealloc_threads, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -252,14 +243,43 @@ static void host_memory_backend_set_prealloc(Object *obj, bool value, } } +static void host_memory_backend_get_prealloc_threads(Object *obj, Visitor *v, + const char *name, void *opaque, Error **errp) +{ + HostMemoryBackend *backend = MEMORY_BACKEND(obj); + visit_type_uint32(v, name, &backend->prealloc_threads, errp); +} + +static void host_memory_backend_set_prealloc_threads(Object *obj, Visitor *v, + const char *name, void *opaque, Error **errp) +{ + HostMemoryBackend *backend = MEMORY_BACKEND(obj); + Error *local_err = NULL; + uint32_t value; + + visit_type_uint32(v, name, &value, &local_err); + if (local_err) { + goto out; + } + if (value <= 0) { + error_setg(&local_err, + "property '%s' of %s doesn't take value '%d'", + name, object_get_typename(obj), value); + goto out; + } + backend->prealloc_threads = value; +out: + error_propagate(errp, local_err); +} + static void host_memory_backend_init(Object *obj) { HostMemoryBackend *backend = MEMORY_BACKEND(obj); MachineState *machine = MACHINE(qdev_get_machine()); + /* TODO: convert access to globals to compat properties */ backend->merge = machine_mem_merge(machine); backend->dump = machine_dump_guest_core(machine); - backend->prealloc = mem_prealloc; } static void host_memory_backend_post_init(Object *obj) @@ -313,7 +333,6 @@ host_memory_backend_memory_complete(UserCreatable *uc, Error **errp) { HostMemoryBackend *backend = MEMORY_BACKEND(uc); HostMemoryBackendClass *bc = MEMORY_BACKEND_GET_CLASS(uc); - MachineState *ms = MACHINE(qdev_get_machine()); Error *local_err = NULL; void *ptr; uint64_t sz; @@ -378,7 +397,7 @@ host_memory_backend_memory_complete(UserCreatable *uc, Error **errp) */ if (backend->prealloc) { os_mem_prealloc(memory_region_get_fd(&backend->mr), ptr, sz, - ms->smp.cpus, &local_err); + backend->prealloc_threads, &local_err); if (local_err) { goto out; } @@ -456,6 +475,12 @@ host_memory_backend_class_init(ObjectClass *oc, void *data) host_memory_backend_set_prealloc, &error_abort); object_class_property_set_description(oc, "prealloc", "Preallocate memory", &error_abort); + object_class_property_add(oc, "prealloc-threads", "int", + host_memory_backend_get_prealloc_threads, + host_memory_backend_set_prealloc_threads, + NULL, NULL, &error_abort); + object_class_property_set_description(oc, "prealloc-threads", + "Number of CPU threads to use for prealloc", &error_abort); object_class_property_add(oc, "size", "int", host_memory_backend_get_size, host_memory_backend_set_size, diff --git a/block/nbd.c b/block/nbd.c index 6d3b22f844..976be76647 100644 --- a/block/nbd.c +++ b/block/nbd.c @@ -95,6 +95,19 @@ typedef struct BDRVNBDState { static int nbd_client_connect(BlockDriverState *bs, Error **errp); +static void nbd_clear_bdrvstate(BDRVNBDState *s) +{ + object_unref(OBJECT(s->tlscreds)); + qapi_free_SocketAddress(s->saddr); + s->saddr = NULL; + g_free(s->export); + s->export = NULL; + g_free(s->tlscredsid); + s->tlscredsid = NULL; + g_free(s->x_dirty_bitmap); + s->x_dirty_bitmap = NULL; +} + static void nbd_channel_error(BDRVNBDState *s, int ret) { if (ret == -EIO) { @@ -1528,8 +1541,10 @@ static int nbd_parse_uri(const char *filename, QDict *options) goto out; } - p = uri->path ? uri->path : "/"; - p += strspn(p, "/"); + p = uri->path ? uri->path : ""; + if (p[0] == '/') { + p++; + } if (p[0]) { qdict_put_str(options, "export", p); } @@ -1877,11 +1892,7 @@ static int nbd_process_options(BlockDriverState *bs, QDict *options, error: if (ret < 0) { - object_unref(OBJECT(s->tlscreds)); - qapi_free_SocketAddress(s->saddr); - g_free(s->export); - g_free(s->tlscredsid); - g_free(s->x_dirty_bitmap); + nbd_clear_bdrvstate(s); } qemu_opts_del(opts); return ret; @@ -1904,6 +1915,7 @@ static int nbd_open(BlockDriverState *bs, QDict *options, int flags, ret = nbd_client_connect(bs, errp); if (ret < 0) { + nbd_clear_bdrvstate(s); return ret; } /* successfully connected */ @@ -1960,12 +1972,7 @@ static void nbd_close(BlockDriverState *bs) BDRVNBDState *s = bs->opaque; nbd_client_close(bs); - - object_unref(OBJECT(s->tlscreds)); - qapi_free_SocketAddress(s->saddr); - g_free(s->export); - g_free(s->tlscredsid); - g_free(s->x_dirty_bitmap); + nbd_clear_bdrvstate(s); } static int64_t nbd_getlength(BlockDriverState *bs) diff --git a/dma-helpers.c b/dma-helpers.c index d3871dc61e..e8a26e81e1 100644 --- a/dma-helpers.c +++ b/dma-helpers.c @@ -28,8 +28,8 @@ int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len) memset(fillbuf, c, FILLBUF_SIZE); while (len > 0) { l = len < FILLBUF_SIZE ? len : FILLBUF_SIZE; - error |= address_space_rw(as, addr, MEMTXATTRS_UNSPECIFIED, - fillbuf, l, true); + error |= address_space_write(as, addr, MEMTXATTRS_UNSPECIFIED, + fillbuf, l); len -= l; addr += l; } diff --git a/docs/devel/tcg-plugins.rst b/docs/devel/tcg-plugins.rst index 718eef00f2..a05990906c 100644 --- a/docs/devel/tcg-plugins.rst +++ b/docs/devel/tcg-plugins.rst @@ -51,8 +51,17 @@ about how QEMU's translation works to the plugins. While there are conceptions such as translation time and translation blocks the details are opaque to plugins. The plugin is able to query select details of instructions and system configuration only through the -exported *qemu_plugin* functions. The types used to describe -instructions and events are opaque to the plugins themselves. +exported *qemu_plugin* functions. + +Query Handle Lifetime +--------------------- + +Each callback provides an opaque anonymous information handle which +can usually be further queried to find out information about a +translation, instruction or operation. The handles themselves are only +valid during the lifetime of the callback so it is important that any +information that is needed is extracted during the callback and saved +by the plugin. Usage ===== @@ -1668,59 +1668,18 @@ static int find_max_backend_pagesize(Object *obj, void *opaque) long qemu_minrampagesize(void) { long hpsize = LONG_MAX; - long mainrampagesize; - Object *memdev_root; - MachineState *ms = MACHINE(qdev_get_machine()); - - mainrampagesize = qemu_mempath_getpagesize(mem_path); - - /* it's possible we have memory-backend objects with - * hugepage-backed RAM. these may get mapped into system - * address space via -numa parameters or memory hotplug - * hooks. we want to take these into account, but we - * also want to make sure these supported hugepage - * sizes are applicable across the entire range of memory - * we may boot from, so we take the min across all - * backends, and assume normal pages in cases where a - * backend isn't backed by hugepages. - */ - memdev_root = object_resolve_path("/objects", NULL); - if (memdev_root) { - object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize); - } - if (hpsize == LONG_MAX) { - /* No additional memory regions found ==> Report main RAM page size */ - return mainrampagesize; - } - - /* If NUMA is disabled or the NUMA nodes are not backed with a - * memory-backend, then there is at least one node using "normal" RAM, - * so if its page size is smaller we have got to report that size instead. - */ - if (hpsize > mainrampagesize && - (ms->numa_state == NULL || - ms->numa_state->num_nodes == 0 || - ms->numa_state->nodes[0].node_memdev == NULL)) { - static bool warned; - if (!warned) { - error_report("Huge page support disabled (n/a for main memory)."); - warned = true; - } - return mainrampagesize; - } + Object *memdev_root = object_resolve_path("/objects", NULL); + object_child_foreach(memdev_root, find_min_backend_pagesize, &hpsize); return hpsize; } long qemu_maxrampagesize(void) { - long pagesize = qemu_mempath_getpagesize(mem_path); + long pagesize = 0; Object *memdev_root = object_resolve_path("/objects", NULL); - if (memdev_root) { - object_child_foreach(memdev_root, find_max_backend_pagesize, - &pagesize); - } + object_child_foreach(memdev_root, find_max_backend_pagesize, &pagesize); return pagesize; } #else @@ -1843,8 +1802,6 @@ static void *file_ram_alloc(RAMBlock *block, bool truncate, Error **errp) { - Error *err = NULL; - MachineState *ms = MACHINE(qdev_get_machine()); void *area; block->page_size = qemu_fd_getpagesize(fd); @@ -1900,15 +1857,6 @@ static void *file_ram_alloc(RAMBlock *block, return NULL; } - if (mem_prealloc) { - os_mem_prealloc(fd, area, memory, ms->smp.cpus, &err); - if (err) { - error_propagate(errp, err); - qemu_ram_munmap(fd, area, memory); - return NULL; - } - } - block->fd = fd; return area; } @@ -2356,9 +2304,9 @@ RAMBlock *qemu_ram_alloc_from_fd(ram_addr_t size, MemoryRegion *mr, size = HOST_PAGE_ALIGN(size); file_size = get_file_size(fd); if (file_size > 0 && file_size < size) { - error_setg(errp, "backing store %s size 0x%" PRIx64 + error_setg(errp, "backing store size 0x%" PRIx64 " does not match 'size' option 0x" RAM_ADDR_FMT, - mem_path, file_size, size); + file_size, size); return NULL; } @@ -2788,9 +2736,9 @@ void cpu_check_watchpoint(CPUState *cpu, vaddr addr, vaddr len, } static MemTxResult flatview_read(FlatView *fv, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, hwaddr len); + MemTxAttrs attrs, void *buf, hwaddr len); static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len); + const void *buf, hwaddr len); static bool flatview_access_valid(FlatView *fv, hwaddr addr, hwaddr len, bool is_write, MemTxAttrs attrs); @@ -3027,11 +2975,12 @@ MemoryRegion *get_system_io(void) /* physical memory access (slow version, mainly for debug) */ #if defined(CONFIG_USER_ONLY) int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - uint8_t *buf, target_ulong len, int is_write) + void *ptr, target_ulong len, bool is_write) { int flags; target_ulong l, page; void * p; + uint8_t *buf = ptr; while (len > 0) { page = addr & TARGET_PAGE_MASK; @@ -3155,14 +3104,15 @@ static bool prepare_mmio_access(MemoryRegion *mr) /* Called within RCU critical section. */ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, + const void *ptr, hwaddr len, hwaddr addr1, hwaddr l, MemoryRegion *mr) { - uint8_t *ptr; + uint8_t *ram_ptr; uint64_t val; MemTxResult result = MEMTX_OK; bool release_lock = false; + const uint8_t *buf = ptr; for (;;) { if (!memory_access_is_direct(mr, true)) { @@ -3175,8 +3125,8 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, size_memop(l), attrs); } else { /* RAM case */ - ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); - memcpy(ptr, buf, l); + ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); + memcpy(ram_ptr, buf, l); invalidate_and_set_dirty(mr, addr1, l); } @@ -3202,7 +3152,7 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr, /* Called from RCU critical section. */ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len) + const void *buf, hwaddr len) { hwaddr l; hwaddr addr1; @@ -3219,14 +3169,15 @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs, /* Called within RCU critical section. */ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, + MemTxAttrs attrs, void *ptr, hwaddr len, hwaddr addr1, hwaddr l, MemoryRegion *mr) { - uint8_t *ptr; + uint8_t *ram_ptr; uint64_t val; MemTxResult result = MEMTX_OK; bool release_lock = false; + uint8_t *buf = ptr; for (;;) { if (!memory_access_is_direct(mr, false)) { @@ -3238,8 +3189,8 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, stn_he_p(buf, l, val); } else { /* RAM case */ - ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); - memcpy(buf, ptr, l); + ram_ptr = qemu_ram_ptr_length(mr->ram_block, addr1, &l, false); + memcpy(buf, ram_ptr, l); } if (release_lock) { @@ -3264,7 +3215,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, /* Called from RCU critical section. */ static MemTxResult flatview_read(FlatView *fv, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, hwaddr len) + MemTxAttrs attrs, void *buf, hwaddr len) { hwaddr l; hwaddr addr1; @@ -3277,7 +3228,7 @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr, } MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, hwaddr len) + MemTxAttrs attrs, void *buf, hwaddr len) { MemTxResult result = MEMTX_OK; FlatView *fv; @@ -3293,7 +3244,7 @@ MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len) + const void *buf, hwaddr len) { MemTxResult result = MEMTX_OK; FlatView *fv; @@ -3308,7 +3259,7 @@ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, } MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - uint8_t *buf, hwaddr len, bool is_write) + void *buf, hwaddr len, bool is_write) { if (is_write) { return address_space_write(as, addr, attrs, buf, len); @@ -3317,8 +3268,8 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, } } -void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, - hwaddr len, int is_write) +void cpu_physical_memory_rw(hwaddr addr, void *buf, + hwaddr len, bool is_write) { address_space_rw(&address_space_memory, addr, MEMTXATTRS_UNSPECIFIED, buf, len, is_write); @@ -3332,14 +3283,15 @@ enum write_rom_type { static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, + const void *ptr, hwaddr len, enum write_rom_type type) { hwaddr l; - uint8_t *ptr; + uint8_t *ram_ptr; hwaddr addr1; MemoryRegion *mr; + const uint8_t *buf = ptr; RCU_READ_LOCK_GUARD(); while (len > 0) { @@ -3351,14 +3303,14 @@ static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, l = memory_access_size(mr, l, addr1); } else { /* ROM/RAM case */ - ptr = qemu_map_ram_ptr(mr->ram_block, addr1); + ram_ptr = qemu_map_ram_ptr(mr->ram_block, addr1); switch (type) { case WRITE_DATA: - memcpy(ptr, buf, l); + memcpy(ram_ptr, buf, l); invalidate_and_set_dirty(mr, addr1, l); break; case FLUSH_CACHE: - flush_icache_range((uintptr_t)ptr, (uintptr_t)ptr + l); + flush_icache_range((uintptr_t)ram_ptr, (uintptr_t)ram_ptr + l); break; } } @@ -3372,7 +3324,7 @@ static inline MemTxResult address_space_write_rom_internal(AddressSpace *as, /* used for ROM loading : can write in RAM and ROM */ MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len) + const void *buf, hwaddr len) { return address_space_write_rom_internal(as, addr, attrs, buf, len, WRITE_DATA); @@ -3602,11 +3554,11 @@ void *address_space_map(AddressSpace *as, } /* Unmaps a memory region previously mapped by address_space_map(). - * Will also mark the memory as dirty if is_write == 1. access_len gives + * Will also mark the memory as dirty if is_write is true. access_len gives * the amount of memory that was actually read or written by the caller. */ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, - int is_write, hwaddr access_len) + bool is_write, hwaddr access_len) { if (buffer != bounce.buffer) { MemoryRegion *mr; @@ -3636,14 +3588,14 @@ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, void *cpu_physical_memory_map(hwaddr addr, hwaddr *plen, - int is_write) + bool is_write) { return address_space_map(&address_space_memory, addr, plen, is_write, MEMTXATTRS_UNSPECIFIED); } void cpu_physical_memory_unmap(void *buffer, hwaddr len, - int is_write, hwaddr access_len) + bool is_write, hwaddr access_len) { return address_space_unmap(&address_space_memory, buffer, len, is_write, access_len); } @@ -3794,10 +3746,11 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr, /* virtual memory access for debug (includes writing to ROM) */ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - uint8_t *buf, target_ulong len, int is_write) + void *ptr, target_ulong len, bool is_write) { hwaddr phys_addr; target_ulong l, page; + uint8_t *buf = ptr; cpu_synchronize_state(cpu); while (len > 0) { @@ -3818,8 +3771,8 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, address_space_write_rom(cpu->cpu_ases[asidx].as, phys_addr, attrs, buf, l); } else { - address_space_rw(cpu->cpu_ases[asidx].as, phys_addr, - attrs, buf, l, 0); + address_space_read(cpu->cpu_ases[asidx].as, phys_addr, attrs, buf, + l); } len -= l; buf += l; diff --git a/hw/alpha/alpha_sys.h b/hw/alpha/alpha_sys.h index 95033d7f0b..bc0a286226 100644 --- a/hw/alpha/alpha_sys.h +++ b/hw/alpha/alpha_sys.h @@ -11,7 +11,7 @@ #include "hw/intc/i8259.h" -PCIBus *typhoon_init(ram_addr_t, ISABus **, qemu_irq *, AlphaCPU *[4], +PCIBus *typhoon_init(MemoryRegion *, ISABus **, qemu_irq *, AlphaCPU *[4], pci_map_irq_fn); /* alpha_pci.c. */ diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index a8f9a89cc4..8d71a30617 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -75,7 +75,7 @@ static void clipper_init(MachineState *machine) cpus[0]->env.trap_arg2 = smp_cpus; /* Init the chipset. */ - pci_bus = typhoon_init(ram_size, &isa_bus, &rtc_irq, cpus, + pci_bus = typhoon_init(machine->ram, &isa_bus, &rtc_irq, cpus, clipper_pci_map_irq); /* Since we have an SRM-compatible PALcode, use the SRM epoch. */ @@ -183,6 +183,7 @@ static void clipper_machine_init(MachineClass *mc) mc->max_cpus = 4; mc->is_default = 1; mc->default_cpu_type = ALPHA_CPU_TYPE_NAME("ev67"); + mc->default_ram_id = "ram"; } DEFINE_MACHINE("clipper", clipper_machine_init) diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index 179e1f7658..1795e2f29d 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -58,7 +58,6 @@ typedef struct TyphoonState { TyphoonCchip cchip; TyphoonPchip pchip; MemoryRegion dchip_region; - MemoryRegion ram_region; } TyphoonState; /* Called when one of DRIR or DIM changes. */ @@ -817,8 +816,7 @@ static void typhoon_alarm_timer(void *opaque) cpu_interrupt(CPU(s->cchip.cpu[cpu]), CPU_INTERRUPT_TIMER); } -PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, - qemu_irq *p_rtc_irq, +PCIBus *typhoon_init(MemoryRegion *ram, ISABus **isa_bus, qemu_irq *p_rtc_irq, AlphaCPU *cpus[4], pci_map_irq_fn sys_map_irq) { MemoryRegion *addr_space = get_system_memory(); @@ -851,9 +849,7 @@ PCIBus *typhoon_init(ram_addr_t ram_size, ISABus **isa_bus, /* Main memory region, 0x00.0000.0000. Real hardware supports 32GB, but the address space hole reserved at this point is 8TB. */ - memory_region_allocate_system_memory(&s->ram_region, OBJECT(s), "ram", - ram_size); - memory_region_add_subregion(addr_space, 0, &s->ram_region); + memory_region_add_subregion(addr_space, 0, ram); /* TIGbus, 0x801.0000.0000, 1GB. */ /* ??? The TIGbus is used for delivering interrupts, and access to diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a17843f0d3..a6a2102a93 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -35,7 +35,6 @@ static struct arm_boot_info aspeed_board_binfo = { struct AspeedBoardState { AspeedSoCState soc; MemoryRegion ram_container; - MemoryRegion ram; MemoryRegion max_ram; }; @@ -197,6 +196,7 @@ static void aspeed_machine_init(MachineState *machine) memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", UINT32_MAX); + memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); object_initialize_child(OBJECT(machine), "soc", &bmc->soc, (sizeof(bmc->soc)), amc->soc_name, &error_abort, @@ -204,8 +204,12 @@ static void aspeed_machine_init(MachineState *machine) sc = ASPEED_SOC_GET_CLASS(&bmc->soc); + /* + * This will error out if isize is not supported by memory controller. + */ object_property_set_uint(OBJECT(&bmc->soc), ram_size, "ram-size", - &error_abort); + &error_fatal); + object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap1, "hw-strap1", &error_abort); object_property_set_int(OBJECT(&bmc->soc), amc->hw_strap2, "hw-strap2", @@ -228,15 +232,6 @@ static void aspeed_machine_init(MachineState *machine) object_property_set_bool(OBJECT(&bmc->soc), true, "realized", &error_abort); - /* - * Allocate RAM after the memory controller has checked the size - * was valid. If not, a default value is used. - */ - ram_size = object_property_get_uint(OBJECT(&bmc->soc), "ram-size", - &error_abort); - - memory_region_allocate_system_memory(&bmc->ram, NULL, "ram", ram_size); - memory_region_add_subregion(&bmc->ram_container, 0, &bmc->ram); memory_region_add_subregion(get_system_memory(), sc->memmap[ASPEED_SDRAM], &bmc->ram_container); @@ -439,6 +434,7 @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data) mc->no_floppy = 1; mc->no_cdrom = 1; mc->no_parallel = 1; + mc->default_ram_id = "ram"; aspeed_machine_class_props_init(oc); } diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 0c213ca627..fef4072db1 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -327,8 +327,7 @@ static void set_kernel_args(const struct arm_boot_info *info, AddressSpace *as) cmdline_size = strlen(info->kernel_cmdline); address_space_write(as, p + 8, MEMTXATTRS_UNSPECIFIED, - (const uint8_t *)info->kernel_cmdline, - cmdline_size + 1); + info->kernel_cmdline, cmdline_size + 1); cmdline_size = (cmdline_size >> 2) + 1; WRITE_WORD(p, cmdline_size + 2); WRITE_WORD(p, 0x54410009); @@ -420,8 +419,7 @@ static void set_kernel_args_old(const struct arm_boot_info *info, } s = info->kernel_cmdline; if (s) { - address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, - (const uint8_t *)s, strlen(s) + 1); + address_space_write(as, p, MEMTXATTRS_UNSPECIFIED, s, strlen(s) + 1); } else { WRITE_WORD(p, 0); } diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 970a4405cc..4992084a3f 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -10,6 +10,7 @@ */ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/cutils.h" #include "hw/sysbus.h" #include "hw/boards.h" #include "strongarm.h" @@ -27,13 +28,18 @@ static void collie_init(MachineState *machine) { StrongARMState *s; DriveInfo *dinfo; - MemoryRegion *sdram = g_new(MemoryRegion, 1); + MachineClass *mc = MACHINE_GET_CLASS(machine); + + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } s = sa1110_init(machine->cpu_type); - memory_region_allocate_system_memory(sdram, NULL, "strongarm.sdram", - collie_binfo.ram_size); - memory_region_add_subregion(get_system_memory(), SA_SDCS0, sdram); + memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000, @@ -57,6 +63,8 @@ static void collie_machine_init(MachineClass *mc) mc->init = collie_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("sa1110"); + mc->default_ram_size = 0x20000000; + mc->default_ram_id = "strongarm.sdram"; } DEFINE_MACHINE("collie", collie_machine_init) diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 6dc2f1d6b6..089f9a30c1 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -28,52 +28,42 @@ static struct arm_boot_info cubieboard_binfo = { .board_id = 0x1008, }; -typedef struct CubieBoardState { - AwA10State *a10; - MemoryRegion sdram; -} CubieBoardState; - static void cubieboard_init(MachineState *machine) { - CubieBoardState *s = g_new(CubieBoardState, 1); + AwA10State *a10 = AW_A10(object_new(TYPE_AW_A10)); Error *err = NULL; - s->a10 = AW_A10(object_new(TYPE_AW_A10)); - - object_property_set_int(OBJECT(&s->a10->emac), 1, "phy-addr", &err); + object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err); if (err != NULL) { error_reportf_err(err, "Couldn't set phy address: "); exit(1); } - object_property_set_int(OBJECT(&s->a10->timer), 32768, "clk0-freq", &err); + object_property_set_int(OBJECT(&a10->timer), 32768, "clk0-freq", &err); if (err != NULL) { error_reportf_err(err, "Couldn't set clk0 frequency: "); exit(1); } - object_property_set_int(OBJECT(&s->a10->timer), 24000000, "clk1-freq", - &err); + object_property_set_int(OBJECT(&a10->timer), 24000000, "clk1-freq", &err); if (err != NULL) { error_reportf_err(err, "Couldn't set clk1 frequency: "); exit(1); } - object_property_set_bool(OBJECT(s->a10), true, "realized", &err); + object_property_set_bool(OBJECT(a10), true, "realized", &err); if (err != NULL) { error_reportf_err(err, "Couldn't realize Allwinner A10: "); exit(1); } - memory_region_allocate_system_memory(&s->sdram, NULL, "cubieboard.ram", - machine->ram_size); memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE, - &s->sdram); + machine->ram); /* TODO create and connect IDE devices for ide_drive_get() */ cubieboard_binfo.ram_size = machine->ram_size; - arm_load_kernel(&s->a10->cpu, machine, &cubieboard_binfo); + arm_load_kernel(&a10->cpu, machine, &cubieboard_binfo); } static void cubieboard_machine_init(MachineClass *mc) @@ -84,6 +74,7 @@ static void cubieboard_machine_init(MachineClass *mc) mc->block_default_type = IF_IDE; mc->units_per_default_bus = 1; mc->ignore_memory_transaction_failures = true; + mc->default_ram_id = "cubieboard.ram"; } DEFINE_MACHINE("cubieboard", cubieboard_machine_init) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index ef3fc2b6a5..518a63e61d 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -35,39 +35,40 @@ #include "hw/loader.h" #include "sysemu/sysemu.h" #include "sysemu/qtest.h" +#include "qemu/units.h" +#include "qemu/cutils.h" #define DIGIC4_ROM0_BASE 0xf0000000 #define DIGIC4_ROM1_BASE 0xf8000000 #define DIGIC4_ROM_MAX_SIZE 0x08000000 -typedef struct DigicBoardState { - DigicState *digic; - MemoryRegion ram; -} DigicBoardState; - typedef struct DigicBoard { - hwaddr ram_size; - void (*add_rom0)(DigicBoardState *, hwaddr, const char *); + void (*add_rom0)(DigicState *, hwaddr, const char *); const char *rom0_def_filename; - void (*add_rom1)(DigicBoardState *, hwaddr, const char *); + void (*add_rom1)(DigicState *, hwaddr, const char *); const char *rom1_def_filename; } DigicBoard; -static void digic4_board_init(DigicBoard *board) +static void digic4_board_init(MachineState *machine, DigicBoard *board) { Error *err = NULL; + DigicState *s = DIGIC(object_new(TYPE_DIGIC)); + MachineClass *mc = MACHINE_GET_CLASS(machine); + + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } - DigicBoardState *s = g_new(DigicBoardState, 1); - - s->digic = DIGIC(object_new(TYPE_DIGIC)); - object_property_set_bool(OBJECT(s->digic), true, "realized", &err); + object_property_set_bool(OBJECT(s), true, "realized", &err); if (err != NULL) { error_reportf_err(err, "Couldn't realize DIGIC SoC: "); exit(1); } - memory_region_allocate_system_memory(&s->ram, NULL, "ram", board->ram_size); - memory_region_add_subregion(get_system_memory(), 0, &s->ram); + memory_region_add_subregion(get_system_memory(), 0, machine->ram); if (board->add_rom0) { board->add_rom0(s, DIGIC4_ROM0_BASE, board->rom0_def_filename); @@ -78,7 +79,7 @@ static void digic4_board_init(DigicBoard *board) } } -static void digic_load_rom(DigicBoardState *s, hwaddr addr, +static void digic_load_rom(DigicState *s, hwaddr addr, hwaddr max_size, const char *def_filename) { target_long rom_size; @@ -118,7 +119,7 @@ static void digic_load_rom(DigicBoardState *s, hwaddr addr, * Samsung K8P3215UQB * 64M Bit (4Mx16) Page Mode / Multi-Bank NOR Flash Memory */ -static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr, +static void digic4_add_k8p3215uqb_rom(DigicState *s, hwaddr addr, const char *def_filename) { #define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024) @@ -135,14 +136,13 @@ static void digic4_add_k8p3215uqb_rom(DigicBoardState *s, hwaddr addr, } static DigicBoard digic4_board_canon_a1100 = { - .ram_size = 64 * 1024 * 1024, .add_rom1 = digic4_add_k8p3215uqb_rom, .rom1_def_filename = "canon-a1100-rom1.bin", }; static void canon_a1100_init(MachineState *machine) { - digic4_board_init(&digic4_board_canon_a1100); + digic4_board_init(machine, &digic4_board_canon_a1100); } static void canon_a1100_machine_init(MachineClass *mc) @@ -150,6 +150,8 @@ static void canon_a1100_machine_init(MachineClass *mc) mc->desc = "Canon PowerShot A1100 IS"; mc->init = &canon_a1100_init; mc->ignore_memory_transaction_failures = true; + mc->default_ram_size = 64 * MiB; + mc->default_ram_id = "ram"; } DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index 518d935fdf..ac9de9411e 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -236,7 +236,6 @@ enum cxmachines { */ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) { - ram_addr_t ram_size = machine->ram_size; DeviceState *dev = NULL; SysBusDevice *busdev; qemu_irq pic[128]; @@ -247,7 +246,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) qemu_irq cpu_virq[4]; qemu_irq cpu_vfiq[4]; MemoryRegion *sysram; - MemoryRegion *dram; MemoryRegion *sysmem; char *sysboot_filename; @@ -290,10 +288,8 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) } sysmem = get_system_memory(); - dram = g_new(MemoryRegion, 1); - memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size); /* SDRAM at address zero. */ - memory_region_add_subregion(sysmem, 0, dram); + memory_region_add_subregion(sysmem, 0, machine->ram); sysram = g_new(MemoryRegion, 1); memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, @@ -387,7 +383,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) /* TODO create and connect IDE devices for ide_drive_get() */ - highbank_binfo.ram_size = ram_size; + highbank_binfo.ram_size = machine->ram_size; /* highbank requires a dtb in order to boot, and the dtb will override * the board ID. The following value is ignored, so set it to -1 to be * clear that the value is meaningless. @@ -430,6 +426,7 @@ static void highbank_class_init(ObjectClass *oc, void *data) mc->units_per_default_bus = 1; mc->max_cpus = 4; mc->ignore_memory_transaction_failures = true; + mc->default_ram_id = "highbank.dram"; } static const TypeInfo highbank_type = { @@ -448,6 +445,7 @@ static void midway_class_init(ObjectClass *oc, void *data) mc->units_per_default_bus = 1; mc->max_cpus = 4; mc->ignore_memory_transaction_failures = true; + mc->default_ram_id = "highbank.dram"; } static const TypeInfo midway_type = { diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index c76fc2bd94..26713d9a7e 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -32,6 +32,7 @@ #include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "hw/i2c/i2c.h" +#include "qemu/cutils.h" /* Memory map for PDK Emulation Baseboard: * 0x00000000-0x7fffffff See i.MX25 SOC fr support @@ -58,7 +59,6 @@ typedef struct IMX25PDK { FslIMX25State soc; - MemoryRegion ram; MemoryRegion ram_alias; } IMX25PDK; @@ -66,6 +66,7 @@ static struct arm_boot_info imx25_pdk_binfo; static void imx25_pdk_init(MachineState *machine) { + MachineClass *mc = MACHINE_GET_CLASS(machine); IMX25PDK *s = g_new0(IMX25PDK, 1); unsigned int ram_size; unsigned int alias_offset; @@ -78,16 +79,14 @@ static void imx25_pdk_init(MachineState *machine) /* We need to initialize our memory */ if (machine->ram_size > (FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE)) { - warn_report("RAM size " RAM_ADDR_FMT " above max supported, " - "reduced to %x", machine->ram_size, - FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE); - machine->ram_size = FSL_IMX25_SDRAM0_SIZE + FSL_IMX25_SDRAM1_SIZE; + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); } - memory_region_allocate_system_memory(&s->ram, NULL, "imx25.ram", - machine->ram_size); memory_region_add_subregion(get_system_memory(), FSL_IMX25_SDRAM0_ADDR, - &s->ram); + machine->ram); /* initialize the alias memory if any */ for (i = 0, ram_size = machine->ram_size, alias_offset = 0; @@ -107,7 +106,8 @@ static void imx25_pdk_init(MachineState *machine) if (size < ram[i].size) { memory_region_init_alias(&s->ram_alias, NULL, "ram.alias", - &s->ram, alias_offset, ram[i].size - size); + machine->ram, + alias_offset, ram[i].size - size); memory_region_add_subregion(get_system_memory(), ram[i].addr + size, &s->ram_alias); } @@ -135,6 +135,7 @@ static void imx25_pdk_machine_init(MachineClass *mc) mc->desc = "ARM i.MX25 PDK board (ARM926)"; mc->init = imx25_pdk_init; mc->ignore_memory_transaction_failures = true; + mc->default_ram_id = "imx25.ram"; } DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 0cd94d9f09..cc845b8534 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -585,7 +585,6 @@ static void integratorcp_init(MachineState *machine) Object *cpuobj; ARMCPU *cpu; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *ram_alias = g_new(MemoryRegion, 1); qemu_irq pic[32]; DeviceState *dev, *sic, *icp; @@ -605,14 +604,13 @@ static void integratorcp_init(MachineState *machine) cpu = ARM_CPU(cpuobj); - memory_region_allocate_system_memory(ram, NULL, "integrator.ram", - ram_size); /* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */ /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero*/ - memory_region_add_subregion(address_space_mem, 0, ram); + memory_region_add_subregion(address_space_mem, 0, machine->ram); /* And again at address 0x80000000 */ - memory_region_init_alias(ram_alias, NULL, "ram.alias", ram, 0, ram_size); + memory_region_init_alias(ram_alias, NULL, "ram.alias", machine->ram, + 0, ram_size); memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias); dev = qdev_create(NULL, TYPE_INTEGRATOR_CM); @@ -660,6 +658,7 @@ static void integratorcp_machine_init(MachineClass *mc) mc->init = integratorcp_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); + mc->default_ram_id = "integrator.ram"; } DEFINE_MACHINE("integratorcp", integratorcp_machine_init) diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index 1d5ef289d5..34f6bcb491 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -25,6 +25,7 @@ #include "hw/char/serial.h" #include "sysemu/qtest.h" #include "sysemu/sysemu.h" +#include "qemu/cutils.h" /* Memory map for Kzm Emulation Baseboard: * 0x00000000-0x7fffffff See i.MX31 SOC for support @@ -51,7 +52,6 @@ typedef struct IMX31KZM { FslIMX31State soc; - MemoryRegion ram; MemoryRegion ram_alias; } IMX31KZM; @@ -78,16 +78,14 @@ static void kzm_init(MachineState *machine) /* Check the amount of memory is compatible with the SOC */ if (machine->ram_size > (FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE)) { - warn_report("RAM size " RAM_ADDR_FMT " above max supported, " - "reduced to %x", machine->ram_size, - FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE); - machine->ram_size = FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE; + char *sz = size_to_str(FSL_IMX31_SDRAM0_SIZE + FSL_IMX31_SDRAM1_SIZE); + error_report("RAM size more than %s is not supported", sz); + g_free(sz); + exit(EXIT_FAILURE); } - memory_region_allocate_system_memory(&s->ram, NULL, "kzm.ram", - machine->ram_size); memory_region_add_subregion(get_system_memory(), FSL_IMX31_SDRAM0_ADDR, - &s->ram); + machine->ram); /* initialize the alias memory if any */ for (i = 0, ram_size = machine->ram_size, alias_offset = 0; @@ -107,7 +105,8 @@ static void kzm_init(MachineState *machine) if (size < ram[i].size) { memory_region_init_alias(&s->ram_alias, NULL, "ram.alias", - &s->ram, alias_offset, ram[i].size - size); + machine->ram, + alias_offset, ram[i].size - size); memory_region_add_subregion(get_system_memory(), ram[i].addr + size, &s->ram_alias); } @@ -139,6 +138,7 @@ static void kzm_machine_init(MachineClass *mc) mc->desc = "ARM KZM Emulation Baseboard (ARM1136)"; mc->init = kzm_init; mc->ignore_memory_transaction_failures = true; + mc->default_ram_id = "kzm.ram"; } DEFINE_MACHINE("kzm", kzm_machine_init) diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index e90b393a44..23a71ed378 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -19,15 +19,10 @@ #include "qemu/error-report.h" #include "sysemu/qtest.h" -typedef struct { - FslIMX6ULState soc; - MemoryRegion ram; -} MCIMX6ULEVK; - static void mcimx6ul_evk_init(MachineState *machine) { static struct arm_boot_info boot_info; - MCIMX6ULEVK *s = g_new0(MCIMX6ULEVK, 1); + FslIMX6ULState *s; int i; if (machine->ram_size > FSL_IMX6UL_MMDC_SIZE) { @@ -43,15 +38,12 @@ static void mcimx6ul_evk_init(MachineState *machine) .nb_cpus = machine->smp.cpus, }; - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), - TYPE_FSL_IMX6UL, &error_fatal, NULL); - - object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); + s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL)); + object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal); + object_property_set_bool(OBJECT(s), true, "realized", &error_fatal); - memory_region_allocate_system_memory(&s->ram, NULL, "mcimx6ul-evk.ram", - machine->ram_size); - memory_region_add_subregion(get_system_memory(), - FSL_IMX6UL_MMDC_ADDR, &s->ram); + memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR, + machine->ram); for (i = 0; i < FSL_IMX6UL_NUM_USDHCS; i++) { BusState *bus; @@ -61,7 +53,7 @@ static void mcimx6ul_evk_init(MachineState *machine) di = drive_get_next(IF_SD); blk = di ? blk_by_legacy_dinfo(di) : NULL; - bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus"); + bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); carddev = qdev_create(bus, TYPE_SD_CARD); qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); object_property_set_bool(OBJECT(carddev), true, @@ -69,7 +61,7 @@ static void mcimx6ul_evk_init(MachineState *machine) } if (!qtest_enabled()) { - arm_load_kernel(&s->soc.cpu, machine, &boot_info); + arm_load_kernel(&s->cpu, machine, &boot_info); } } @@ -78,5 +70,6 @@ static void mcimx6ul_evk_machine_init(MachineClass *mc) mc->desc = "Freescale i.MX6UL Evaluation Kit (Cortex A7)"; mc->init = mcimx6ul_evk_init; mc->max_cpus = FSL_IMX6UL_NUM_CPUS; + mc->default_ram_id = "mcimx6ul-evk.ram"; } DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init) diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index 0d1f62d30a..de1e264217 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -21,15 +21,10 @@ #include "qemu/error-report.h" #include "sysemu/qtest.h" -typedef struct { - FslIMX7State soc; - MemoryRegion ram; -} MCIMX7Sabre; - static void mcimx7d_sabre_init(MachineState *machine) { static struct arm_boot_info boot_info; - MCIMX7Sabre *s = g_new0(MCIMX7Sabre, 1); + FslIMX7State *s; int i; if (machine->ram_size > FSL_IMX7_MMDC_SIZE) { @@ -45,15 +40,12 @@ static void mcimx7d_sabre_init(MachineState *machine) .nb_cpus = machine->smp.cpus, }; - object_initialize_child(OBJECT(machine), "soc", - &s->soc, sizeof(s->soc), - TYPE_FSL_IMX7, &error_fatal, NULL); - object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_fatal); + s = FSL_IMX7(object_new(TYPE_FSL_IMX7)); + object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal); + object_property_set_bool(OBJECT(s), true, "realized", &error_fatal); - memory_region_allocate_system_memory(&s->ram, NULL, "mcimx7d-sabre.ram", - machine->ram_size); - memory_region_add_subregion(get_system_memory(), - FSL_IMX7_MMDC_ADDR, &s->ram); + memory_region_add_subregion(get_system_memory(), FSL_IMX7_MMDC_ADDR, + machine->ram); for (i = 0; i < FSL_IMX7_NUM_USDHCS; i++) { BusState *bus; @@ -63,7 +55,7 @@ static void mcimx7d_sabre_init(MachineState *machine) di = drive_get_next(IF_SD); blk = di ? blk_by_legacy_dinfo(di) : NULL; - bus = qdev_get_child_bus(DEVICE(&s->soc.usdhc[i]), "sd-bus"); + bus = qdev_get_child_bus(DEVICE(&s->usdhc[i]), "sd-bus"); carddev = qdev_create(bus, TYPE_SD_CARD); qdev_prop_set_drive(carddev, "drive", blk, &error_fatal); object_property_set_bool(OBJECT(carddev), true, @@ -71,7 +63,7 @@ static void mcimx7d_sabre_init(MachineState *machine) } if (!qtest_enabled()) { - arm_load_kernel(&s->soc.cpu[0], machine, &boot_info); + arm_load_kernel(&s->cpu[0], machine, &boot_info); } } @@ -80,5 +72,6 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc) mc->desc = "Freescale i.MX7 DUAL SABRE (Cortex A7)"; mc->init = mcimx7d_sabre_init; mc->max_cpus = FSL_IMX7_NUM_CPUS; + mc->default_ram_id = "mcimx7d-sabre.ram"; } DEFINE_MACHINE("mcimx7d-sabre", mcimx7d_sabre_machine_init) diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c index f8b620bcc6..a8dea7dde1 100644 --- a/hw/arm/mps2-tz.c +++ b/hw/arm/mps2-tz.c @@ -39,6 +39,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/arm/boot.h" @@ -79,7 +80,6 @@ typedef struct { MachineState parent; ARMSSE iotkit; - MemoryRegion psram; MemoryRegion ssram[3]; MemoryRegion ssram1_m; MPS2SCC scc; @@ -388,6 +388,13 @@ static void mps2tz_common_init(MachineState *machine) exit(1); } + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + sysbus_init_child_obj(OBJECT(machine), "iotkit", &mms->iotkit, sizeof(mms->iotkit), mmc->armsse_type); iotkitdev = DEVICE(&mms->iotkit); @@ -458,9 +465,7 @@ static void mps2tz_common_init(MachineState *machine) * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily * call the 16MB our "system memory", as it's the largest lump. */ - memory_region_allocate_system_memory(&mms->psram, - NULL, "mps.ram", 16 * MiB); - memory_region_add_subregion(system_memory, 0x80000000, &mms->psram); + memory_region_add_subregion(system_memory, 0x80000000, machine->ram); /* The overflow IRQs for all UARTs are ORed together. * Tx, Rx and "combined" IRQs are sent to the NVIC separately. @@ -642,6 +647,8 @@ static void mps2tz_class_init(ObjectClass *oc, void *data) mc->init = mps2tz_common_init; iic->check = mps2_tz_idau_check; + mc->default_ram_size = 16 * MiB; + mc->default_ram_id = "mps.ram"; } static void mps2tz_an505_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index d002b126d3..f246213206 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/cutils.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "hw/arm/boot.h" @@ -55,7 +56,6 @@ typedef struct { MachineState parent; ARMv7MState armv7m; - MemoryRegion psram; MemoryRegion ssram1; MemoryRegion ssram1_m; MemoryRegion ssram23; @@ -118,6 +118,13 @@ static void mps2_common_init(MachineState *machine) exit(1); } + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + /* The FPGA images have an odd combination of different RAMs, * because in hardware they are different implementations and * connected to different buses, giving varying performance/size @@ -146,9 +153,7 @@ static void mps2_common_init(MachineState *machine) * This is of no use for QEMU so we don't implement it (as if * zbt_boot_ctrl is always zero). */ - memory_region_allocate_system_memory(&mms->psram, - NULL, "mps.ram", 16 * MiB); - memory_region_add_subregion(system_memory, 0x21000000, &mms->psram); + memory_region_add_subregion(system_memory, 0x21000000, machine->ram); switch (mmc->fpga_type) { case FPGA_AN385: @@ -338,6 +343,8 @@ static void mps2_class_init(ObjectClass *oc, void *data) mc->init = mps2_common_init; mc->max_cpus = 1; + mc->default_ram_size = 16 * MiB; + mc->default_ram_id = "mps.ram"; } static void mps2_an385_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index dc551bb0c0..db8b03cb83 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -32,6 +32,7 @@ #include "sysemu/runstate.h" #include "exec/address-spaces.h" #include "ui/pixel_ops.h" +#include "qemu/cutils.h" #define MP_MISC_BASE 0x80002000 #define MP_MISC_SIZE 0x00001000 @@ -1589,16 +1590,21 @@ static void musicpal_init(MachineState *machine) int i; unsigned long flash_size; DriveInfo *dinfo; + MachineClass *mc = MACHINE_GET_CLASS(machine); MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); + /* For now we use a fixed - the original - RAM size */ + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + cpu = ARM_CPU(cpu_create(machine->cpu_type)); - /* For now we use a fixed - the original - RAM size */ - memory_region_allocate_system_memory(ram, NULL, "musicpal.ram", - MP_RAM_DEFAULT_SIZE); - memory_region_add_subregion(address_space_mem, 0, ram); + memory_region_add_subregion(address_space_mem, 0, machine->ram); memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, &error_fatal); @@ -1714,6 +1720,8 @@ static void musicpal_machine_init(MachineClass *mc) mc->init = musicpal_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); + mc->default_ram_size = MP_RAM_DEFAULT_SIZE; + mc->default_ram_id = "musicpal.ram"; } DEFINE_MACHINE("musicpal", musicpal_machine_init) diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 3fd196fb30..eae800b5c1 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -47,7 +47,6 @@ /* Nokia N8x0 support */ struct n800_s { - MemoryRegion sdram; struct omap_mpu_state_s *mpu; struct rfbi_chip_s blizzard; @@ -1311,13 +1310,19 @@ static void n8x0_init(MachineState *machine, struct arm_boot_info *binfo, int model) { struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); - uint64_t sdram_size = binfo->ram_size; + MachineClass *mc = MACHINE_GET_CLASS(machine); - memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram", - sdram_size); - memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, &s->sdram); + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + + memory_region_add_subregion(get_system_memory(), OMAP2_Q2_BASE, + machine->ram); - s->mpu = omap2420_mpu_init(&s->sdram, machine->cpu_type); + s->mpu = omap2420_mpu_init(machine->ram, machine->cpu_type); /* Setup peripherals * @@ -1383,9 +1388,8 @@ static void n8x0_init(MachineState *machine, * * The code above is for loading the `zImage' file from Nokia * images. */ - load_image_targphys(option_rom[0].name, - OMAP2_Q2_BASE + 0x400000, - sdram_size - 0x400000); + load_image_targphys(option_rom[0].name, OMAP2_Q2_BASE + 0x400000, + machine->ram_size - 0x400000); n800_setup_nolo_tags(nolo_tags); cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); @@ -1395,16 +1399,12 @@ static void n8x0_init(MachineState *machine, static struct arm_boot_info n800_binfo = { .loader_start = OMAP2_Q2_BASE, - /* Actually two chips of 0x4000000 bytes each */ - .ram_size = 0x08000000, .board_id = 0x4f7, .atag_board = n800_atag_setup, }; static struct arm_boot_info n810_binfo = { .loader_start = OMAP2_Q2_BASE, - /* Actually two chips of 0x4000000 bytes each */ - .ram_size = 0x08000000, /* 0x60c and 0x6bf (WiMAX Edition) have been assigned but are not * used by some older versions of the bootloader and 5555 is used * instead (including versions that shipped with many devices). */ @@ -1431,6 +1431,9 @@ static void n800_class_init(ObjectClass *oc, void *data) mc->default_boot_order = ""; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); + /* Actually two chips of 0x4000000 bytes each */ + mc->default_ram_size = 0x08000000; + mc->default_ram_id = "omap2.dram"; } static const TypeInfo n800_type = { @@ -1448,6 +1451,9 @@ static void n810_class_init(ObjectClass *oc, void *data) mc->default_boot_order = ""; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1136-r2"); + /* Actually two chips of 0x4000000 bytes each */ + mc->default_ram_size = 0x08000000; + mc->default_ram_id = "omap2.dram"; } static const TypeInfo n810_type = { diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index be245714db..2bebab4171 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -35,6 +35,7 @@ #include "sysemu/qtest.h" #include "exec/address-spaces.h" #include "cpu.h" +#include "qemu/cutils.h" /*****************************************************************************/ /* Siemens SX1 Cellphone V1 */ @@ -102,8 +103,8 @@ static struct arm_boot_info sx1_binfo = { static void sx1_init(MachineState *machine, const int version) { struct omap_mpu_state_s *mpu; + MachineClass *mc = MACHINE_GET_CLASS(machine); MemoryRegion *address_space = get_system_memory(); - MemoryRegion *dram = g_new(MemoryRegion, 1); MemoryRegion *flash = g_new(MemoryRegion, 1); MemoryRegion *cs = g_new(MemoryRegion, 4); static uint32_t cs0val = 0x00213090; @@ -115,15 +116,20 @@ static void sx1_init(MachineState *machine, const int version) uint32_t flash_size = flash0_size; int be; + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + if (version == 2) { flash_size = flash2_size; } - memory_region_allocate_system_memory(dram, NULL, "omap1.dram", - sx1_binfo.ram_size); - memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, dram); + memory_region_add_subregion(address_space, OMAP_EMIFF_BASE, machine->ram); - mpu = omap310_mpu_init(dram, machine->cpu_type); + mpu = omap310_mpu_init(machine->ram, machine->cpu_type); /* External Flash (EMIFS) */ memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size, @@ -223,6 +229,8 @@ static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) mc->init = sx1_init_v2; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); + mc->default_ram_size = sdram_size; + mc->default_ram_id = "omap1.dram"; } static const TypeInfo sx1_machine_v2_type = { @@ -239,6 +247,8 @@ static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) mc->init = sx1_init_v1; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); + mc->default_ram_size = sdram_size; + mc->default_ram_id = "omap1.dram"; } static const TypeInfo sx1_machine_v1_type = { diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 72eca8cc55..99554bda19 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -31,6 +31,7 @@ #include "hw/loader.h" #include "exec/address-spaces.h" #include "cpu.h" +#include "qemu/cutils.h" static uint64_t static_read(void *opaque, hwaddr offset, unsigned size) { @@ -195,15 +196,21 @@ static void palmte_init(MachineState *machine) static uint32_t cs2val = 0x0000e1a0; static uint32_t cs3val = 0xe1a0e1a0; int rom_size, rom_loaded = 0; - MemoryRegion *dram = g_new(MemoryRegion, 1); + MachineClass *mc = MACHINE_GET_CLASS(machine); MemoryRegion *flash = g_new(MemoryRegion, 1); MemoryRegion *cs = g_new(MemoryRegion, 4); - memory_region_allocate_system_memory(dram, NULL, "omap1.dram", - palmte_binfo.ram_size); - memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, dram); + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + + memory_region_add_subregion(address_space_mem, OMAP_EMIFF_BASE, + machine->ram); - mpu = omap310_mpu_init(dram, machine->cpu_type); + mpu = omap310_mpu_init(machine->ram, machine->cpu_type); /* External Flash (EMIFS) */ memory_region_init_ram(flash, NULL, "palmte.flash", flash_size, @@ -265,6 +272,8 @@ static void palmte_machine_init(MachineClass *mc) mc->init = palmte_init; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t"); + mc->default_ram_size = 0x02000000; + mc->default_ram_id = "omap1.dram"; } DEFINE_MACHINE("cheetah", palmte_machine_init) diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 90ad9b8115..acd2bb794d 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -39,7 +39,6 @@ typedef struct RaspiMachineState { MachineState parent_obj; /*< public >*/ BCM283XState soc; - MemoryRegion ram; } RaspiMachineState; typedef struct RaspiMachineClass { @@ -277,16 +276,14 @@ static void raspi_machine_init(MachineState *machine) exit(1); } - /* Allocate and map RAM */ - memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram", - machine->ram_size); /* FIXME: Remove when we have custom CPU address space support */ - memory_region_add_subregion_overlap(get_system_memory(), 0, &s->ram, 0); + memory_region_add_subregion_overlap(get_system_memory(), 0, + machine->ram, 0); /* Setup the SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), board_soc_type(board_rev), &error_abort, NULL); - object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram), + object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(machine->ram), &error_abort); object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev", &error_abort); @@ -324,6 +321,7 @@ static void raspi_machine_class_init(ObjectClass *oc, void *data) mc->no_cdrom = 1; mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev); mc->default_ram_size = board_ram_size(board_rev); + mc->default_ram_id = "ram"; if (board_version(board_rev) == 2) { mc->ignore_memory_transaction_failures = true; } diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index 96cc455c5c..e31694bb92 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -19,11 +19,6 @@ #include "qemu/error-report.h" #include "sysemu/qtest.h" -typedef struct IMX6Sabrelite { - FslIMX6State soc; - MemoryRegion ram; -} IMX6Sabrelite; - static struct arm_boot_info sabrelite_binfo = { /* DDR memory start */ .loader_start = FSL_IMX6_MMDC_ADDR, @@ -45,7 +40,7 @@ static void sabrelite_reset_secondary(ARMCPU *cpu, static void sabrelite_init(MachineState *machine) { - IMX6Sabrelite *s = g_new0(IMX6Sabrelite, 1); + FslIMX6State *s; Error *err = NULL; /* Check the amount of memory is compatible with the SOC */ @@ -55,19 +50,16 @@ static void sabrelite_init(MachineState *machine) exit(1); } - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), - TYPE_FSL_IMX6, &error_abort, NULL); - - object_property_set_bool(OBJECT(&s->soc), true, "realized", &err); + s = FSL_IMX6(object_new(TYPE_FSL_IMX6)); + object_property_add_child(OBJECT(machine), "soc", OBJECT(s), &error_fatal); + object_property_set_bool(OBJECT(s), true, "realized", &err); if (err != NULL) { error_report("%s", error_get_pretty(err)); exit(1); } - memory_region_allocate_system_memory(&s->ram, NULL, "sabrelite.ram", - machine->ram_size); memory_region_add_subregion(get_system_memory(), FSL_IMX6_MMDC_ADDR, - &s->ram); + machine->ram); { /* @@ -78,7 +70,7 @@ static void sabrelite_init(MachineState *machine) /* Add the sst25vf016b NOR FLASH memory to first SPI */ Object *spi_dev; - spi_dev = object_resolve_path_component(OBJECT(&s->soc), "spi1"); + spi_dev = object_resolve_path_component(OBJECT(s), "spi1"); if (spi_dev) { SSIBus *spi_bus; @@ -109,7 +101,7 @@ static void sabrelite_init(MachineState *machine) sabrelite_binfo.secondary_cpu_reset_hook = sabrelite_reset_secondary; if (!qtest_enabled()) { - arm_load_kernel(&s->soc.cpu[0], machine, &sabrelite_binfo); + arm_load_kernel(&s->cpu[0], machine, &sabrelite_binfo); } } @@ -119,6 +111,7 @@ static void sabrelite_machine_init(MachineClass *mc) mc->init = sabrelite_init; mc->max_cpus = FSL_IMX6_NUM_CPUS; mc->ignore_memory_transaction_failures = true; + mc->default_ram_id = "sabrelite.ram"; } DEFINE_MACHINE("sabrelite", sabrelite_machine_init) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 9b5bcb5634..1cba9fc302 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -593,7 +593,6 @@ static void sbsa_ref_init(MachineState *machine) MachineClass *mc = MACHINE_GET_CLASS(machine); MemoryRegion *sysmem = get_system_memory(); MemoryRegion *secure_sysmem = g_new(MemoryRegion, 1); - MemoryRegion *ram = g_new(MemoryRegion, 1); bool firmware_loaded; const CPUArchIdList *possible_cpus; int n, sbsa_max_cpus; @@ -685,9 +684,8 @@ static void sbsa_ref_init(MachineState *machine) object_unref(cpuobj); } - memory_region_allocate_system_memory(ram, NULL, "sbsa-ref.ram", - machine->ram_size); - memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, ram); + memory_region_add_subregion(sysmem, sbsa_ref_memmap[SBSA_MEM].base, + machine->ram); create_fdt(sms); @@ -785,6 +783,7 @@ static void sbsa_ref_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_IDE; mc->no_cdrom = 1; mc->default_ram_size = 1 * GiB; + mc->default_ram_id = "sbsa-ref.ram"; mc->default_cpus = 4; mc->possible_cpu_arch_ids = sbsa_ref_possible_cpu_arch_ids; mc->cpu_index_to_instance_props = sbsa_ref_cpu_index_to_props; diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 23eb117041..0f2573f004 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -74,8 +74,7 @@ static int get_pte(dma_addr_t baseaddr, uint32_t index, uint64_t *pte, dma_addr_t addr = baseaddr + index * sizeof(*pte); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, addr, - (uint8_t *)pte, sizeof(*pte)); + ret = dma_memory_read(&address_space_memory, addr, pte, sizeof(*pte)); if (ret != MEMTX_OK) { info->type = SMMU_PTW_ERR_WALK_EABT; diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 8b5f157dc7..57a79df55b 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -279,8 +279,7 @@ static int smmu_get_ste(SMMUv3State *s, dma_addr_t addr, STE *buf, trace_smmuv3_get_ste(addr); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, addr, - (void *)buf, sizeof(*buf)); + ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Cannot fetch pte at address=0x%"PRIx64"\n", addr); @@ -301,8 +300,7 @@ static int smmu_get_cd(SMMUv3State *s, STE *ste, uint32_t ssid, trace_smmuv3_get_cd(addr); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, addr, - (void *)buf, sizeof(*buf)); + ret = dma_memory_read(&address_space_memory, addr, buf, sizeof(*buf)); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Cannot fetch pte at address=0x%"PRIx64"\n", addr); @@ -406,8 +404,8 @@ static int smmu_find_ste(SMMUv3State *s, uint32_t sid, STE *ste, l2_ste_offset = sid & ((1 << s->sid_split) - 1); l1ptr = (dma_addr_t)(strtab_base + l1_ste_offset * sizeof(l1std)); /* TODO: guarantee 64-bit single-copy atomicity */ - ret = dma_memory_read(&address_space_memory, l1ptr, - (uint8_t *)&l1std, sizeof(l1std)); + ret = dma_memory_read(&address_space_memory, l1ptr, &l1std, + sizeof(l1std)); if (ret != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "Could not read L1PTR at 0X%"PRIx64"\n", l1ptr); diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index e86af01537..f3c4a50b19 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -184,7 +184,6 @@ static void versatile_init(MachineState *machine, int board_id) Object *cpuobj; ARMCPU *cpu; MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); qemu_irq pic[32]; qemu_irq sic[32]; DeviceState *dev, *sysctl; @@ -220,11 +219,9 @@ static void versatile_init(MachineState *machine, int board_id) cpu = ARM_CPU(cpuobj); - memory_region_allocate_system_memory(ram, NULL, "versatile.ram", - machine->ram_size); /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero. */ - memory_region_add_subregion(sysmem, 0, ram); + memory_region_add_subregion(sysmem, 0, machine->ram); sysctl = qdev_create(NULL, "realview_sysctl"); qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004); @@ -398,6 +395,7 @@ static void versatilepb_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_SCSI; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); + mc->default_ram_id = "versatile.ram"; } static const TypeInfo versatilepb_type = { @@ -415,6 +413,7 @@ static void versatileab_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_SCSI; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926"); + mc->default_ram_id = "versatile.ram"; } static const TypeInfo versatileab_type = { diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 4673a88a8d..ed683eeea5 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -273,7 +273,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, { MachineState *machine = MACHINE(vms); MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *lowram = g_new(MemoryRegion, 1); ram_addr_t low_ram_size; @@ -283,8 +282,6 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, exit(1); } - memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", - ram_size); low_ram_size = ram_size; if (low_ram_size > 0x4000000) { low_ram_size = 0x4000000; @@ -293,9 +290,10 @@ static void a9_daughterboard_init(const VexpressMachineState *vms, * address space should in theory be remappable to various * things including ROM or RAM; we always map the RAM there. */ - memory_region_init_alias(lowram, NULL, "vexpress.lowmem", ram, 0, low_ram_size); + memory_region_init_alias(lowram, NULL, "vexpress.lowmem", machine->ram, + 0, low_ram_size); memory_region_add_subregion(sysmem, 0x0, lowram); - memory_region_add_subregion(sysmem, 0x60000000, ram); + memory_region_add_subregion(sysmem, 0x60000000, machine->ram); /* 0x1e000000 A9MPCore (SCU) private memory region */ init_cpus(machine, cpu_type, TYPE_A9MPCORE_PRIV, 0x1e000000, pic, @@ -360,7 +358,6 @@ static void a15_daughterboard_init(const VexpressMachineState *vms, { MachineState *machine = MACHINE(vms); MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); { @@ -375,10 +372,8 @@ static void a15_daughterboard_init(const VexpressMachineState *vms, } } - memory_region_allocate_system_memory(ram, NULL, "vexpress.highmem", - ram_size); /* RAM is from 0x80000000 upwards; there is no low-memory alias for it. */ - memory_region_add_subregion(sysmem, 0x80000000, ram); + memory_region_add_subregion(sysmem, 0x80000000, machine->ram); /* 0x2c000000 A15MPCore private memory region (GIC) */ init_cpus(machine, cpu_type, TYPE_A15MPCORE_PRIV, @@ -795,6 +790,7 @@ static void vexpress_class_init(ObjectClass *oc, void *data) mc->init = vexpress_common_init; mc->max_cpus = 4; mc->ignore_memory_transaction_failures = true; + mc->default_ram_id = "vexpress.highmem"; } static void vexpress_a9_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index cfe317922f..a8191a3e75 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1542,7 +1542,6 @@ static void machvirt_init(MachineState *machine) MemoryRegion *sysmem = get_system_memory(); MemoryRegion *secure_sysmem = NULL; int n, virt_max_cpus; - MemoryRegion *ram = g_new(MemoryRegion, 1); bool firmware_loaded; bool aarch64 = true; bool has_ged = !vmc->no_ged; @@ -1736,9 +1735,8 @@ static void machvirt_init(MachineState *machine) } } - memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", - machine->ram_size); - memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); + memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, + machine->ram); if (machine->device_memory) { memory_region_add_subregion(sysmem, machine->device_memory->base, &machine->device_memory->mr); @@ -2101,6 +2099,7 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) hc->unplug_request = virt_machine_device_unplug_request_cb; mc->numa_mem_supported = true; mc->auto_enable_numa_with_memhp = true; + mc->default_ram_id = "mach-virt.ram"; } static void virt_instance_init(Object *obj) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3a0fa5b23f..3d439a45d5 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -158,16 +158,20 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, static void zynq_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; ARMCPU *cpu; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *ext_ram = g_new(MemoryRegion, 1); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); DeviceState *dev; SysBusDevice *busdev; qemu_irq pic[64]; int n; + /* max 2GB ram */ + if (machine->ram_size > 2 * GiB) { + error_report("RAM size more than 2 GiB is not supported"); + exit(EXIT_FAILURE); + } + cpu = ARM_CPU(object_new(machine->cpu_type)); /* By default A9 CPUs have EL3 enabled. This board does not @@ -184,15 +188,8 @@ static void zynq_init(MachineState *machine) &error_fatal); object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); - /* max 2GB ram */ - if (ram_size > 0x80000000) { - ram_size = 0x80000000; - } - /* DDR remapped to address zero. */ - memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram", - ram_size); - memory_region_add_subregion(address_space_mem, 0, ext_ram); + memory_region_add_subregion(address_space_mem, 0, machine->ram); /* 256K of on-chip memory */ memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, @@ -300,7 +297,7 @@ static void zynq_init(MachineState *machine) sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); sysbus_mmio_map(busdev, 0, 0xF8007000); - zynq_binfo.ram_size = ram_size; + zynq_binfo.ram_size = machine->ram_size; zynq_binfo.nb_cpus = 1; zynq_binfo.board_id = 0xd32; zynq_binfo.loader_start = 0; @@ -318,6 +315,7 @@ static void zynq_machine_init(MachineClass *mc) mc->no_sdcard = 1; mc->ignore_memory_transaction_failures = true; mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9"); + mc->default_ram_id = "zynq.ext_ram"; } DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 0d2e3bdda1..e7f4ca8bf9 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -30,7 +30,6 @@ typedef struct VersalVirt { MachineState parent_obj; Versal soc; - MemoryRegion mr_ddr; void *fdt; int fdt_size; @@ -414,12 +413,9 @@ static void versal_virt_init(MachineState *machine) psci_conduit = QEMU_PSCI_CONDUIT_SMC; } - memory_region_allocate_system_memory(&s->mr_ddr, NULL, "ddr", - machine->ram_size); - sysbus_init_child_obj(OBJECT(machine), "xlnx-ve", &s->soc, sizeof(s->soc), TYPE_XLNX_VERSAL); - object_property_set_link(OBJECT(&s->soc), OBJECT(&s->mr_ddr), + object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram), "ddr", &error_abort); object_property_set_int(OBJECT(&s->soc), psci_conduit, "psci-conduit", &error_abort); @@ -473,6 +469,7 @@ static void versal_virt_machine_class_init(ObjectClass *oc, void *data) mc->max_cpus = XLNX_VERSAL_NR_ACPUS; mc->default_cpus = XLNX_VERSAL_NR_ACPUS; mc->no_cdrom = true; + mc->default_ram_id = "ddr"; } static const TypeInfo versal_virt_machine_init_typeinfo = { diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 53cfe7c1f1..bd645ad818 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -28,7 +28,6 @@ typedef struct XlnxZCU102 { MachineState parent_obj; XlnxZynqMPState soc; - MemoryRegion ddr_ram; bool secure; bool virt; @@ -87,13 +86,10 @@ static void xlnx_zcu102_init(MachineState *machine) ram_size); } - memory_region_allocate_system_memory(&s->ddr_ram, NULL, "ddr-ram", - ram_size); - object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), TYPE_XLNX_ZYNQMP, &error_abort, NULL); - object_property_set_link(OBJECT(&s->soc), OBJECT(&s->ddr_ram), + object_property_set_link(OBJECT(&s->soc), OBJECT(machine->ram), "ddr-ram", &error_abort); object_property_set_bool(OBJECT(&s->soc), s->secure, "secure", &error_fatal); @@ -211,6 +207,7 @@ static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) mc->ignore_memory_transaction_failures = true; mc->max_cpus = XLNX_ZYNQMP_NUM_APU_CPUS + XLNX_ZYNQMP_NUM_RPU_CPUS; mc->default_cpus = XLNX_ZYNQMP_NUM_APU_CPUS; + mc->default_ram_id = "ddr-ram"; } static const TypeInfo xlnx_zcu102_machine_init_typeinfo = { diff --git a/hw/core/machine.c b/hw/core/machine.c index ce403ccea9..9e8c06036f 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -26,6 +26,7 @@ #include "sysemu/qtest.h" #include "hw/pci/pci.h" #include "hw/mem/nvdimm.h" +#include "migration/vmstate.h" GlobalProperty hw_compat_4_2[] = { { "virtio-blk-device", "queue-size", "128"}, @@ -510,6 +511,22 @@ static void validate_sysbus_device(SysBusDevice *sbdev, void *opaque) } } +static char *machine_get_memdev(Object *obj, Error **errp) +{ + MachineState *ms = MACHINE(obj); + + return g_strdup(ms->ram_memdev_id); +} + +static void machine_set_memdev(Object *obj, const char *value, Error **errp) +{ + MachineState *ms = MACHINE(obj); + + g_free(ms->ram_memdev_id); + ms->ram_memdev_id = g_strdup(value); +} + + static void machine_init_notify(Notifier *notifier, void *data) { MachineState *machine = MACHINE(qdev_get_machine()); @@ -891,6 +908,14 @@ static void machine_initfn(Object *obj) "Table (HMAT)", NULL); } + object_property_add_str(obj, "memory-backend", + machine_get_memdev, machine_set_memdev, + &error_abort); + object_property_set_description(obj, "memory-backend", + "Set RAM backend" + "Valid value is ID of hostmem based backend", + &error_abort); + /* Register notifier when init is done for sysbus sanity checks */ ms->sysbus_notifier.notify = machine_init_notify; qemu_add_machine_init_done_notifier(&ms->sysbus_notifier); @@ -1037,10 +1062,33 @@ static void machine_numa_finish_cpu_init(MachineState *machine) g_string_free(s, true); } +MemoryRegion *machine_consume_memdev(MachineState *machine, + HostMemoryBackend *backend) +{ + MemoryRegion *ret = host_memory_backend_get_memory(backend); + + if (memory_region_is_mapped(ret)) { + char *path = object_get_canonical_path_component(OBJECT(backend)); + error_report("memory backend %s can't be used multiple times.", path); + g_free(path); + exit(EXIT_FAILURE); + } + host_memory_backend_set_mapped(backend, true); + vmstate_register_ram_global(ret); + return ret; +} + void machine_run_board_init(MachineState *machine) { MachineClass *machine_class = MACHINE_GET_CLASS(machine); + if (machine->ram_memdev_id) { + Object *o; + o = object_resolve_path_type(machine->ram_memdev_id, + TYPE_MEMORY_BACKEND, NULL); + machine->ram = machine_consume_memdev(machine, MEMORY_BACKEND(o)); + } + if (machine->numa_state) { numa_complete_configuration(machine); if (machine->numa_state->num_nodes) { diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 1aa0a9a01a..cb47d9d4f8 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -32,11 +32,8 @@ static void machine_none_init(MachineState *mch) } /* RAM at address zero */ - if (mch->ram_size) { - MemoryRegion *ram = g_new(MemoryRegion, 1); - - memory_region_allocate_system_memory(ram, NULL, "ram", mch->ram_size); - memory_region_add_subregion(get_system_memory(), 0, ram); + if (mch->ram) { + memory_region_add_subregion(get_system_memory(), 0, mch->ram); } if (mch->kernel_filename) { @@ -52,6 +49,7 @@ static void machine_none_machine_init(MachineClass *mc) mc->init = machine_none_init; mc->max_cpus = 1; mc->default_ram_size = 0; + mc->default_ram_id = "ram"; } DEFINE_MACHINE("none", machine_none_machine_init) diff --git a/hw/core/numa.c b/hw/core/numa.c index 0d1b4be76a..316bc50d75 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -52,6 +52,11 @@ QemuOptsList qemu_numa_opts = { }; static int have_memdevs; +bool numa_uses_legacy_mem(void) +{ + return !have_memdevs; +} + static int have_mem; static int max_numa_nodeid; /* Highest specified NUMA node ID, plus one. * For all nodes, nodeid < max_numa_nodeid @@ -652,6 +657,23 @@ void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes, nodes[i].node_mem = size - usedmem; } +static void numa_init_memdev_container(MachineState *ms, MemoryRegion *ram) +{ + int i; + uint64_t addr = 0; + + for (i = 0; i < ms->numa_state->num_nodes; i++) { + uint64_t size = ms->numa_state->nodes[i].node_mem; + HostMemoryBackend *backend = ms->numa_state->nodes[i].node_memdev; + if (!backend) { + continue; + } + MemoryRegion *seg = machine_consume_memdev(ms, backend); + memory_region_add_subregion(ram, addr, seg); + addr += size; + } +} + void numa_complete_configuration(MachineState *ms) { int i; @@ -734,6 +756,12 @@ void numa_complete_configuration(MachineState *ms) exit(1); } + if (!numa_uses_legacy_mem() && mc->default_ram_id) { + ms->ram = g_new(MemoryRegion, 1); + memory_region_init(ms->ram, OBJECT(ms), mc->default_ram_id, + ram_size); + numa_init_memdev_container(ms, ms->ram); + } /* QEMU needs at least all unique node pair distances to build * the whole NUMA distance table. QEMU treats the distance table * as symmetric by default, i.e. distance A->B == distance B->A. @@ -778,79 +806,6 @@ void numa_cpu_pre_plug(const CPUArchId *slot, DeviceState *dev, Error **errp) } } -static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner, - const char *name, - uint64_t ram_size) -{ - if (mem_path) { -#ifdef __linux__ - Error *err = NULL; - memory_region_init_ram_from_file(mr, owner, name, ram_size, 0, 0, - mem_path, &err); - if (err) { - error_report_err(err); - if (mem_prealloc) { - exit(1); - } - warn_report("falling back to regular RAM allocation"); - error_printf("This is deprecated. Make sure that -mem-path " - " specified path has sufficient resources to allocate" - " -m specified RAM amount\n"); - /* Legacy behavior: if allocation failed, fall back to - * regular RAM allocation. - */ - mem_path = NULL; - memory_region_init_ram_nomigrate(mr, owner, name, ram_size, &error_fatal); - } -#else - fprintf(stderr, "-mem-path not supported on this host\n"); - exit(1); -#endif - } else { - memory_region_init_ram_nomigrate(mr, owner, name, ram_size, &error_fatal); - } - vmstate_register_ram_global(mr); -} - -void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, - const char *name, - uint64_t ram_size) -{ - uint64_t addr = 0; - int i; - MachineState *ms = MACHINE(qdev_get_machine()); - - if (ms->numa_state == NULL || - ms->numa_state->num_nodes == 0 || !have_memdevs) { - allocate_system_memory_nonnuma(mr, owner, name, ram_size); - return; - } - - memory_region_init(mr, owner, name, ram_size); - for (i = 0; i < ms->numa_state->num_nodes; i++) { - uint64_t size = ms->numa_state->nodes[i].node_mem; - HostMemoryBackend *backend = ms->numa_state->nodes[i].node_memdev; - if (!backend) { - continue; - } - MemoryRegion *seg = host_memory_backend_get_memory(backend); - - if (memory_region_is_mapped(seg)) { - char *path = object_get_canonical_path_component(OBJECT(backend)); - error_report("memory backend %s is used multiple times. Each " - "-numa option must use a different memdev value.", - path); - g_free(path); - exit(1); - } - - host_memory_backend_set_mapped(backend, true); - memory_region_add_subregion(mr, addr, seg); - vmstate_register_ram_global(seg); - addr += size; - } -} - static void numa_stat_memory_devices(NumaNodeMem node_mem[]) { MemoryDeviceInfoList *info_list = qmp_memory_device_list(); diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index be7760476a..cf6790fd6f 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -249,7 +249,6 @@ static struct cris_load_info li; static void axisdev88_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; CRISCPU *cpu; @@ -261,16 +260,12 @@ void axisdev88_init(MachineState *machine) struct etraxfs_dma_client *dma_eth; int i; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); MemoryRegion *phys_intmem = g_new(MemoryRegion, 1); /* init CPUs */ cpu = CRIS_CPU(cpu_create(machine->cpu_type)); - /* allocate RAM */ - memory_region_allocate_system_memory(phys_ram, NULL, "axisdev88.ram", - ram_size); - memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram); + memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram); /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the internal memory. */ @@ -351,6 +346,7 @@ static void axisdev88_machine_init(MachineClass *mc) mc->init = axisdev88_init; mc->is_default = 1; mc->default_cpu_type = CRIS_CPU_TYPE_NAME("crisv32"); + mc->default_ram_id = "axisdev88.ram"; } DEFINE_MACHINE("axis-dev88", axisdev88_machine_init) diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c index c1071ecd46..ec6776680e 100644 --- a/hw/display/exynos4210_fimd.c +++ b/hw/display/exynos4210_fimd.c @@ -1164,7 +1164,8 @@ static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win) goto error_return; } - w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, 0); + w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len, + false); if (!w->host_fb_addr) { DPRINT_ERROR("Failed to map window %u framebuffer\n", win); goto error_return; diff --git a/hw/display/milkymist-tmu2.c b/hw/display/milkymist-tmu2.c index 199f1227e7..513c0d5bab 100644 --- a/hw/display/milkymist-tmu2.c +++ b/hw/display/milkymist-tmu2.c @@ -218,7 +218,7 @@ static void tmu2_start(MilkymistTMU2State *s) glGenTextures(1, &texture); glBindTexture(GL_TEXTURE_2D, texture); fb_len = 2ULL * s->regs[R_TEXHRES] * s->regs[R_TEXVRES]; - fb = cpu_physical_memory_map(s->regs[R_TEXFBUF], &fb_len, 0); + fb = cpu_physical_memory_map(s->regs[R_TEXFBUF], &fb_len, false); if (fb == NULL) { glDeleteTextures(1, &texture); glXMakeContextCurrent(s->dpy, None, None, NULL); @@ -262,7 +262,7 @@ static void tmu2_start(MilkymistTMU2State *s) /* Read the QEMU dest. framebuffer into the OpenGL framebuffer */ fb_len = 2ULL * s->regs[R_DSTHRES] * s->regs[R_DSTVRES]; - fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, 0); + fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, false); if (fb == NULL) { glDeleteTextures(1, &texture); glXMakeContextCurrent(s->dpy, None, None, NULL); @@ -281,7 +281,7 @@ static void tmu2_start(MilkymistTMU2State *s) /* Map the texture */ mesh_len = MESH_MAXSIZE*MESH_MAXSIZE*sizeof(struct vertex); - mesh = cpu_physical_memory_map(s->regs[R_VERTICESADDR], &mesh_len, 0); + mesh = cpu_physical_memory_map(s->regs[R_VERTICESADDR], &mesh_len, false); if (mesh == NULL) { glDeleteTextures(1, &texture); glXMakeContextCurrent(s->dpy, None, None, NULL); @@ -298,7 +298,7 @@ static void tmu2_start(MilkymistTMU2State *s) /* Write back the OpenGL framebuffer to the QEMU framebuffer */ fb_len = 2ULL * s->regs[R_DSTHRES] * s->regs[R_DSTVRES]; - fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, 1); + fb = cpu_physical_memory_map(s->regs[R_DSTFBUF], &fb_len, true); if (fb == NULL) { glDeleteTextures(1, &texture); glXMakeContextCurrent(s->dpy, None, None, NULL); diff --git a/hw/display/omap_dss.c b/hw/display/omap_dss.c index 637aae8d39..32dc0d6aa7 100644 --- a/hw/display/omap_dss.c +++ b/hw/display/omap_dss.c @@ -632,7 +632,7 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s) len = s->rfbi.pixels * 2; data_addr = s->dispc.l[0].addr[0]; - data = cpu_physical_memory_map(data_addr, &len, 0); + data = cpu_physical_memory_map(data_addr, &len, false); if (data && len != s->rfbi.pixels * 2) { cpu_physical_memory_unmap(data, len, 0, 0); data = NULL; diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index 6ad13f2e9e..fa4a381db6 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -91,9 +91,9 @@ static void omap_update_display(void *opaque) frame_offset = 0; if (omap_lcd->plm != 2) { - cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[ - omap_lcd->dma->current_frame], - (void *)omap_lcd->palette, 0x200); + cpu_physical_memory_read( + omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_frame], + omap_lcd->palette, 0x200); switch (omap_lcd->palette[0] >> 12 & 7) { case 3 ... 7: frame_offset += 0x200; @@ -244,8 +244,8 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s) { if (s->plm != 2 && !s->palette_done) { cpu_physical_memory_read( - s->dma->phys_framebuffer[s->dma->current_frame], - (void *)s->palette, 0x200); + s->dma->phys_framebuffer[s->dma->current_frame], + s->palette, 0x200); s->palette_done = 1; omap_lcd_interrupts(s); } diff --git a/hw/display/ramfb.c b/hw/display/ramfb.c index cd94940223..7ba07c80f6 100644 --- a/hw/display/ramfb.c +++ b/hw/display/ramfb.c @@ -57,7 +57,7 @@ static DisplaySurface *ramfb_create_display_surface(int width, int height, } size = (hwaddr)linesize * height; - data = cpu_physical_memory_map(addr, &size, 0); + data = cpu_physical_memory_map(addr, &size, false); if (size != (hwaddr)linesize * height) { cpu_physical_memory_unmap(data, size, 0, 0); return NULL; diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index 47e1c6df12..c4334e87bf 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -225,9 +225,8 @@ static void channel_load_g(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP); /* Load and decode. FIXME: handle endianness. */ - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_g, - sizeof ctrl->channels[c].current_g); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_g, + sizeof(ctrl->channels[c].current_g)); } static void dump_c(int ch, struct dma_descr_context *c) @@ -257,9 +256,8 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Load and decode. FIXME: handle endianness. */ - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_c, - sizeof ctrl->channels[c].current_c); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_c, + sizeof(ctrl->channels[c].current_c)); D(dump_c(c, &ctrl->channels[c].current_c)); /* I guess this should update the current pos. */ @@ -275,9 +273,8 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) /* Load and decode. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_d, - sizeof ctrl->channels[c].current_d); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_d, + sizeof(ctrl->channels[c].current_d)); D(dump_d(c, &ctrl->channels[c].current_d)); ctrl->channels[c].regs[RW_DATA] = addr; @@ -290,9 +287,8 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); D(dump_d(c, &ctrl->channels[c].current_d)); - cpu_physical_memory_write (addr, - (void *) &ctrl->channels[c].current_c, - sizeof ctrl->channels[c].current_c); + cpu_physical_memory_write(addr, &ctrl->channels[c].current_c, + sizeof(ctrl->channels[c].current_c)); } static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) @@ -301,9 +297,8 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); - cpu_physical_memory_write (addr, - (void *) &ctrl->channels[c].current_d, - sizeof ctrl->channels[c].current_d); + cpu_physical_memory_write(addr, &ctrl->channels[c].current_d, + sizeof(ctrl->channels[c].current_d)); } static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) diff --git a/hw/dma/rc4030.c b/hw/dma/rc4030.c index c4cf8236f4..21e2c360ac 100644 --- a/hw/dma/rc4030.c +++ b/hw/dma/rc4030.c @@ -513,8 +513,8 @@ static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr, if (i < s->dma_tl_limit / sizeof(entry)) { entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry); if (address_space_read(ret.target_as, entry_address, - MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry, - sizeof(entry)) == MEMTX_OK) { + MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry)) + == MEMTX_OK) { ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1); ret.perm = IOMMU_RW; } @@ -590,7 +590,7 @@ static const VMStateDescription vmstate_rc4030 = { }; static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, - int len, int is_write) + int len, bool is_write) { rc4030State *s = opaque; hwaddr dma_addr; @@ -630,13 +630,13 @@ struct rc4030DMAState { void rc4030_dma_read(void *dma, uint8_t *buf, int len) { rc4030_dma s = dma; - rc4030_do_dma(s->opaque, s->n, buf, len, 0); + rc4030_do_dma(s->opaque, s->n, buf, len, false); } void rc4030_dma_write(void *dma, uint8_t *buf, int len) { rc4030_dma s = dma; - rc4030_do_dma(s->opaque, s->n, buf, len, 1); + rc4030_do_dma(s->opaque, s->n, buf, len, true); } static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c index 8fb83f5b07..1c1b142293 100644 --- a/hw/dma/xlnx-zdma.c +++ b/hw/dma/xlnx-zdma.c @@ -311,8 +311,7 @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf) return false; } - address_space_rw(s->dma_as, addr, s->attr, - buf, sizeof(XlnxZDMADescr), false); + address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr)); return true; } @@ -364,7 +363,7 @@ static uint64_t zdma_update_descr_addr(XlnxZDMA *s, bool type, } else { addr = zdma_get_regaddr64(s, basereg); addr += sizeof(s->dsc_dst); - address_space_rw(s->dma_as, addr, s->attr, (void *) &next, 8, false); + address_space_read(s->dma_as, addr, s->attr, &next, 8); zdma_put_regaddr64(s, basereg, next); } return next; @@ -416,8 +415,7 @@ static void zdma_write_dst(XlnxZDMA *s, uint8_t *buf, uint32_t len) } } - address_space_rw(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen, - true); + address_space_write(s->dma_as, s->dsc_dst.addr, s->attr, buf, dlen); if (burst_type == AXI_BURST_INCR) { s->dsc_dst.addr += dlen; } @@ -493,8 +491,7 @@ static void zdma_process_descr(XlnxZDMA *s) len = s->cfg.bus_width / 8; } } else { - address_space_rw(s->dma_as, src_addr, s->attr, s->buf, len, - false); + address_space_read(s->dma_as, src_addr, s->attr, s->buf, len); if (burst_type == AXI_BURST_INCR) { src_addr += len; } diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index d8755ec422..67181e75ba 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -71,14 +71,11 @@ static void machine_hppa_init(MachineState *machine) uint64_t kernel_entry = 0, kernel_low, kernel_high; MemoryRegion *addr_space = get_system_memory(); MemoryRegion *rom_region; - MemoryRegion *ram_region; MemoryRegion *cpu_region; long i; unsigned int smp_cpus = machine->smp.cpus; SysBusDevice *s; - ram_size = machine->ram_size; - /* Create CPUs. */ for (i = 0; i < smp_cpus; i++) { char *name = g_strdup_printf("cpu%ld-io-eir", i); @@ -97,10 +94,8 @@ static void machine_hppa_init(MachineState *machine) error_report("RAM size is currently restricted to 3GB"); exit(EXIT_FAILURE); } - ram_region = g_new(MemoryRegion, 1); - memory_region_allocate_system_memory(ram_region, OBJECT(machine), - "ram", ram_size); - memory_region_add_subregion_overlap(addr_space, 0, ram_region, -1); + memory_region_add_subregion_overlap(addr_space, 0, machine->ram, -1); + /* Init Lasi chip */ lasi_init(addr_space); @@ -298,6 +293,7 @@ static void machine_hppa_machine_init(MachineClass *mc) mc->is_default = 1; mc->default_ram_size = 512 * MiB; mc->default_boot_order = "cd"; + mc->default_ram_id = "ram"; } DEFINE_MACHINE("hppa", machine_hppa_machine_init) diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index d23485108d..38d8e51703 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -167,7 +167,7 @@ static void microvm_memory_init(MicrovmMachineState *mms) { MachineState *machine = MACHINE(mms); X86MachineState *x86ms = X86_MACHINE(mms); - MemoryRegion *ram, *ram_below_4g, *ram_above_4g; + MemoryRegion *ram_below_4g, *ram_above_4g; MemoryRegion *system_memory = get_system_memory(); FWCfgState *fw_cfg; ram_addr_t lowmem; @@ -214,12 +214,8 @@ static void microvm_memory_init(MicrovmMachineState *mms) x86ms->below_4g_mem_size = machine->ram_size; } - ram = g_malloc(sizeof(*ram)); - memory_region_allocate_system_memory(ram, NULL, "microvm.ram", - machine->ram_size); - ram_below_4g = g_malloc(sizeof(*ram_below_4g)); - memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, + memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 0, x86ms->below_4g_mem_size); memory_region_add_subregion(system_memory, 0, ram_below_4g); @@ -227,7 +223,8 @@ static void microvm_memory_init(MicrovmMachineState *mms) if (x86ms->above_4g_mem_size > 0) { ram_above_4g = g_malloc(sizeof(*ram_above_4g)); - memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, + memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", + machine->ram, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size); memory_region_add_subregion(system_memory, 0x100000000ULL, @@ -502,6 +499,7 @@ static void microvm_class_init(ObjectClass *oc, void *data) mc->auto_enable_numa_with_memhp = false; mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported = false; + mc->default_ram_id = "microvm.ram"; /* Avoid relying too much on kernel components */ mc->default_kernel_irqchip_split = true; diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2ddce4230a..6ab4acb0c6 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -937,7 +937,7 @@ void pc_memory_init(PCMachineState *pcms, MemoryRegion **ram_memory) { int linux_boot, i; - MemoryRegion *ram, *option_rom_mr; + MemoryRegion *option_rom_mr; MemoryRegion *ram_below_4g, *ram_above_4g; FWCfgState *fw_cfg; MachineState *machine = MACHINE(pcms); @@ -950,22 +950,20 @@ void pc_memory_init(PCMachineState *pcms, linux_boot = (machine->kernel_filename != NULL); - /* Allocate RAM. We allocate it as a single memory region and use - * aliases to address portions of it, mostly for backwards compatibility - * with older qemus that used qemu_ram_alloc(). + /* + * Split single memory region and use aliases to address portions of it, + * done for backwards compatibility with older qemus. */ - ram = g_malloc(sizeof(*ram)); - memory_region_allocate_system_memory(ram, NULL, "pc.ram", - machine->ram_size); - *ram_memory = ram; + *ram_memory = machine->ram; ram_below_4g = g_malloc(sizeof(*ram_below_4g)); - memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", ram, + memory_region_init_alias(ram_below_4g, NULL, "ram-below-4g", machine->ram, 0, x86ms->below_4g_mem_size); memory_region_add_subregion(system_memory, 0, ram_below_4g); e820_add_entry(0, x86ms->below_4g_mem_size, E820_RAM); if (x86ms->above_4g_mem_size > 0) { ram_above_4g = g_malloc(sizeof(*ram_above_4g)); - memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", ram, + memory_region_init_alias(ram_above_4g, NULL, "ram-above-4g", + machine->ram, x86ms->below_4g_mem_size, x86ms->above_4g_mem_size); memory_region_add_subregion(system_memory, 0x100000000ULL, @@ -1952,6 +1950,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported = true; mc->numa_mem_supported = true; + mc->default_ram_id = "pc.ram"; object_class_property_add(oc, PC_MACHINE_DEVMEM_REGION_SIZE, "int", pc_machine_get_device_memory_region_size, NULL, diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 68264a22e8..13d91e109a 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1461,7 +1461,7 @@ static void ahci_commit_buf(IDEDMA *dma, uint32_t tx_bytes) ad->cur_cmd->status = cpu_to_le32(tx_bytes); } -static int ahci_dma_rw_buf(IDEDMA *dma, int is_write) +static int ahci_dma_rw_buf(IDEDMA *dma, bool is_write) { AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); IDEState *s = &ad->port.ifs[0]; diff --git a/hw/ide/core.c b/hw/ide/core.c index 80000eb766..689bb36409 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -2570,7 +2570,7 @@ static void ide_init1(IDEBus *bus, int unit) ide_sector_write_timer_cb, s); } -static int ide_nop_int(IDEDMA *dma, int x) +static int ide_nop_int(IDEDMA *dma, bool is_write) { return 0; } diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 7a8470e921..a9f25e5d02 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -376,7 +376,7 @@ static void macio_ide_reset(DeviceState *dev) ide_bus_reset(&d->bus); } -static int ide_nop_int(IDEDMA *dma, int x) +static int ide_nop_int(IDEDMA *dma, bool is_write) { return 0; } diff --git a/hw/ide/pci.c b/hw/ide/pci.c index cce1da804d..1a6a287e76 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -181,7 +181,7 @@ static int32_t bmdma_prepare_buf(IDEDMA *dma, int32_t limit) } /* return 0 if buffer completed */ -static int bmdma_rw_buf(IDEDMA *dma, int is_write) +static int bmdma_rw_buf(IDEDMA *dma, bool is_write) { BMDMAState *bm = DO_UPCAST(BMDMAState, dma, dma); IDEState *s = bmdma_active_if(bm); diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c index d1894adab8..4e0a98c117 100644 --- a/hw/lm32/lm32_boards.c +++ b/hw/lm32/lm32_boards.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/cutils.h" #include "qemu/error-report.h" #include "cpu.h" #include "hw/sysbus.h" @@ -75,22 +76,28 @@ static void main_cpu_reset(void *opaque) static void lm32_evr_init(MachineState *machine) { + MachineClass *mc = MACHINE_GET_CLASS(machine); const char *kernel_filename = machine->kernel_filename; LM32CPU *cpu; CPULM32State *env; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32]; ResetInfo *reset_info; int i; + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + /* memory map */ hwaddr flash_base = 0x04000000; size_t flash_sector_size = 256 * KiB; size_t flash_size = 32 * MiB; hwaddr ram_base = 0x08000000; - size_t ram_size = 64 * MiB; hwaddr timer0_base = 0x80002000; hwaddr uart0_base = 0x80006000; hwaddr timer1_base = 0x8000a000; @@ -107,9 +114,7 @@ static void lm32_evr_init(MachineState *machine) reset_info->flash_base = flash_base; - memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram", - ram_size); - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); + memory_region_add_subregion(address_space_mem, ram_base, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); /* Spansion S29NS128P */ @@ -144,7 +149,7 @@ static void lm32_evr_init(MachineState *machine) if (kernel_size < 0) { kernel_size = load_image_targphys(kernel_filename, ram_base, - ram_size); + machine->ram_size); reset_info->bootstrap_pc = ram_base; } @@ -159,6 +164,7 @@ static void lm32_evr_init(MachineState *machine) static void lm32_uclinux_init(MachineState *machine) { + MachineClass *mc = MACHINE_GET_CLASS(machine); const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -166,18 +172,23 @@ static void lm32_uclinux_init(MachineState *machine) CPULM32State *env; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32]; HWSetup *hw; ResetInfo *reset_info; int i; + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + /* memory map */ hwaddr flash_base = 0x04000000; size_t flash_sector_size = 256 * KiB; size_t flash_size = 32 * MiB; hwaddr ram_base = 0x08000000; - size_t ram_size = 64 * MiB; hwaddr uart0_base = 0x80000000; hwaddr timer0_base = 0x80002000; hwaddr timer1_base = 0x80010000; @@ -200,9 +211,7 @@ static void lm32_uclinux_init(MachineState *machine) reset_info->flash_base = flash_base; - memory_region_allocate_system_memory(phys_ram, NULL, - "lm32_uclinux.sdram", ram_size); - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); + memory_region_add_subregion(address_space_mem, ram_base, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); /* Spansion S29NS128P */ @@ -238,7 +247,7 @@ static void lm32_uclinux_init(MachineState *machine) if (kernel_size < 0) { kernel_size = load_image_targphys(kernel_filename, ram_base, - ram_size); + machine->ram_size); reset_info->bootstrap_pc = ram_base; } @@ -252,7 +261,7 @@ static void lm32_uclinux_init(MachineState *machine) hw = hwsetup_init(); hwsetup_add_cpu(hw, "LM32", 75000000); hwsetup_add_flash(hw, "flash", flash_base, flash_size); - hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size); + hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, machine->ram_size); hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq); hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq); hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq); @@ -288,6 +297,8 @@ static void lm32_evr_class_init(ObjectClass *oc, void *data) mc->init = lm32_evr_init; mc->is_default = 1; mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); + mc->default_ram_size = 64 * MiB; + mc->default_ram_id = "lm32_evr.sdram"; } static const TypeInfo lm32_evr_type = { @@ -304,6 +315,8 @@ static void lm32_uclinux_class_init(ObjectClass *oc, void *data) mc->init = lm32_uclinux_init; mc->is_default = 0; mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); + mc->default_ram_size = 64 * MiB; + mc->default_ram_id = "lm32_uclinux.sdram"; } static const TypeInfo lm32_uclinux_type = { diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c index 6d46134232..5c72266e58 100644 --- a/hw/lm32/milkymist.c +++ b/hw/lm32/milkymist.c @@ -36,6 +36,7 @@ #include "hw/display/milkymist_tmu2.h" #include "lm32.h" #include "exec/address-spaces.h" +#include "qemu/cutils.h" #define BIOS_FILENAME "mmone-bios.bin" #define BIOS_OFFSET 0x00860000 @@ -82,6 +83,7 @@ static void main_cpu_reset(void *opaque) static void milkymist_init(MachineState *machine) { + MachineClass *mc = MACHINE_GET_CLASS(machine); const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -90,22 +92,27 @@ milkymist_init(MachineState *machine) int kernel_size; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *phys_sdram = g_new(MemoryRegion, 1); qemu_irq irq[32]; int i; char *bios_filename; ResetInfo *reset_info; + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + /* memory map */ hwaddr flash_base = 0x00000000; size_t flash_sector_size = 128 * KiB; size_t flash_size = 32 * MiB; hwaddr sdram_base = 0x40000000; - size_t sdram_size = 128 * MiB; hwaddr initrd_base = sdram_base + 0x1002000; hwaddr cmdline_base = sdram_base + 0x1000000; - size_t initrd_max = sdram_size - 0x1002000; + size_t initrd_max = machine->ram_size - 0x1002000; reset_info = g_malloc0(sizeof(ResetInfo)); @@ -116,9 +123,7 @@ milkymist_init(MachineState *machine) cpu_lm32_set_phys_msb_ignore(env, 1); - memory_region_allocate_system_memory(phys_sdram, NULL, "milkymist.sdram", - sdram_size); - memory_region_add_subregion(address_space_mem, sdram_base, phys_sdram); + memory_region_add_subregion(address_space_mem, sdram_base, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); /* Numonyx JS28F256J3F105 */ @@ -183,7 +188,7 @@ milkymist_init(MachineState *machine) if (kernel_size < 0) { kernel_size = load_image_targphys(kernel_filename, sdram_base, - sdram_size); + machine->ram_size); reset_info->bootstrap_pc = sdram_base; } @@ -216,6 +221,8 @@ static void milkymist_machine_init(MachineClass *mc) mc->init = milkymist_init; mc->is_default = 0; mc->default_cpu_type = LM32_CPU_TYPE_NAME("lm32-full"); + mc->default_ram_size = 128 * MiB; + mc->default_ram_id = "milkymist.sdram"; } DEFINE_MACHINE("milkymist", milkymist_machine_init) diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c index bed43a936d..846f4e40c6 100644 --- a/hw/m68k/an5206.c +++ b/hw/m68k/an5206.c @@ -33,7 +33,6 @@ static void an5206_init(MachineState *machine) uint64_t elf_entry; hwaddr entry; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); cpu = M68K_CPU(cpu_create(machine->cpu_type)); @@ -46,8 +45,7 @@ static void an5206_init(MachineState *machine) env->rambar0 = AN5206_RAMBAR_ADDR | 1; /* DRAM at address zero */ - memory_region_allocate_system_memory(ram, NULL, "an5206.ram", ram_size); - memory_region_add_subregion(address_space_mem, 0, ram); + memory_region_add_subregion(address_space_mem, 0, machine->ram); /* Internal SRAM. */ memory_region_init_ram(sram, NULL, "an5206.sram", 512, &error_fatal); @@ -89,6 +87,7 @@ static void an5206_machine_init(MachineClass *mc) mc->desc = "Arnewsh 5206"; mc->init = an5206_init; mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5206"); + mc->default_ram_id = "an5206.ram"; } DEFINE_MACHINE("an5206", an5206_machine_init) diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index a999c21982..31622c71cb 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -234,7 +234,6 @@ static void mcf5208evb_init(MachineState *machine) qemu_irq *pic; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *rom = g_new(MemoryRegion, 1); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); cpu = M68K_CPU(cpu_create(machine->cpu_type)); @@ -249,8 +248,7 @@ static void mcf5208evb_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0x00000000, rom); /* DRAM at 0x40000000 */ - memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size); - memory_region_add_subregion(address_space_mem, 0x40000000, ram); + memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram); /* Internal SRAM. */ memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal); @@ -354,6 +352,7 @@ static void mcf5208evb_machine_init(MachineClass *mc) mc->init = mcf5208evb_init; mc->is_default = 1; mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); + mc->default_ram_id = "mcf5208.ram"; } DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init) diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 350c6fec78..14b99ed25d 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -860,7 +860,6 @@ static void next_cube_init(MachineState *machine) { M68kCPU *cpu; CPUM68KState *env; - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *rom = g_new(MemoryRegion, 1); MemoryRegion *mmiomem = g_new(MemoryRegion, 1); MemoryRegion *scrmem = g_new(MemoryRegion, 1); @@ -893,8 +892,7 @@ static void next_cube_init(MachineState *machine) memcpy(ns->rtc.ram, rtc_ram2, 32); /* 64MB RAM starting at 0x04000000 */ - memory_region_allocate_system_memory(ram, NULL, "next.ram", ram_size); - memory_region_add_subregion(sysmem, 0x04000000, ram); + memory_region_add_subregion(sysmem, 0x04000000, machine->ram); /* Framebuffer */ dev = qdev_create(NULL, TYPE_NEXTFB); @@ -967,6 +965,7 @@ static void next_machine_class_init(ObjectClass *oc, void *data) mc->desc = "NeXT Cube"; mc->init = next_cube_init; mc->default_ram_size = RAM_SIZE; + mc->default_ram_id = "next.ram"; mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); } diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 1e32363688..a4c4bc14cb 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -160,7 +160,6 @@ static void q800_init(MachineState *machine) ram_addr_t initrd_base; int32_t initrd_size; MemoryRegion *rom; - MemoryRegion *ram; MemoryRegion *io; const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1; int i; @@ -194,9 +193,7 @@ static void q800_init(MachineState *machine) qemu_register_reset(main_cpu_reset, cpu); /* RAM */ - ram = g_malloc(sizeof(*ram)); - memory_region_init_ram(ram, NULL, "m68k_mac.ram", ram_size, &error_abort); - memory_region_add_subregion(get_system_memory(), 0, ram); + memory_region_add_subregion(get_system_memory(), 0, machine->ram); /* * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated @@ -443,6 +440,7 @@ static void q800_machine_class_init(ObjectClass *oc, void *data) mc->max_cpus = 1; mc->is_default = 0; mc->block_default_type = IF_SCSI; + mc->default_ram_id = "m68k_mac.ram"; } static const TypeInfo q800_machine_typeinfo = { diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 0df3a7755a..98ecd25e8e 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -427,7 +427,7 @@ static void boston_mach_init(MachineState *machine) DeviceState *dev; BostonState *s; Error *err = NULL; - MemoryRegion *flash, *ddr, *ddr_low_alias, *lcd, *platreg; + MemoryRegion *flash, *ddr_low_alias, *lcd, *platreg; MemoryRegion *sys_mem = get_system_memory(); XilinxPCIEHost *pcie2; PCIDevice *ahci; @@ -473,14 +473,12 @@ static void boston_mach_init(MachineState *machine) memory_region_init_rom(flash, NULL, "boston.flash", 128 * MiB, &err); memory_region_add_subregion_overlap(sys_mem, 0x18000000, flash, 0); - ddr = g_new(MemoryRegion, 1); - memory_region_allocate_system_memory(ddr, NULL, "boston.ddr", - machine->ram_size); - memory_region_add_subregion_overlap(sys_mem, 0x80000000, ddr, 0); + memory_region_add_subregion_overlap(sys_mem, 0x80000000, machine->ram, 0); ddr_low_alias = g_new(MemoryRegion, 1); memory_region_init_alias(ddr_low_alias, NULL, "boston_low.ddr", - ddr, 0, MIN(machine->ram_size, (256 * MiB))); + machine->ram, 0, + MIN(machine->ram_size, (256 * MiB))); memory_region_add_subregion_overlap(sys_mem, 0, ddr_low_alias, 0); xilinx_pcie_init(sys_mem, 0, @@ -552,6 +550,7 @@ static void boston_mach_class_init(MachineClass *mc) mc->init = boston_mach_init; mc->block_default_type = IF_IDE; mc->default_ram_size = 1 * GiB; + mc->default_ram_id = "boston.ddr"; mc->max_cpus = 16; mc->default_cpu_type = MIPS_CPU_TYPE_NAME("I6400"); } diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 2e043cbb98..c373ab066b 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -294,9 +294,7 @@ static void mips_fulong2e_init(MachineState *machine) const char *initrd_filename = machine->initrd_filename; char *filename; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); - ram_addr_t ram_size = machine->ram_size; long bios_size; uint8_t *spd_data; Error *err = NULL; @@ -315,15 +313,17 @@ static void mips_fulong2e_init(MachineState *machine) qemu_register_reset(main_cpu_reset, cpu); /* TODO: support more than 256M RAM as highmem */ - ram_size = 256 * MiB; + if (machine->ram_size != 256 * MiB) { + error_report("Invalid RAM size, should be 256MB"); + exit(EXIT_FAILURE); + } /* allocate RAM */ - memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_size); memory_region_init_ram(bios, NULL, "fulong2e.bios", BIOS_SIZE, &error_fatal); memory_region_set_readonly(bios, true); - memory_region_add_subregion(address_space_mem, 0, ram); + memory_region_add_subregion(address_space_mem, 0, machine->ram); memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); /* @@ -332,7 +332,7 @@ static void mips_fulong2e_init(MachineState *machine) */ if (kernel_filename) { - loaderparams.ram_size = ram_size; + loaderparams.ram_size = machine->ram_size; loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; @@ -378,7 +378,7 @@ static void mips_fulong2e_init(MachineState *machine) } /* Populate SPD eeprom data */ - spd_data = spd_data_generate(DDR, ram_size, &err); + spd_data = spd_data_generate(DDR, machine->ram_size, &err); if (err) { warn_report_err(err); } @@ -399,6 +399,7 @@ static void mips_fulong2e_machine_init(MachineClass *mc) mc->block_default_type = IF_IDE; mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E"); mc->default_ram_size = 256 * MiB; + mc->default_ram_id = "fulong2e.ram"; } DEFINE_MACHINE("fulong2e", mips_fulong2e_machine_init) diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 66fd4d867d..32fbd10b4e 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -159,12 +159,16 @@ static void mips_jazz_init(MachineState *machine, ISABus *isa_bus; ISADevice *pit; DriveInfo *fds[MAX_FD]; - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); MemoryRegion *bios2 = g_new(MemoryRegion, 1); SysBusESPState *sysbus_esp; ESPState *esp; + if (machine->ram_size > 256 * MiB) { + error_report("RAM size more than 256Mb is not supported"); + exit(EXIT_FAILURE); + } + /* init CPUs */ cpu = MIPS_CPU(cpu_create(machine->cpu_type)); env = &cpu->env; @@ -191,9 +195,7 @@ static void mips_jazz_init(MachineState *machine, cc->do_transaction_failed = mips_jazz_do_transaction_failed; /* allocate RAM */ - memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", - machine->ram_size); - memory_region_add_subregion(address_space, 0, ram); + memory_region_add_subregion(address_space, 0, machine->ram); memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, &error_fatal); @@ -393,6 +395,7 @@ static void mips_magnum_class_init(ObjectClass *oc, void *data) mc->init = mips_magnum_init; mc->block_default_type = IF_SCSI; mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); + mc->default_ram_id = "mips_jazz.ram"; } static const TypeInfo mips_magnum_type = { @@ -409,6 +412,7 @@ static void mips_pica61_class_init(ObjectClass *oc, void *data) mc->init = mips_pica61_init; mc->block_default_type = IF_SCSI; mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); + mc->default_ram_id = "mips_jazz.ram"; } static const TypeInfo mips_pica61_type = { diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 34b76bb6a1..6e7ba9235d 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1224,7 +1224,6 @@ void mips_malta_init(MachineState *machine) char *filename; PFlashCFI01 *fl; MemoryRegion *system_memory = get_system_memory(); - MemoryRegion *ram_high = g_new(MemoryRegion, 1); MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); MemoryRegion *ram_low_postio; MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); @@ -1262,13 +1261,11 @@ void mips_malta_init(MachineState *machine) } /* register RAM at high address where it is undisturbed by IO */ - memory_region_allocate_system_memory(ram_high, NULL, "mips_malta.ram", - ram_size); - memory_region_add_subregion(system_memory, 0x80000000, ram_high); + memory_region_add_subregion(system_memory, 0x80000000, machine->ram); /* alias for pre IO hole access */ memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram", - ram_high, 0, MIN(ram_size, 256 * MiB)); + machine->ram, 0, MIN(ram_size, 256 * MiB)); memory_region_add_subregion(system_memory, 0, ram_low_preio); /* alias for post IO hole access, if there is enough RAM */ @@ -1276,7 +1273,7 @@ void mips_malta_init(MachineState *machine) ram_low_postio = g_new(MemoryRegion, 1); memory_region_init_alias(ram_low_postio, NULL, "mips_malta_low_postio.ram", - ram_high, 512 * MiB, + machine->ram, 512 * MiB, ram_size - 512 * MiB); memory_region_add_subregion(system_memory, 512 * MiB, ram_low_postio); @@ -1448,6 +1445,7 @@ static void mips_malta_machine_init(MachineClass *mc) #else mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); #endif + mc->default_ram_id = "mips_malta.ram"; } DEFINE_MACHINE("malta", mips_malta_machine_init) diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index b934ca9d51..b2555ddb89 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -143,14 +143,12 @@ static void mipsnet_init(int base, qemu_irq irq, NICInfo *nd) static void mips_mipssim_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; char *filename; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *isa = g_new(MemoryRegion, 1); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); MIPSCPU *cpu; CPUMIPSState *env; @@ -167,13 +165,11 @@ mips_mipssim_init(MachineState *machine) qemu_register_reset(main_cpu_reset, reset_info); /* Allocate RAM. */ - memory_region_allocate_system_memory(ram, NULL, "mips_mipssim.ram", - ram_size); memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE, &error_fatal); memory_region_set_readonly(bios, true); - memory_region_add_subregion(address_space_mem, 0, ram); + memory_region_add_subregion(address_space_mem, 0, machine->ram); /* Map the BIOS / boot exception handler. */ memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios); @@ -200,7 +196,7 @@ mips_mipssim_init(MachineState *machine) } if (kernel_filename) { - loaderparams.ram_size = ram_size; + loaderparams.ram_size = machine->ram_size; loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; @@ -245,6 +241,7 @@ static void mips_mipssim_machine_init(MachineClass *mc) #else mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); #endif + mc->default_ram_id = "mips_mipssim.ram"; } DEFINE_MACHINE("mipssim", mips_mipssim_machine_init) diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index b2aec434c3..258cd91578 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -171,13 +171,11 @@ static const int sector_len = 32 * KiB; static void mips_r4k_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; char *filename; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios; MemoryRegion *iomem = g_new(MemoryRegion, 1); MemoryRegion *isa_io = g_new(MemoryRegion, 1); @@ -203,14 +201,12 @@ void mips_r4k_init(MachineState *machine) qemu_register_reset(main_cpu_reset, reset_info); /* allocate RAM */ - if (ram_size > 256 * MiB) { + if (machine->ram_size > 256 * MiB) { error_report("Too much memory for this machine: %" PRId64 "MB," " maximum 256MB", ram_size / MiB); exit(1); } - memory_region_allocate_system_memory(ram, NULL, "mips_r4k.ram", ram_size); - - memory_region_add_subregion(address_space_mem, 0, ram); + memory_region_add_subregion(address_space_mem, 0, machine->ram); memory_region_init_io(iomem, NULL, &mips_qemu_ops, NULL, "mips-qemu", 0x10000); @@ -261,7 +257,7 @@ void mips_r4k_init(MachineState *machine) g_free(filename); if (kernel_filename) { - loaderparams.ram_size = ram_size; + loaderparams.ram_size = machine->ram_size; loaderparams.kernel_filename = kernel_filename; loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.initrd_filename = initrd_filename; @@ -316,7 +312,7 @@ static void mips_machine_init(MachineClass *mc) #else mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf"); #endif - + mc->default_ram_id = "mips_r4k.ram"; } DEFINE_MACHINE("mips", mips_machine_init) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 9c184790cd..7b466bf19a 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -17,6 +17,9 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "trace.h" +#include "qemu/units.h" +#include "qemu/cutils.h" +#include "qapi/visitor.h" /* Protection Key Register */ #define R_PROT (0x00 / 4) @@ -160,14 +163,9 @@ static int ast2400_rambits(AspeedSDMCState *s) case 512: return ASPEED_SDMC_DRAM_512MB; default: + g_assert_not_reached(); break; } - - /* use a common default */ - warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M", - s->ram_size); - s->ram_size = 256 << 20; - return ASPEED_SDMC_DRAM_256MB; } static int ast2500_rambits(AspeedSDMCState *s) @@ -182,14 +180,9 @@ static int ast2500_rambits(AspeedSDMCState *s) case 1024: return ASPEED_SDMC_AST2500_1024MB; default: + g_assert_not_reached(); break; } - - /* use a common default */ - warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M", - s->ram_size); - s->ram_size = 512 << 20; - return ASPEED_SDMC_AST2500_512MB; } static int ast2600_rambits(AspeedSDMCState *s) @@ -204,14 +197,9 @@ static int ast2600_rambits(AspeedSDMCState *s) case 2048: return ASPEED_SDMC_AST2600_2048MB; default: + g_assert_not_reached(); break; } - - /* use a common default */ - warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 1024M", - s->ram_size); - s->ram_size = 1024 << 20; - return ASPEED_SDMC_AST2600_1024MB; } static void aspeed_sdmc_reset(DeviceState *dev) @@ -225,6 +213,51 @@ static void aspeed_sdmc_reset(DeviceState *dev) s->regs[R_CONF] = asc->compute_conf(s, 0); } +static void aspeed_sdmc_get_ram_size(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + AspeedSDMCState *s = ASPEED_SDMC(obj); + int64_t value = s->ram_size; + + visit_type_int(v, name, &value, errp); +} + +static void aspeed_sdmc_set_ram_size(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + int i; + char *sz; + int64_t value; + Error *local_err = NULL; + AspeedSDMCState *s = ASPEED_SDMC(obj); + AspeedSDMCClass *asc = ASPEED_SDMC_GET_CLASS(s); + + visit_type_int(v, name, &value, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + + for (i = 0; asc->valid_ram_sizes[i]; i++) { + if (value == asc->valid_ram_sizes[i]) { + s->ram_size = value; + return; + } + } + + sz = size_to_str(value); + error_setg(&local_err, "Invalid RAM size %s", sz); + g_free(sz); + error_propagate(errp, local_err); +} + +static void aspeed_sdmc_initfn(Object *obj) +{ + object_property_add(obj, "ram-size", "int", + aspeed_sdmc_get_ram_size, aspeed_sdmc_set_ram_size, + NULL, NULL, NULL); +} + static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -249,7 +282,6 @@ static const VMStateDescription vmstate_aspeed_sdmc = { }; static Property aspeed_sdmc_properties[] = { - DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0), DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), DEFINE_PROP_END_OF_LIST(), }; @@ -268,6 +300,7 @@ static const TypeInfo aspeed_sdmc_info = { .name = TYPE_ASPEED_SDMC, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(AspeedSDMCState), + .instance_init = aspeed_sdmc_initfn, .class_init = aspeed_sdmc_class_init, .class_size = sizeof(AspeedSDMCClass), .abstract = true, @@ -298,6 +331,9 @@ static void aspeed_2400_sdmc_write(AspeedSDMCState *s, uint32_t reg, s->regs[reg] = data; } +static const uint64_t +aspeed_2400_ram_sizes[] = { 64 * MiB, 128 * MiB, 256 * MiB, 512 * MiB, 0}; + static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -307,6 +343,7 @@ static void aspeed_2400_sdmc_class_init(ObjectClass *klass, void *data) asc->max_ram_size = 512 << 20; asc->compute_conf = aspeed_2400_sdmc_compute_conf; asc->write = aspeed_2400_sdmc_write; + asc->valid_ram_sizes = aspeed_2400_ram_sizes; } static const TypeInfo aspeed_2400_sdmc_info = { @@ -351,6 +388,9 @@ static void aspeed_2500_sdmc_write(AspeedSDMCState *s, uint32_t reg, s->regs[reg] = data; } +static const uint64_t +aspeed_2500_ram_sizes[] = { 128 * MiB, 256 * MiB, 512 * MiB, 1024 * MiB, 0}; + static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -360,6 +400,7 @@ static void aspeed_2500_sdmc_class_init(ObjectClass *klass, void *data) asc->max_ram_size = 1024 << 20; asc->compute_conf = aspeed_2500_sdmc_compute_conf; asc->write = aspeed_2500_sdmc_write; + asc->valid_ram_sizes = aspeed_2500_ram_sizes; } static const TypeInfo aspeed_2500_sdmc_info = { @@ -404,6 +445,9 @@ static void aspeed_2600_sdmc_write(AspeedSDMCState *s, uint32_t reg, s->regs[reg] = data; } +static const uint64_t +aspeed_2600_ram_sizes[] = { 256 * MiB, 512 * MiB, 1024 * MiB, 2048 * MiB, 0}; + static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -413,6 +457,7 @@ static void aspeed_2600_sdmc_class_init(ObjectClass *klass, void *data) asc->max_ram_size = 2048 << 20; asc->compute_conf = aspeed_2600_sdmc_compute_conf; asc->write = aspeed_2600_sdmc_write; + asc->valid_ram_sizes = aspeed_2600_ram_sizes; } static const TypeInfo aspeed_2600_sdmc_info = { diff --git a/hw/misc/pc-testdev.c b/hw/misc/pc-testdev.c index 0fb84ddc6b..8aa8e6549f 100644 --- a/hw/misc/pc-testdev.c +++ b/hw/misc/pc-testdev.c @@ -125,7 +125,7 @@ static void test_flush_page_write(void *opaque, hwaddr addr, uint64_t data, unsigned len) { hwaddr page = 4096; - void *a = cpu_physical_memory_map(data & ~0xffful, &page, 0); + void *a = cpu_physical_memory_map(data & ~0xffful, &page, false); /* We might not be able to get the full page, only mprotect what we actually have mapped */ diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 871fcf2031..ddabdb3f90 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -871,7 +871,7 @@ static void gem_get_rx_desc(CadenceGEMState *s, int q) /* read current descriptor */ address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->rx_desc[q], + s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); /* Descriptor owned by software ? */ @@ -1029,9 +1029,8 @@ static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size) /* Descriptor write-back. */ desc_addr = gem_get_rx_desc_addr(s, q); - address_space_write(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->rx_desc[q], + address_space_write(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED, + s->rx_desc[q], sizeof(uint32_t) * gem_get_desc_len(s, true)); /* Next descriptor */ @@ -1137,7 +1136,7 @@ static void gem_transmit(CadenceGEMState *s) DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); address_space_read(&s->dma_as, packet_desc_addr, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, + MEMTXATTRS_UNSPECIFIED, desc, sizeof(uint32_t) * gem_get_desc_len(s, false)); /* Handle all descriptors owned by hardware */ while (tx_desc_get_used(desc) == 0) { @@ -1185,14 +1184,12 @@ static void gem_transmit(CadenceGEMState *s) * the processor. */ address_space_read(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)desc_first, + MEMTXATTRS_UNSPECIFIED, desc_first, sizeof(desc_first)); tx_desc_set_used(desc_first); address_space_write(&s->dma_as, desc_addr, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)desc_first, - sizeof(desc_first)); + MEMTXATTRS_UNSPECIFIED, desc_first, + sizeof(desc_first)); /* Advance the hardware current descriptor past this packet */ if (tx_desc_get_wrap(desc)) { s->tx_desc_addr[q] = s->regs[GEM_TXQBASE]; @@ -1246,8 +1243,8 @@ static void gem_transmit(CadenceGEMState *s) } DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr); address_space_read(&s->dma_as, packet_desc_addr, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc, - sizeof(uint32_t) * gem_get_desc_len(s, false)); + MEMTXATTRS_UNSPECIFIED, desc, + sizeof(uint32_t) * gem_get_desc_len(s, false)); } if (tx_desc_get_used(desc)) { diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index a134d431ae..70451934ae 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -275,8 +275,8 @@ static void dp8393x_do_load_cam(dp8393xState *s) while (s->regs[SONIC_CDC] & 0x1f) { /* Fill current entry */ - address_space_rw(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, dp8393x_cdp(s), + MEMTXATTRS_UNSPECIFIED, s->data, size); s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff; s->cam[index][1] = dp8393x_get(s, width, 1) >> 8; s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff; @@ -293,8 +293,8 @@ static void dp8393x_do_load_cam(dp8393xState *s) } /* Read CAM enable */ - address_space_rw(&s->as, dp8393x_cdp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, dp8393x_cdp(s), + MEMTXATTRS_UNSPECIFIED, s->data, size); s->regs[SONIC_CE] = dp8393x_get(s, width, 0); DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]); @@ -311,8 +311,8 @@ static void dp8393x_do_read_rra(dp8393xState *s) /* Read memory */ width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1; size = sizeof(uint16_t) * 4 * width; - address_space_rw(&s->as, dp8393x_rrp(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, dp8393x_rrp(s), + MEMTXATTRS_UNSPECIFIED, s->data, size); /* Update SONIC registers */ s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0); @@ -426,8 +426,8 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) size = sizeof(uint16_t) * 6 * width; s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA]; DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s)); - address_space_rw(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width, + MEMTXATTRS_UNSPECIFIED, s->data, size); tx_len = 0; /* Update registers */ @@ -451,17 +451,19 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) if (tx_len + len > sizeof(s->tx_buffer)) { len = sizeof(s->tx_buffer) - tx_len; } - address_space_rw(&s->as, dp8393x_tsa(s), - MEMTXATTRS_UNSPECIFIED, &s->tx_buffer[tx_len], len, 0); + address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED, + &s->tx_buffer[tx_len], len); tx_len += len; i++; if (i != s->regs[SONIC_TFC]) { /* Read next fragment details */ size = sizeof(uint16_t) * 3 * width; - address_space_rw(&s->as, - dp8393x_ttda(s) + sizeof(uint16_t) * (4 + 3 * i) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, + dp8393x_ttda(s) + + sizeof(uint16_t) * width * (4 + 3 * i), + MEMTXATTRS_UNSPECIFIED, s->data, + size); s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0); s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1); s->regs[SONIC_TFS] = dp8393x_get(s, width, 2); @@ -494,18 +496,18 @@ static void dp8393x_do_transmit_packets(dp8393xState *s) dp8393x_put(s, width, 0, s->regs[SONIC_TCR] & 0x0fff); /* status */ size = sizeof(uint16_t) * width; - address_space_rw(&s->as, - dp8393x_ttda(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); + address_space_write(&s->as, dp8393x_ttda(s), + MEMTXATTRS_UNSPECIFIED, s->data, size); if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) { /* Read footer of packet */ size = sizeof(uint16_t) * width; - address_space_rw(&s->as, - dp8393x_ttda(s) + - sizeof(uint16_t) * - (4 + 3 * s->regs[SONIC_TFC]) * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, + dp8393x_ttda(s) + + sizeof(uint16_t) * width + * (4 + 3 * s->regs[SONIC_TFC]), + MEMTXATTRS_UNSPECIFIED, s->data, + size); s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0) & ~0x1; if (dp8393x_get(s, width, 0) & 0x1) { /* EOL detected */ @@ -767,8 +769,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, /* Are we still in resource exhaustion? */ size = sizeof(uint16_t) * 1 * width; address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width; - address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->data, size, 0); + address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED, + s->data, size); if (dp8393x_get(s, width, 0) & 0x1) { /* Still EOL ; stop reception */ return -1; @@ -787,11 +789,11 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, /* Put packet into RBA */ DPRINTF("Receive packet at %08x\n", dp8393x_crba(s)); address = dp8393x_crba(s); - address_space_rw(&s->as, address, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)buf, rx_len, 1); + address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, + buf, rx_len); address += rx_len; - address_space_rw(&s->as, address, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)&checksum, 4, 1); + address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED, + &checksum, 4); rx_len += 4; s->regs[SONIC_CRBA1] = address >> 16; s->regs[SONIC_CRBA0] = address & 0xffff; @@ -819,13 +821,15 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */ dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */ size = sizeof(uint16_t) * 5 * width; - address_space_rw(&s->as, dp8393x_crda(s), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 1); + address_space_write(&s->as, dp8393x_crda(s), + MEMTXATTRS_UNSPECIFIED, + s->data, size); /* Move to next descriptor */ size = sizeof(uint16_t) * width; - address_space_rw(&s->as, dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, - MEMTXATTRS_UNSPECIFIED, (uint8_t *)s->data, size, 0); + address_space_read(&s->as, + dp8393x_crda(s) + sizeof(uint16_t) * 5 * width, + MEMTXATTRS_UNSPECIFIED, s->data, size); s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0); if (s->regs[SONIC_LLFA] & 0x1) { /* EOL detected */ @@ -838,8 +842,8 @@ static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf, offset += sizeof(uint16_t); } s->data[0] = 0; - address_space_rw(&s->as, offset, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)s->data, sizeof(uint16_t), 1); + address_space_write(&s->as, offset, MEMTXATTRS_UNSPECIFIED, + s->data, sizeof(uint16_t)); s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA]; s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX; s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) | (((s->regs[SONIC_RSC] & 0x00ff) + 1) & 0x00ff); diff --git a/hw/net/i82596.c b/hw/net/i82596.c index 3a0e1ec4c0..fe9f2390a9 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -148,8 +148,8 @@ static void i82596_transmit(I82596State *s, uint32_t addr) if (s->nic && len) { assert(len <= sizeof(s->tx_buffer)); - address_space_rw(&address_space_memory, tba, - MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len, 0); + address_space_read(&address_space_memory, tba, + MEMTXATTRS_UNSPECIFIED, s->tx_buffer, len); DBG(PRINT_PKTHDR("Send", &s->tx_buffer)); DBG(printf("Sending %d bytes\n", len)); qemu_send_packet(qemu_get_queue(s->nic), s->tx_buffer, len); @@ -172,8 +172,8 @@ static void set_individual_address(I82596State *s, uint32_t addr) nc = qemu_get_queue(s->nic); m = s->conf.macaddr.a; - address_space_rw(&address_space_memory, addr + 8, - MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN, 0); + address_space_read(&address_space_memory, addr + 8, + MEMTXATTRS_UNSPECIFIED, m, ETH_ALEN); qemu_format_nic_info_str(nc, m); trace_i82596_new_mac(nc->info_str); } @@ -190,9 +190,8 @@ static void set_multicast_list(I82596State *s, uint32_t addr) } for (i = 0; i < mc_count; i++) { uint8_t multicast_addr[ETH_ALEN]; - address_space_rw(&address_space_memory, - addr + i * ETH_ALEN, MEMTXATTRS_UNSPECIFIED, - multicast_addr, ETH_ALEN, 0); + address_space_read(&address_space_memory, addr + i * ETH_ALEN, + MEMTXATTRS_UNSPECIFIED, multicast_addr, ETH_ALEN); DBG(printf("Add multicast entry " MAC_FMT "\n", MAC_ARG(multicast_addr))); unsigned mcast_idx = (net_crc32(multicast_addr, ETH_ALEN) & @@ -260,8 +259,8 @@ static void command_loop(I82596State *s) byte_cnt = MAX(byte_cnt, 4); byte_cnt = MIN(byte_cnt, sizeof(s->config)); /* copy byte_cnt max. */ - address_space_rw(&address_space_memory, s->cmd_p + 8, - MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt, 0); + address_space_read(&address_space_memory, s->cmd_p + 8, + MEMTXATTRS_UNSPECIFIED, s->config, byte_cnt); /* config byte according to page 35ff */ s->config[2] &= 0x82; /* mask valid bits */ s->config[2] |= 0x40; @@ -640,14 +639,14 @@ ssize_t i82596_receive(NetClientState *nc, const uint8_t *buf, size_t sz) } rba = get_uint32(rbd + 8); /* printf("rba is 0x%x\n", rba); */ - address_space_rw(&address_space_memory, rba, - MEMTXATTRS_UNSPECIFIED, (void *)buf, num, 1); + address_space_write(&address_space_memory, rba, + MEMTXATTRS_UNSPECIFIED, buf, num); rba += num; buf += num; len -= num; if (len == 0) { /* copy crc */ - address_space_rw(&address_space_memory, rba - 4, - MEMTXATTRS_UNSPECIFIED, crc_ptr, 4, 1); + address_space_write(&address_space_memory, rba - 4, + MEMTXATTRS_UNSPECIFIED, crc_ptr, 4); } num |= 0x4000; /* set F BIT */ diff --git a/hw/net/lasi_i82596.c b/hw/net/lasi_i82596.c index 427b3fbf70..52637a562d 100644 --- a/hw/net/lasi_i82596.c +++ b/hw/net/lasi_i82596.c @@ -55,8 +55,9 @@ static void lasi_82596_mem_write(void *opaque, hwaddr addr, * Provided for SeaBIOS only. Write MAC of Network card to addr @val. * Needed for the PDC_LAN_STATION_ID_READ PDC call. */ - address_space_rw(&address_space_memory, val, - MEMTXATTRS_UNSPECIFIED, d->state.conf.macaddr.a, ETH_ALEN, 1); + address_space_write(&address_space_memory, val, + MEMTXATTRS_UNSPECIFIED, d->state.conf.macaddr.a, + ETH_ALEN); break; } } diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c index 877ddef7b9..15d08281d4 100644 --- a/hw/nvram/spapr_nvram.c +++ b/hw/nvram/spapr_nvram.c @@ -89,7 +89,7 @@ static void rtas_nvram_fetch(PowerPCCPU *cpu, SpaprMachineState *spapr, assert(nvram->buf); - membuf = cpu_physical_memory_map(buffer, &len, 1); + membuf = cpu_physical_memory_map(buffer, &len, true); memcpy(membuf, nvram->buf + offset, len); cpu_physical_memory_unmap(membuf, len, 1, len); @@ -127,7 +127,7 @@ static void rtas_nvram_store(PowerPCCPU *cpu, SpaprMachineState *spapr, return; } - membuf = cpu_physical_memory_map(buffer, &len, 0); + membuf = cpu_physical_memory_map(buffer, &len, false); alen = len; if (nvram->blk) { diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index af537bba2b..854cd3ac46 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -832,7 +832,6 @@ static void ppce500_power_off(void *opaque, int line, int on) void ppce500_init(MachineState *machine) { MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); PPCE500MachineState *pms = PPCE500_MACHINE(machine); const PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); PCIBus *pci_bus; @@ -907,13 +906,13 @@ void ppce500_init(MachineState *machine) env = firstenv; - /* Fixup Memory size on a alignment boundary */ - ram_size &= ~(RAM_SIZES_ALIGN - 1); - machine->ram_size = ram_size; + if (!QEMU_IS_ALIGNED(machine->ram_size, RAM_SIZES_ALIGN)) { + error_report("RAM size must be multiple of %" PRIu64, RAM_SIZES_ALIGN); + exit(EXIT_FAILURE); + } /* Register Memory */ - memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size); - memory_region_add_subregion(address_space_mem, 0, ram); + memory_region_add_subregion(address_space_mem, 0, machine->ram); dev = qdev_create(NULL, "e500-ccsr"); object_property_add_child(qdev_get_machine(), "e500-ccsr", @@ -1084,7 +1083,7 @@ void ppce500_init(MachineState *machine) kernel_base = cur_base; kernel_size = load_image_targphys(machine->kernel_filename, cur_base, - ram_size - cur_base); + machine->ram_size - cur_base); if (kernel_size < 0) { error_report("could not load kernel '%s'", machine->kernel_filename); @@ -1098,7 +1097,7 @@ void ppce500_init(MachineState *machine) if (machine->initrd_filename) { initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK; initrd_size = load_image_targphys(machine->initrd_filename, initrd_base, - ram_size - initrd_base); + machine->ram_size - initrd_base); if (initrd_size < 0) { error_report("could not load initial ram disk '%s'", @@ -1116,7 +1115,7 @@ void ppce500_init(MachineState *machine) * ensures enough space between kernel and initrd. */ dt_base = (loadaddr + payload_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK; - if (dt_base + DTB_MAX_SIZE > ram_size) { + if (dt_base + DTB_MAX_SIZE > machine->ram_size) { error_report("not enough memory for device tree"); exit(1); } diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 7078386300..bddd5e7c48 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -97,6 +97,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) mc->init = e500plat_init; mc->max_cpus = 32; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30"); + mc->default_ram_id = "mpc8544ds.ram"; machine_class_allow_dynamic_sysbus_dev(mc, TYPE_ETSEC_COMMON); } diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 464d012103..b8189bf7a4 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -118,7 +118,7 @@ static void ppc_core99_init(MachineState *machine) char *filename; IrqLines *openpic_irqs; int linux_boot, i, j, k; - MemoryRegion *ram = g_new(MemoryRegion, 1), *bios = g_new(MemoryRegion, 1); + MemoryRegion *bios = g_new(MemoryRegion, 1); hwaddr kernel_base, initrd_base, cmdline_base = 0; long kernel_size, initrd_size; UNINHostState *uninorth_pci; @@ -152,8 +152,7 @@ static void ppc_core99_init(MachineState *machine) } /* allocate RAM */ - memory_region_allocate_system_memory(ram, NULL, "ppc_core99.ram", ram_size); - memory_region_add_subregion(get_system_memory(), 0, ram); + memory_region_add_subregion(get_system_memory(), 0, machine->ram); /* allocate and load BIOS */ memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, @@ -586,6 +585,7 @@ static void core99_machine_class_init(ObjectClass *oc, void *data) #else mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9"); #endif + mc->default_ram_id = "ppc_core99.ram"; mc->ignore_boot_device_suffixes = true; fwc->get_dev_path = core99_fw_dev_path; } diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 7318d7e9b4..66e434bba3 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -91,7 +91,6 @@ static void ppc_heathrow_init(MachineState *machine) CPUPPCState *env = NULL; char *filename; int linux_boot, i; - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); uint32_t kernel_base, initrd_base, cmdline_base = 0; int32_t kernel_size, initrd_size; @@ -127,9 +126,7 @@ static void ppc_heathrow_init(MachineState *machine) exit(1); } - memory_region_allocate_system_memory(ram, NULL, "ppc_heathrow.ram", - ram_size); - memory_region_add_subregion(sysmem, 0, ram); + memory_region_add_subregion(sysmem, 0, machine->ram); /* allocate and load BIOS */ memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, @@ -446,6 +443,7 @@ static void heathrow_class_init(ObjectClass *oc, void *data) mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1"); mc->default_display = "std"; mc->ignore_boot_device_suffixes = true; + mc->default_ram_id = "ppc_heathrow.ram"; fwc->get_dev_path = heathrow_fw_dev_path; } diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c index c2c5e11fa1..81177505f0 100644 --- a/hw/ppc/mpc8544ds.c +++ b/hw/ppc/mpc8544ds.c @@ -55,6 +55,7 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) mc->init = mpc8544ds_init; mc->max_cpus = 15; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30"); + mc->default_ram_id = "mpc8544ds.ram"; } #define TYPE_MPC8544DS_MACHINE MACHINE_TYPE_NAME("mpc8544ds") diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index e98038b809..b75ad06390 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -692,7 +692,6 @@ static void pnv_init(MachineState *machine) { PnvMachineState *pnv = PNV_MACHINE(machine); MachineClass *mc = MACHINE_GET_CLASS(machine); - MemoryRegion *ram; char *fw_filename; long fw_size; int i; @@ -704,11 +703,7 @@ static void pnv_init(MachineState *machine) if (machine->ram_size < (1 * GiB)) { warn_report("skiboot may not work with < 1GB of RAM"); } - - ram = g_new(MemoryRegion, 1); - memory_region_allocate_system_memory(ram, NULL, "pnv.ram", - machine->ram_size); - memory_region_add_subregion(get_system_memory(), 0, ram); + memory_region_add_subregion(get_system_memory(), 0, machine->ram); /* * Create our simple PNOR device @@ -1978,6 +1973,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) * enough to fit the maximum initrd size at it's load address */ mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; + mc->default_ram_id = "pnv.ram"; ispc->print_info = pnv_pic_print_info; object_class_property_add_bool(oc, "hb-mode", diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 5989d723c5..f150deca34 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -238,16 +238,16 @@ static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data, int sz) { /* XXX Handle access size limits and FW read caching here */ - return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, - data, sz, false); + return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, + data, sz); } static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, int sz) { /* XXX Handle access size limits here */ - return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, - data, sz, true); + return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, + data, sz); } #define ECCB_CTL_READ PPC_BIT(15) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 1f721feed6..de93c40f1a 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -40,6 +40,7 @@ #include "qemu/error-report.h" #include "hw/loader.h" #include "exec/address-spaces.h" +#include "qemu/cutils.h" #define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_SIZE (2 * MiB) @@ -137,7 +138,7 @@ static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) static void ref405ep_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; + MachineClass *mc = MACHINE_GET_CLASS(machine); const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -161,15 +162,21 @@ static void ref405ep_init(MachineState *machine) DriveInfo *dinfo; MemoryRegion *sysmem = get_system_memory(); + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + /* XXX: fix this */ - memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram", - 0x08000000); + memory_region_init_alias(&ram_memories[0], NULL, "ef405ep.ram.alias", + machine->ram, 0, machine->ram_size); ram_bases[0] = 0; - ram_sizes[0] = 0x08000000; + ram_sizes[0] = machine->ram_size; memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0); ram_bases[1] = 0x00000000; ram_sizes[1] = 0x00000000; - ram_size = 128 * MiB; env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate SRAM */ @@ -227,7 +234,7 @@ static void ref405ep_init(MachineState *machine) if (linux_boot) { memset(&bd, 0, sizeof(bd)); bd.bi_memstart = 0x00000000; - bd.bi_memsize = ram_size; + bd.bi_memsize = machine->ram_size; bd.bi_flashstart = -bios_size; bd.bi_flashsize = -bios_size; bd.bi_flashoffset = 0; @@ -255,7 +262,7 @@ static void ref405ep_init(MachineState *machine) kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ kernel_size = load_image_targphys(kernel_filename, kernel_base, - ram_size - kernel_base); + machine->ram_size - kernel_base); if (kernel_size < 0) { error_report("could not load kernel '%s'", kernel_filename); exit(1); @@ -266,7 +273,7 @@ static void ref405ep_init(MachineState *machine) if (initrd_filename) { initrd_base = INITRD_LOAD_ADDR; initrd_size = load_image_targphys(initrd_filename, initrd_base, - ram_size - initrd_base); + machine->ram_size - initrd_base); if (initrd_size < 0) { error_report("could not load initial ram disk '%s'", initrd_filename); @@ -304,6 +311,8 @@ static void ref405ep_class_init(ObjectClass *oc, void *data) mc->desc = "ref405ep"; mc->init = ref405ep_init; + mc->default_ram_size = 0x08000000; + mc->default_ram_id = "ef405ep.ram"; } static const TypeInfo ref405ep_type = { @@ -408,7 +417,7 @@ static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base) static void taihu_405ep_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; + MachineClass *mc = MACHINE_GET_CLASS(machine); const char *kernel_filename = machine->kernel_filename; const char *initrd_filename = machine->initrd_filename; char *filename; @@ -416,7 +425,6 @@ static void taihu_405ep_init(MachineState *machine) MemoryRegion *sysmem = get_system_memory(); MemoryRegion *bios; MemoryRegion *ram_memories = g_new(MemoryRegion, 2); - MemoryRegion *ram = g_malloc0(sizeof(*ram)); hwaddr ram_bases[2], ram_sizes[2]; long bios_size; target_ulong kernel_base, initrd_base; @@ -425,20 +433,22 @@ static void taihu_405ep_init(MachineState *machine) int fl_idx; DriveInfo *dinfo; - /* RAM is soldered to the board so the size cannot be changed */ - ram_size = 0x08000000; - memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram", - ram_size); + if (machine->ram_size != mc->default_ram_size) { + char *sz = size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } ram_bases[0] = 0; ram_sizes[0] = 0x04000000; memory_region_init_alias(&ram_memories[0], NULL, - "taihu_405ep.ram-0", ram, ram_bases[0], + "taihu_405ep.ram-0", machine->ram, ram_bases[0], ram_sizes[0]); ram_bases[1] = 0x04000000; ram_sizes[1] = 0x04000000; memory_region_init_alias(&ram_memories[1], NULL, - "taihu_405ep.ram-1", ram, ram_bases[1], + "taihu_405ep.ram-1", machine->ram, ram_bases[1], ram_sizes[1]); ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes, 33333333, &pic, kernel_filename == NULL ? 0 : 1); @@ -500,7 +510,7 @@ static void taihu_405ep_init(MachineState *machine) kernel_base = KERNEL_LOAD_ADDR; /* now we can load the kernel */ kernel_size = load_image_targphys(kernel_filename, kernel_base, - ram_size - kernel_base); + machine->ram_size - kernel_base); if (kernel_size < 0) { error_report("could not load kernel '%s'", kernel_filename); exit(1); @@ -509,7 +519,7 @@ static void taihu_405ep_init(MachineState *machine) if (initrd_filename) { initrd_base = INITRD_LOAD_ADDR; initrd_size = load_image_targphys(initrd_filename, initrd_base, - ram_size - initrd_base); + machine->ram_size - initrd_base); if (initrd_size < 0) { error_report("could not load initial ram disk '%s'", initrd_filename); @@ -533,6 +543,8 @@ static void taihu_class_init(ObjectClass *oc, void *data) mc->desc = "taihu"; mc->init = taihu_405ep_init; + mc->default_ram_size = 0x08000000; + mc->default_ram_id = "taihu_405ep.ram"; } static const TypeInfo taihu_type = { diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index da777ef9c2..4c5e9e4373 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -158,7 +158,6 @@ static void main_cpu_reset(void *opaque) static void bamboo_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -203,10 +202,8 @@ static void bamboo_init(MachineState *machine) /* SDRAM controller */ memset(ram_bases, 0, sizeof(ram_bases)); memset(ram_sizes, 0, sizeof(ram_sizes)); - ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS, - ram_memories, - ram_bases, ram_sizes, - ppc440ep_sdram_bank_sizes); + ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, + ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, ram_bases, ram_sizes, 1); @@ -268,7 +265,7 @@ static void bamboo_init(MachineState *machine) /* Load initrd. */ if (initrd_filename) { initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, - ram_size - RAMDISK_ADDR); + machine->ram_size - RAMDISK_ADDR); if (initrd_size < 0) { error_report("could not load ram disk '%s' at %x", @@ -279,7 +276,7 @@ static void bamboo_init(MachineState *machine) /* If we're loading a kernel directly, we must load the device tree too. */ if (kernel_filename) { - if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR, + if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, initrd_size, kernel_cmdline) < 0) { error_report("couldn't load device tree"); exit(1); @@ -292,6 +289,7 @@ static void bamboo_machine_init(MachineClass *mc) mc->desc = "bamboo"; mc->init = bamboo_init; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb"); + mc->default_ram_id = "ppc4xx.sdram"; } DEFINE_MACHINE("bamboo", bamboo_machine_init) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 1a6a8fac22..d5ea962249 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -909,8 +909,10 @@ static void dcr_write_dma(void *opaque, int dcrn, uint32_t val) sidx = didx = 0; width = 1 << ((val & DMA0_CR_PW) >> 25); - rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, 0); - wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, 1); + rptr = cpu_physical_memory_map(dma->ch[chnl].sa, &rlen, + false); + wptr = cpu_physical_memory_map(dma->ch[chnl].da, &wlen, + true); if (rptr && wptr) { if (!(val & DMA0_CR_DEC) && val & DMA0_CR_SAI && val & DMA0_CR_DAI) { diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index c2e50138aa..3376c43ff5 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -666,21 +666,22 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, sdram_map_bcr(sdram); } -/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory. +/* + * Split RAM between SDRAM banks. * - * sdram_bank_sizes[] must be 0-terminated. + * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] + * and must be 0-terminated. * * The 4xx SDRAM controller supports a small number of banks, and each bank * must be one of a small set of sizes. The number of banks and the supported - * sizes varies by SoC. */ -ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, - MemoryRegion ram_memories[], - hwaddr ram_bases[], - hwaddr ram_sizes[], - const ram_addr_t sdram_bank_sizes[]) + * sizes varies by SoC. + */ +void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, + MemoryRegion ram_memories[], + hwaddr ram_bases[], hwaddr ram_sizes[], + const ram_addr_t sdram_bank_sizes[]) { - MemoryRegion *ram = g_malloc0(sizeof(*ram)); - ram_addr_t size_left = ram_size; + ram_addr_t size_left = memory_region_size(ram); ram_addr_t base = 0; ram_addr_t bank_size; int i; @@ -690,7 +691,16 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, for (j = 0; sdram_bank_sizes[j] != 0; j++) { bank_size = sdram_bank_sizes[j]; if (bank_size <= size_left) { + char name[32]; + + ram_bases[i] = base; + ram_sizes[i] = bank_size; + base += bank_size; size_left -= bank_size; + snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); + memory_region_init_alias(&ram_memories[i], NULL, name, ram, + ram_bases[i], ram_sizes[i]); + break; } } if (!size_left) { @@ -699,34 +709,23 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, } } - ram_size -= size_left; if (size_left) { - error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM" - " controller limits", ram_size / MiB); - } + ram_addr_t used_size = memory_region_size(ram) - size_left; + GString *s = g_string_new(NULL); - memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size); - - size_left = ram_size; - for (i = 0; i < nr_banks && size_left; i++) { - for (j = 0; sdram_bank_sizes[j] != 0; j++) { - bank_size = sdram_bank_sizes[j]; - - if (bank_size <= size_left) { - char name[32]; - snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); - memory_region_init_alias(&ram_memories[i], NULL, name, ram, - base, bank_size); - ram_bases[i] = base; - ram_sizes[i] = bank_size; - base += bank_size; - size_left -= bank_size; - break; - } + for (i = 0; sdram_bank_sizes[i]; i++) { + g_string_append_printf(s, "%" PRIi64 "%s", + sdram_bank_sizes[i] / MiB, + sdram_bank_sizes[i + 1] ? " ," : ""); } - } + error_report("Max %d banks of %s MB DIMM/bank supported", + nr_banks, s->str); + error_report("Possible valid RAM size: %" PRIi64, + used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); - return ram_size; + g_string_free(s, true); + exit(EXIT_FAILURE); + } } /*****************************************************************************/ diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 89bc70eb94..898453cf30 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -324,9 +324,8 @@ static void sam460ex_init(MachineState *machine) /* SDRAM controller */ /* put all RAM on first bank because board has one slot * and firmware only checks that */ - machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1, - ram_memories, ram_bases, ram_sizes, - ppc460ex_sdram_bank_sizes); + ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes, + ppc460ex_sdram_bank_sizes); /* FIXME: does 460EX have ECC interrupts? */ ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories, @@ -485,6 +484,7 @@ static void sam460ex_machine_init(MachineClass *mc) mc->init = sam460ex_init; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb"); mc->default_ram_size = 512 * MiB; + mc->default_ram_id = "ppc4xx.sdram"; } DEFINE_MACHINE("sam460ex", sam460ex_machine_init) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 828e2cc135..c03ce6afb9 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -2652,7 +2652,6 @@ static void spapr_machine_init(MachineState *machine) PCIHostState *phb; int i; MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); hwaddr node0_size = spapr_node0_size(machine); long load_limit, fw_size; char *filename; @@ -2831,10 +2830,8 @@ static void spapr_machine_init(MachineState *machine) kvmppc_enable_h_page_init(); } - /* allocate RAM */ - memory_region_allocate_system_memory(ram, NULL, "ppc_spapr.ram", - machine->ram_size); - memory_region_add_subregion(sysmem, 0, ram); + /* map RAM */ + memory_region_add_subregion(sysmem, 0, machine->ram); /* always allocate the device memory information */ machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); @@ -4473,6 +4470,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data) mc->no_parallel = 1; mc->default_boot_order = ""; mc->default_ram_size = 512 * MiB; + mc->default_ram_id = "ppc_spapr.ram"; mc->default_display = "std"; mc->kvm_type = spapr_kvm_type; machine_class_allow_dynamic_sysbus_dev(mc, TYPE_SPAPR_PCI_HOST_BRIDGE); diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 6db3dbde9c..934eb12d27 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -832,7 +832,7 @@ static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, if (!is_ram_address(spapr, dst) || (dst & ~TARGET_PAGE_MASK) != 0) { return H_PARAMETER; } - pdst = cpu_physical_memory_map(dst, &len, 1); + pdst = cpu_physical_memory_map(dst, &len, true); if (!pdst || len != TARGET_PAGE_SIZE) { return H_PARAMETER; } @@ -843,7 +843,7 @@ static target_ulong h_page_init(PowerPCCPU *cpu, SpaprMachineState *spapr, ret = H_PARAMETER; goto unmap_out; } - psrc = cpu_physical_memory_map(src, &len, 0); + psrc = cpu_physical_memory_map(src, &len, false); if (!psrc || len != TARGET_PAGE_SIZE) { ret = H_PARAMETER; goto unmap_out; diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index 4eef70069f..0dacfcd236 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -194,7 +194,6 @@ static int xilinx_load_device_tree(hwaddr addr, static void virtex_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; hwaddr initrd_base = 0; @@ -205,7 +204,6 @@ static void virtex_init(MachineState *machine) CPUPPCState *env; hwaddr ram_base = 0; DriveInfo *dinfo; - MemoryRegion *phys_ram = g_new(MemoryRegion, 1); qemu_irq irq[32], *cpu_irq; int kernel_size; int i; @@ -222,8 +220,7 @@ static void virtex_init(MachineState *machine) qemu_register_reset(main_cpu_reset, cpu); - memory_region_allocate_system_memory(phys_ram, NULL, "ram", ram_size); - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); + memory_region_add_subregion(address_space_mem, ram_base, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE, @@ -266,7 +263,7 @@ static void virtex_init(MachineState *machine) /* If we failed loading ELF's try a raw image. */ kernel_size = load_image_targphys(kernel_filename, boot_offset, - ram_size); + machine->ram_size); boot_info.bootstrap_pc = boot_offset; high = boot_info.bootstrap_pc + kernel_size + 8192; } @@ -277,7 +274,7 @@ static void virtex_init(MachineState *machine) if (machine->initrd_filename) { initrd_base = high = ROUND_UP(high, 4); initrd_size = load_image_targphys(machine->initrd_filename, - high, ram_size - high); + high, machine->ram_size - high); if (initrd_size < 0) { error_report("couldn't load ram disk '%s'", @@ -291,7 +288,7 @@ static void virtex_init(MachineState *machine) boot_info.fdt = high + (8192 * 2); boot_info.fdt &= ~8191; - xilinx_load_device_tree(boot_info.fdt, ram_size, + xilinx_load_device_tree(boot_info.fdt, machine->ram_size, initrd_base, initrd_size, kernel_cmdline); } @@ -303,6 +300,7 @@ static void virtex_machine_init(MachineClass *mc) mc->desc = "Xilinx Virtex ML507 reference design"; mc->init = virtex_init; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440-xilinx"); + mc->default_ram_id = "ram"; } DEFINE_MACHINE("virtex-ml507", virtex_machine_init) diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 844caab408..5d8e08667e 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -874,18 +874,18 @@ static inline int ida_read_next_idaw(CcwDataStream *cds) if (idaw_addr & 0x07 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { return -EINVAL; /* channel program check */ } - ret = address_space_rw(&address_space_memory, idaw_addr, - MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt2, - sizeof(idaw.fmt2), false); + ret = address_space_read(&address_space_memory, idaw_addr, + MEMTXATTRS_UNSPECIFIED, &idaw.fmt2, + sizeof(idaw.fmt2)); cds->cda = be64_to_cpu(idaw.fmt2); } else { idaw_addr = cds->cda_orig + sizeof(idaw.fmt1) * cds->at_idaw; if (idaw_addr & 0x03 || !cds_ccw_addrs_ok(idaw_addr, 0, ccw_fmt1)) { return -EINVAL; /* channel program check */ } - ret = address_space_rw(&address_space_memory, idaw_addr, - MEMTXATTRS_UNSPECIFIED, (void *) &idaw.fmt1, - sizeof(idaw.fmt1), false); + ret = address_space_read(&address_space_memory, idaw_addr, + MEMTXATTRS_UNSPECIFIED, &idaw.fmt1, + sizeof(idaw.fmt1)); cds->cda = be64_to_cpu(idaw.fmt1); if (cds->cda & 0x80000000) { return -EINVAL; /* channel program check */ diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index 7773499d7f..0817874b48 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -626,7 +626,7 @@ static void s390_ipl_prepare_qipl(S390CPU *cpu) uint8_t *addr; uint64_t len = 4096; - addr = cpu_physical_memory_map(cpu->env.psa, &len, 1); + addr = cpu_physical_memory_map(cpu->env.psa, &len, true); if (!addr || len < QIPL_ADDRESS + sizeof(QemuIplParameters)) { error_report("Cannot set QEMU IPL parameters"); return; diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 7c6a2b3c63..ed8be124da 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -641,7 +641,7 @@ static uint8_t set_ind_atomic(uint64_t ind_loc, uint8_t to_be_set) hwaddr len = 1; uint8_t *ind_addr; - ind_addr = cpu_physical_memory_map(ind_loc, &len, 1); + ind_addr = cpu_physical_memory_map(ind_loc, &len, true); if (!ind_addr) { s390_pci_generate_error_event(ERR_EVENT_AIRERR, 0, 0, 0, 0); return -1; diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index e759eb5f83..a89cf4c129 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -154,14 +154,12 @@ static void virtio_ccw_register_hcalls(void) virtio_ccw_hcall_early_printk); } -static void s390_memory_init(ram_addr_t mem_size) +static void s390_memory_init(MemoryRegion *ram) { MemoryRegion *sysmem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); Error *local_err = NULL; /* allocate RAM for core */ - memory_region_allocate_system_memory(ram, NULL, "s390.ram", mem_size); memory_region_add_subregion(sysmem, 0, ram); /* @@ -245,7 +243,7 @@ static void ccw_init(MachineState *machine) s390_sclp_init(); /* init memory + setup max page size. Required for the CPU model */ - s390_memory_init(machine->ram_size); + s390_memory_init(machine->ram); /* init CPUs (incl. CPU model) early so s390_has_feature() works */ s390_init_cpus(machine); @@ -471,6 +469,7 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data) hc->plug = s390_machine_device_plug; hc->unplug_request = s390_machine_device_unplug_request; nc->nmi_monitor_handler = s390_nmi; + mc->default_ram_id = "s390.ram"; } static inline bool machine_get_aes_key_wrap(Object *obj, Error **errp) diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 13f57e7b67..50cf95b781 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -790,7 +790,7 @@ static uint8_t virtio_set_ind_atomic(SubchDev *sch, uint64_t ind_loc, hwaddr len = 1; uint8_t *ind_addr; - ind_addr = cpu_physical_memory_map(ind_loc, &len, 1); + ind_addr = cpu_physical_memory_map(ind_loc, &len, true); if (!ind_addr) { error_report("%s(%x.%x.%04x): unable to access indicator", __func__, sch->cssid, sch->ssid, sch->schid); diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index e4ee2e6643..c91352cf46 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -404,8 +404,7 @@ pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCmpDesc *cmp_desc) cmp_descr_pa = pvscsi_ring_pop_cmp_descr(&s->rings); trace_pvscsi_cmp_ring_put(cmp_descr_pa); - cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc, - sizeof(*cmp_desc)); + cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc)); } static void @@ -415,8 +414,7 @@ pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMsgDesc *msg_desc) msg_descr_pa = pvscsi_ring_pop_msg_descr(&s->rings); trace_pvscsi_msg_ring_put(msg_descr_pa); - cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc, - sizeof(*msg_desc)); + cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc)); } static void @@ -491,7 +489,7 @@ pvscsi_get_next_sg_elem(PVSCSISGState *sg) { struct PVSCSISGElement elem; - cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem)); + cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem)); if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) != 0) { /* * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 69dc3e6b90..de63ffb037 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -701,8 +701,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) hwaddr entry_addr = (hwaddr)s->admasysaddr; switch (SDHC_DMA_TYPE(s->hostctl1)) { case SDHC_CTRL_ADMA2_32: - dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, - sizeof(adma2)); + dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2)); adma2 = le64_to_cpu(adma2); /* The spec does not specify endianness of descriptor table. * We currently assume that it is LE. @@ -713,8 +712,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) dscr->incr = 8; break; case SDHC_CTRL_ADMA1_32: - dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma1, - sizeof(adma1)); + dma_memory_read(s->dma_as, entry_addr, &adma1, sizeof(adma1)); adma1 = le32_to_cpu(adma1); dscr->addr = (hwaddr)(adma1 & 0xFFFFF000); dscr->attr = (uint8_t)extract32(adma1, 0, 7); @@ -726,13 +724,10 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) } break; case SDHC_CTRL_ADMA2_64: - dma_memory_read(s->dma_as, entry_addr, - (uint8_t *)(&dscr->attr), 1); - dma_memory_read(s->dma_as, entry_addr + 2, - (uint8_t *)(&dscr->length), 2); + dma_memory_read(s->dma_as, entry_addr, &dscr->attr, 1); + dma_memory_read(s->dma_as, entry_addr + 2, &dscr->length, 2); dscr->length = le16_to_cpu(dscr->length); - dma_memory_read(s->dma_as, entry_addr + 4, - (uint8_t *)(&dscr->addr), 8); + dma_memory_read(s->dma_as, entry_addr + 4, &dscr->addr, 8); dscr->addr = le64_to_cpu(dscr->addr); dscr->attr &= (uint8_t) ~0xC0; dscr->incr = 12; diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index f5a087dd86..5fa58aa55f 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -189,7 +189,6 @@ static void leon3_generic_hw_init(MachineState *machine) SPARCCPU *cpu; CPUSPARCState *env; MemoryRegion *address_space_mem = get_system_memory(); - MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *prom = g_new(MemoryRegion, 1); int ret; char *filename; @@ -251,8 +250,8 @@ static void leon3_generic_hw_init(MachineState *machine) exit(1); } - memory_region_allocate_system_memory(ram, NULL, "leon3.ram", ram_size); - memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, ram); + memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET, + machine->ram); /* Allocate BIOS */ prom_size = 8 * MiB; @@ -358,6 +357,7 @@ static void leon3_generic_machine_init(MachineClass *mc) mc->desc = "Leon-3 generic"; mc->init = leon3_generic_hw_init; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3"); + mc->default_ram_id = "leon3.ram"; } DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 25e96db5ca..f5bf95fc9f 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -777,63 +777,42 @@ static const TypeInfo prom_info = { typedef struct RamDevice { SysBusDevice parent_obj; - - MemoryRegion ram; - uint64_t size; + HostMemoryBackend *memdev; } RamDevice; /* System RAM */ static void ram_realize(DeviceState *dev, Error **errp) { RamDevice *d = SUN4M_RAM(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); - memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", - d->size); - sysbus_init_mmio(sbd, &d->ram); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); } -static void ram_init(hwaddr addr, ram_addr_t RAM_size, - uint64_t max_mem) +static void ram_initfn(Object *obj) { - DeviceState *dev; - SysBusDevice *s; - RamDevice *d; - - /* allocate RAM */ - if ((uint64_t)RAM_size > max_mem) { - error_report("Too much memory for this machine: %" PRId64 "," - " maximum %" PRId64, - RAM_size / MiB, max_mem / MiB); - exit(1); - } - dev = qdev_create(NULL, "memory"); - s = SYS_BUS_DEVICE(dev); - - d = SUN4M_RAM(dev); - d->size = RAM_size; - qdev_init_nofail(dev); - - sysbus_mmio_map(s, 0, addr); + RamDevice *d = SUN4M_RAM(obj); + object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, + (Object **)&d->memdev, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG, &error_abort); + object_property_set_description(obj, "memdev", "Set RAM backend" + "Valid value is ID of a hostmem backend", + &error_abort); } -static Property ram_properties[] = { - DEFINE_PROP_UINT64("size", RamDevice, size, 0), - DEFINE_PROP_END_OF_LIST(), -}; - static void ram_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = ram_realize; - device_class_set_props(dc, ram_properties); } static const TypeInfo ram_info = { .name = TYPE_SUN4M_MEMORY, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(RamDevice), + .instance_init = ram_initfn, .class_init = ram_class_init, }; @@ -879,6 +858,15 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, SysBusDevice *s; unsigned int smp_cpus = machine->smp.cpus; unsigned int max_cpus = machine->smp.max_cpus; + Object *ram_memdev = object_resolve_path_type(machine->ram_memdev_id, + TYPE_MEMORY_BACKEND, NULL); + + if (machine->ram_size > hwdef->max_mem) { + error_report("Too much memory for this machine: %" PRId64 "," + " maximum %" PRId64, + machine->ram_size / MiB, hwdef->max_mem / MiB); + exit(1); + } /* init CPUs */ for(i = 0; i < smp_cpus; i++) { @@ -888,9 +876,12 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, for (i = smp_cpus; i < MAX_CPUS; i++) cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); + /* Create and map RAM frontend */ + dev = qdev_create(NULL, "memory"); + object_property_set_link(OBJECT(dev), ram_memdev, "memdev", &error_fatal); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); - /* set up devices */ - ram_init(0, machine->ram_size, hwdef->max_mem); /* models without ECC don't trap when missing ram is accessed */ if (!hwdef->ecc_base) { empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); @@ -1078,7 +1069,7 @@ static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); - fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); @@ -1415,6 +1406,7 @@ static void ss5_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss5_type = { @@ -1434,6 +1426,7 @@ static void ss10_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss10_type = { @@ -1453,6 +1446,7 @@ static void ss600mp_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss600mp_type = { @@ -1472,6 +1466,7 @@ static void ss20_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss20_type = { @@ -1490,6 +1485,7 @@ static void voyager_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo voyager_type = { @@ -1508,6 +1504,7 @@ static void ss_lx_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss_lx_type = { @@ -1526,6 +1523,7 @@ static void ss4_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo ss4_type = { @@ -1544,6 +1542,7 @@ static void scls_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo scls_type = { @@ -1562,6 +1561,7 @@ static void sbook_class_init(ObjectClass *oc, void *data) mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); mc->default_display = "tcx"; + mc->default_ram_id = "sun4m.ram"; } static const TypeInfo sbook_type = { diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c index 5eb2d097b9..ab5ef8c5b3 100644 --- a/hw/sparc64/niagara.c +++ b/hw/sparc64/niagara.c @@ -40,7 +40,6 @@ typedef struct NiagaraBoardState { MemoryRegion hv_ram; - MemoryRegion partition_ram; MemoryRegion nvram; MemoryRegion md_rom; MemoryRegion hv_rom; @@ -111,11 +110,8 @@ static void niagara_init(MachineState *machine) NIAGARA_HV_RAM_SIZE, &error_fatal); memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram); - memory_region_allocate_system_memory(&s->partition_ram, NULL, - "sun4v-partition.ram", - machine->ram_size); memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE, - &s->partition_ram); + machine->ram); memory_region_init_ram(&s->nvram, NULL, "sun4v.nvram", NIAGARA_NVRAM_SIZE, &error_fatal); @@ -173,6 +169,7 @@ static void niagara_class_init(ObjectClass *oc, void *data) mc->max_cpus = 1; /* XXX for now */ mc->default_boot_order = "c"; mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1"); + mc->default_ram_id = "sun4v-partition.ram"; } static const TypeInfo niagara_type = { diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 9edfadc81d..0d226dae10 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -294,7 +294,7 @@ static int vhost_dev_has_iommu(struct vhost_dev *dev) } static void *vhost_memory_map(struct vhost_dev *dev, hwaddr addr, - hwaddr *plen, int is_write) + hwaddr *plen, bool is_write) { if (!vhost_dev_has_iommu(dev)) { return cpu_physical_memory_map(addr, plen, is_write); @@ -1012,21 +1012,21 @@ static int vhost_virtqueue_start(struct vhost_dev *dev, vq->desc_size = s = l = virtio_queue_get_desc_size(vdev, idx); vq->desc_phys = a; - vq->desc = vhost_memory_map(dev, a, &l, 0); + vq->desc = vhost_memory_map(dev, a, &l, false); if (!vq->desc || l != s) { r = -ENOMEM; goto fail_alloc_desc; } vq->avail_size = s = l = virtio_queue_get_avail_size(vdev, idx); vq->avail_phys = a = virtio_queue_get_avail_addr(vdev, idx); - vq->avail = vhost_memory_map(dev, a, &l, 0); + vq->avail = vhost_memory_map(dev, a, &l, false); if (!vq->avail || l != s) { r = -ENOMEM; goto fail_alloc_avail; } vq->used_size = s = l = virtio_queue_get_used_size(vdev, idx); vq->used_phys = a = virtio_queue_get_used_addr(vdev, idx); - vq->used = vhost_memory_map(dev, a, &l, 1); + vq->used = vhost_memory_map(dev, a, &l, true); if (!vq->used || l != s) { r = -ENOMEM; goto fail_alloc_used; diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 00d444699d..b2d415e5dd 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -1358,7 +1358,7 @@ static void virtqueue_undo_map_desc(unsigned int out_num, unsigned int in_num, static void virtqueue_map_iovec(VirtIODevice *vdev, struct iovec *sg, hwaddr *addr, unsigned int num_sg, - int is_write) + bool is_write) { unsigned int i; hwaddr len; @@ -1382,8 +1382,9 @@ static void virtqueue_map_iovec(VirtIODevice *vdev, struct iovec *sg, void virtqueue_map(VirtIODevice *vdev, VirtQueueElement *elem) { - virtqueue_map_iovec(vdev, elem->in_sg, elem->in_addr, elem->in_num, 1); - virtqueue_map_iovec(vdev, elem->out_sg, elem->out_addr, elem->out_num, 0); + virtqueue_map_iovec(vdev, elem->in_sg, elem->in_addr, elem->in_num, true); + virtqueue_map_iovec(vdev, elem->out_sg, elem->out_addr, elem->out_num, + false); } static void *virtqueue_alloc_element(size_t sz, unsigned out_num, unsigned in_num) diff --git a/hw/xen/xen_pt_graphics.c b/hw/xen/xen_pt_graphics.c index b69732729b..a3bc7e3921 100644 --- a/hw/xen/xen_pt_graphics.c +++ b/hw/xen/xen_pt_graphics.c @@ -222,7 +222,7 @@ void xen_pt_setup_vga(XenPCIPassthroughState *s, XenHostPCIDevice *dev, } /* Currently we fixed this address as a primary for legacy BIOS. */ - cpu_physical_memory_rw(0xc0000, bios, bios_size, 1); + cpu_physical_memory_write(0xc0000, bios, bios_size); } uint32_t igd_read_opregion(XenPCIPassthroughState *s) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index e96781a455..49384bb66a 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -388,7 +388,7 @@ void dump_opcount_info(void); #endif /* !CONFIG_USER_ONLY */ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - uint8_t *buf, target_ulong len, int is_write); + void *ptr, target_ulong len, bool is_write); int cpu_exec(CPUState *cpu); diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 81753bbb34..b47e5630e7 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -69,23 +69,23 @@ void qemu_ram_unset_migratable(RAMBlock *rb); size_t qemu_ram_pagesize(RAMBlock *block); size_t qemu_ram_pagesize_largest(void); -void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf, - hwaddr len, int is_write); +void cpu_physical_memory_rw(hwaddr addr, void *buf, + hwaddr len, bool is_write); static inline void cpu_physical_memory_read(hwaddr addr, void *buf, hwaddr len) { - cpu_physical_memory_rw(addr, buf, len, 0); + cpu_physical_memory_rw(addr, buf, len, false); } static inline void cpu_physical_memory_write(hwaddr addr, const void *buf, hwaddr len) { - cpu_physical_memory_rw(addr, (void *)buf, len, 1); + cpu_physical_memory_rw(addr, (void *)buf, len, true); } void *cpu_physical_memory_map(hwaddr addr, hwaddr *plen, - int is_write); + bool is_write); void cpu_physical_memory_unmap(void *buffer, hwaddr len, - int is_write, hwaddr access_len); + bool is_write, hwaddr access_len); void cpu_register_map_client(QEMUBH *bh); void cpu_unregister_map_client(QEMUBH *bh); diff --git a/include/exec/memory.h b/include/exec/memory.h index e85b7de99a..1614d9a02c 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2052,7 +2052,7 @@ void address_space_remove_listeners(AddressSpace *as); * @is_write: indicates the transfer direction */ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, + MemTxAttrs attrs, void *buf, hwaddr len, bool is_write); /** @@ -2070,7 +2070,7 @@ MemTxResult address_space_rw(AddressSpace *as, hwaddr addr, */ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len); + const void *buf, hwaddr len); /** * address_space_write_rom: write to address space, including ROM. @@ -2096,7 +2096,7 @@ MemTxResult address_space_write(AddressSpace *as, hwaddr addr, */ MemTxResult address_space_write_rom(AddressSpace *as, hwaddr addr, MemTxAttrs attrs, - const uint8_t *buf, hwaddr len); + const void *buf, hwaddr len); /* address_space_ld*: load from an address space * address_space_st*: store to an address space @@ -2329,14 +2329,14 @@ void *address_space_map(AddressSpace *as, hwaddr addr, * @is_write: indicates the transfer direction */ void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len, - int is_write, hwaddr access_len); + bool is_write, hwaddr access_len); /* Internal functions, part of the implementation of address_space_read. */ MemTxResult address_space_read_full(AddressSpace *as, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, hwaddr len); + MemTxAttrs attrs, void *buf, hwaddr len); MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, + MemTxAttrs attrs, void *buf, hwaddr len, hwaddr addr1, hwaddr l, MemoryRegion *mr); void *qemu_map_ram_ptr(RAMBlock *ram_block, ram_addr_t addr); @@ -2374,7 +2374,7 @@ static inline bool memory_access_is_direct(MemoryRegion *mr, bool is_write) */ static inline __attribute__((__always_inline__)) MemTxResult address_space_read(AddressSpace *as, hwaddr addr, - MemTxAttrs attrs, uint8_t *buf, + MemTxAttrs attrs, void *buf, hwaddr len) { MemTxResult result = MEMTX_OK; @@ -2433,7 +2433,7 @@ address_space_read_cached(MemoryRegionCache *cache, hwaddr addr, */ static inline void address_space_write_cached(MemoryRegionCache *cache, hwaddr addr, - void *buf, hwaddr len) + const void *buf, hwaddr len) { assert(addr < cache->len && len <= cache->len - addr); if (likely(cache->ptr)) { diff --git a/include/hw/boards.h b/include/hw/boards.h index fb1b43d5b9..142b86d0ae 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -4,6 +4,7 @@ #define HW_BOARDS_H #include "exec/memory.h" +#include "sysemu/hostmem.h" #include "sysemu/blockdev.h" #include "sysemu/accel.h" #include "qapi/qapi-types-machine.h" @@ -11,38 +12,6 @@ #include "qom/object.h" #include "hw/core/cpu.h" -/** - * memory_region_allocate_system_memory - Allocate a board's main memory - * @mr: the #MemoryRegion to be initialized - * @owner: the object that tracks the region's reference count - * @name: name of the memory region - * @ram_size: size of the region in bytes - * - * This function allocates the main memory for a board model, and - * initializes @mr appropriately. It also arranges for the memory - * to be migrated (by calling vmstate_register_ram_global()). - * - * Memory allocated via this function will be backed with the memory - * backend the user provided using "-mem-path" or "-numa node,memdev=..." - * if appropriate; this is typically used to cause host huge pages to be - * used. This function should therefore be called by a board exactly once, - * for the primary or largest RAM area it implements. - * - * For boards where the major RAM is split into two parts in the memory - * map, you can deal with this by calling memory_region_allocate_system_memory() - * once to get a MemoryRegion with enough RAM for both parts, and then - * creating alias MemoryRegions via memory_region_init_alias() which - * alias into different parts of the RAM MemoryRegion and can be mapped - * into the memory map in the appropriate places. - * - * Smaller pieces of memory (display RAM, static RAMs, etc) don't need - * to be backed via the -mem-path memory backend and can simply - * be created via memory_region_init_ram(). - */ -void memory_region_allocate_system_memory(MemoryRegion *mr, Object *owner, - const char *name, - uint64_t ram_size); - #define TYPE_MACHINE_SUFFIX "-machine" /* Machine class name that needs to be used for class-name-based machine @@ -72,7 +41,12 @@ void machine_set_cpu_numa_node(MachineState *machine, Error **errp); void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *type); - +/* + * Checks that backend isn't used, preps it for exclusive usage and + * returns migratable MemoryRegion provided by backend. + */ +MemoryRegion *machine_consume_memdev(MachineState *machine, + HostMemoryBackend *backend); /** * CPUArchId: @@ -169,6 +143,13 @@ typedef struct { * false is returned, an error must be set to show the reason of * the rejection. If the hook is not provided, all hotplug will be * allowed. + * @default_ram_id: + * Specifies inital RAM MemoryRegion name to be used for default backend + * creation if user explicitly hasn't specified backend with "memory-backend" + * property. + * It also will be used as a way to optin into "-m" option support. + * If it's not set by board, '-m' will be ignored and generic code will + * not create default RAM MemoryRegion. */ struct MachineClass { /*< private >*/ @@ -225,6 +206,7 @@ struct MachineClass { bool nvdimm_supported; bool numa_mem_supported; bool auto_enable_numa; + const char *default_ram_id; HotplugHandler *(*get_hotplug_handler)(MachineState *machine, DeviceState *dev); @@ -285,6 +267,12 @@ struct MachineState { bool enforce_config_section; bool enable_graphics; char *memory_encryption; + char *ram_memdev_id; + /* + * convenience alias to ram_memdev_id backend memory region + * or to numa container memory region + */ + MemoryRegion *ram; DeviceMemoryState *device_memory; ram_addr_t ram_size; diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h index 52ec197da0..1bc1fc73e5 100644 --- a/include/hw/ide/internal.h +++ b/include/hw/ide/internal.h @@ -322,11 +322,10 @@ typedef void EndTransferFunc(IDEState *); typedef void DMAStartFunc(IDEDMA *, IDEState *, BlockCompletionFunc *); typedef void DMAVoidFunc(IDEDMA *); -typedef int DMAIntFunc(IDEDMA *, int); +typedef int DMAIntFunc(IDEDMA *, bool); typedef int32_t DMAInt32Func(IDEDMA *, int32_t len); typedef void DMAu32Func(IDEDMA *, uint32_t); typedef void DMAStopFunc(IDEDMA *, bool); -typedef void DMARestartFunc(void *, int, RunState); struct unreported_events { bool eject_request; diff --git a/include/hw/misc/aspeed_sdmc.h b/include/hw/misc/aspeed_sdmc.h index 5dbde59fe7..cea1e67fe3 100644 --- a/include/hw/misc/aspeed_sdmc.h +++ b/include/hw/misc/aspeed_sdmc.h @@ -40,6 +40,7 @@ typedef struct AspeedSDMCClass { SysBusDeviceClass parent_class; uint64_t max_ram_size; + const uint64_t *valid_ram_sizes; uint32_t (*compute_conf)(AspeedSDMCState *s, uint32_t data); void (*write)(AspeedSDMCState *s, uint32_t reg, uint32_t data); } AspeedSDMCClass; diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 7d82259051..cc19c8da5b 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -42,11 +42,10 @@ enum { qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); -ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, - MemoryRegion ram_memories[], - hwaddr ram_bases[], - hwaddr ram_sizes[], - const ram_addr_t sdram_bank_sizes[]); +void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, + MemoryRegion ram_memories[], + hwaddr ram_bases[], hwaddr ram_sizes[], + const ram_addr_t sdram_bank_sizes[]); void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion ram_memories[], diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 02c1ce6a5d..f55ce8b320 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -302,6 +302,44 @@ static inline uint32_t extract32(uint32_t value, int start, int length) } /** + * extract8: + * @value: the value to extract the bit field from + * @start: the lowest bit in the bit field (numbered from 0) + * @length: the length of the bit field + * + * Extract from the 8 bit input @value the bit field specified by the + * @start and @length parameters, and return it. The bit field must + * lie entirely within the 8 bit word. It is valid to request that + * all 8 bits are returned (ie @length 8 and @start 0). + * + * Returns: the value of the bit field extracted from the input value. + */ +static inline uint8_t extract8(uint8_t value, int start, int length) +{ + assert(start >= 0 && length > 0 && length <= 8 - start); + return extract32(value, start, length); +} + +/** + * extract16: + * @value: the value to extract the bit field from + * @start: the lowest bit in the bit field (numbered from 0) + * @length: the length of the bit field + * + * Extract from the 16 bit input @value the bit field specified by the + * @start and @length parameters, and return it. The bit field must + * lie entirely within the 16 bit word. It is valid to request that + * all 16 bits are returned (ie @length 16 and @start 0). + * + * Returns: the value of the bit field extracted from the input value. + */ +static inline uint16_t extract16(uint16_t value, int start, int length) +{ + assert(start >= 0 && length > 0 && length <= 16 - start); + return extract32(value, start, length); +} + +/** * extract64: * @value: the value to extract the bit field from * @start: the lowest bit in the bit field (numbered from 0) diff --git a/include/sysemu/hostmem.h b/include/sysemu/hostmem.h index 4dbdadd39e..8276e53683 100644 --- a/include/sysemu/hostmem.h +++ b/include/sysemu/hostmem.h @@ -27,6 +27,22 @@ #define MEMORY_BACKEND_CLASS(klass) \ OBJECT_CLASS_CHECK(HostMemoryBackendClass, (klass), TYPE_MEMORY_BACKEND) +/* hostmem-ram.c */ +/** + * @TYPE_MEMORY_BACKEND_RAM: + * name of backend that uses mmap on the anonymous RAM + */ + +#define TYPE_MEMORY_BACKEND_RAM "memory-backend-ram" + +/* hostmem-file.c */ +/** + * @TYPE_MEMORY_BACKEND_FILE: + * name of backend that uses mmap on a file descriptor + */ +#define TYPE_MEMORY_BACKEND_FILE "memory-backend-file" + +typedef struct HostMemoryBackend HostMemoryBackend; typedef struct HostMemoryBackendClass HostMemoryBackendClass; /** @@ -45,6 +61,7 @@ struct HostMemoryBackendClass { * @parent: opaque parent object container * @size: amount of memory backend provides * @mr: MemoryRegion representing host memory belonging to backend + * @prealloc_threads: number of threads to be used for preallocatining RAM */ struct HostMemoryBackend { /* private */ @@ -53,7 +70,8 @@ struct HostMemoryBackend { /* protected */ uint64_t size; bool merge, dump, use_canonical_path; - bool prealloc, force_prealloc, is_mapped, share; + bool prealloc, is_mapped, share; + uint32_t prealloc_threads; DECLARE_BITMAP(host_nodes, MAX_NODES + 1); HostMemPolicy policy; diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h index ba693cc80b..ad58ee88f7 100644 --- a/include/sysemu/numa.h +++ b/include/sysemu/numa.h @@ -112,5 +112,6 @@ void numa_default_auto_assign_ram(MachineClass *mc, NodeInfo *nodes, int nb_nodes, ram_addr_t size); void numa_cpu_pre_plug(const struct CPUArchId *slot, DeviceState *dev, Error **errp); +bool numa_uses_legacy_mem(void); #endif diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index dec64fcc17..479d90bcea 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -50,8 +50,6 @@ extern uint8_t *boot_splash_filedata; extern bool enable_mlock; extern bool enable_cpu_pm; extern QEMUClockType rtc_clock; -extern const char *mem_path; -extern int mem_prealloc; #define MAX_OPTION_ROMS 16 typedef struct QEMUOptionRom { @@ -794,10 +794,19 @@ static void address_space_update_ioeventfds(AddressSpace *as) FlatView *view; FlatRange *fr; unsigned ioeventfd_nb = 0; - MemoryRegionIoeventfd *ioeventfds = NULL; + unsigned ioeventfd_max; + MemoryRegionIoeventfd *ioeventfds; AddrRange tmp; unsigned i; + /* + * It is likely that the number of ioeventfds hasn't changed much, so use + * the previous size as the starting value, with some headroom to avoid + * gratuitous reallocations. + */ + ioeventfd_max = QEMU_ALIGN_UP(as->ioeventfd_nb, 4); + ioeventfds = g_new(MemoryRegionIoeventfd, ioeventfd_max); + view = address_space_get_flatview(as); FOR_EACH_FLAT_RANGE(fr, view) { for (i = 0; i < fr->mr->ioeventfd_nb; ++i) { @@ -806,8 +815,11 @@ static void address_space_update_ioeventfds(AddressSpace *as) int128_make64(fr->offset_in_region))); if (addrrange_intersects(fr->addr, tmp)) { ++ioeventfd_nb; - ioeventfds = g_realloc(ioeventfds, - ioeventfd_nb * sizeof(*ioeventfds)); + if (ioeventfd_nb > ioeventfd_max) { + ioeventfd_max = MAX(ioeventfd_max * 2, 4); + ioeventfds = g_realloc(ioeventfds, + ioeventfd_max * sizeof(*ioeventfds)); + } ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i]; ioeventfds[ioeventfd_nb-1].addr = tmp; } diff --git a/nbd/server.c b/nbd/server.c index 87fcd2e7bf..11a31094ff 100644 --- a/nbd/server.c +++ b/nbd/server.c @@ -2384,15 +2384,23 @@ static coroutine_fn int nbd_handle_request(NBDClient *client, !client->export_meta.bitmap, NBD_META_ID_BASE_ALLOCATION, errp); - } else { /* client->export_meta.bitmap */ + if (ret < 0) { + return ret; + } + } + + if (client->export_meta.bitmap) { ret = nbd_co_send_bitmap(client, request->handle, client->exp->export_bitmap, request->from, request->len, dont_fragment, true, NBD_META_ID_DIRTY_BITMAP, errp); + if (ret < 0) { + return ret; + } } - return ret; + return 0; } else { return nbd_send_generic_reply(client, request->handle, -EINVAL, "CMD_BLOCK_STATUS not negotiated", diff --git a/plugins/core.c b/plugins/core.c index 9e1b9e7a91..ed863011ba 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -286,6 +286,7 @@ static inline uint32_t cb_to_tcg_flags(enum qemu_plugin_cb_flags flags) switch (flags) { case QEMU_PLUGIN_CB_RW_REGS: ret = 0; + break; case QEMU_PLUGIN_CB_R_REGS: ret = TCG_CALL_NO_WG; break; diff --git a/qdev-monitor.c b/qdev-monitor.c index dbbe92dfa1..9833b33549 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -888,6 +888,12 @@ void qmp_device_del(const char *id, Error **errp) { DeviceState *dev = find_device_state(id, errp); if (dev != NULL) { + if (dev->pending_deleted_event) { + error_setg(errp, "Device %s is already in the " + "process of unplug", id); + return; + } + qdev_unplug(dev, errp); } } diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi index 0671c26c80..66eca3a1de 100644 --- a/qemu-deprecated.texi +++ b/qemu-deprecated.texi @@ -113,15 +113,6 @@ QEMU using implicit generic or board specific splitting rule. Use @option{memdev} with @var{memory-backend-ram} backend or @option{mem} (if it's supported by used machine type) to define mapping explictly instead. -@subsection -mem-path fallback to RAM (since 4.1) -Currently if guest RAM allocation from file pointed by @option{mem-path} -fails, QEMU falls back to allocating from RAM, which might result -in unpredictable behavior since the backing file specified by the user -is ignored. In the future, users will be responsible for making sure -the backing storage specified with @option{-mem-path} can actually provide -the guest RAM configured with @option{-m} and QEMU will fail to start up if -RAM allocation is unsuccessful. - @subsection RISC-V -bios (since 4.1) QEMU 4.1 introduced support for the -bios option in QEMU for RISC-V for the @@ -434,23 +434,23 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][5] == 'b') { uint8_t data = value; - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 1, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 1); } else if (words[0][5] == 'w') { uint16_t data = value; tswap16s(&data); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 2, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 2); } else if (words[0][5] == 'l') { uint32_t data = value; tswap32s(&data); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 4, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 4); } else if (words[0][5] == 'q') { uint64_t data = value; tswap64s(&data); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 8, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 8); } qtest_send_prefix(chr); qtest_send(chr, "OK\n"); @@ -468,22 +468,22 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (words[0][4] == 'b') { uint8_t data; - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - &data, 1, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 1); value = data; } else if (words[0][4] == 'w') { uint16_t data; - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 2, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 2); value = tswap16(data); } else if (words[0][4] == 'l') { uint32_t data; - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &data, 4, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &data, 4); value = tswap32(data); } else if (words[0][4] == 'q') { - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *) &value, 8, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + &value, 8); tswap64s(&value); } qtest_send_prefix(chr); @@ -503,8 +503,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(len); data = g_malloc(len); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + len); enc = g_malloc(2 * len + 1); for (i = 0; i < len; i++) { @@ -529,8 +529,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) g_assert(ret == 0); data = g_malloc(len); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, false); + address_space_read(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + len); b64_data = g_base64_encode(data, len); qtest_send_prefix(chr); qtest_sendf(chr, "OK %s\n", b64_data); @@ -564,8 +564,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) data[i] = 0; } } - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + len); g_free(data); qtest_send_prefix(chr); @@ -587,8 +587,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) if (len) { data = g_malloc(len); memset(data, pattern, len); - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, + data, len); g_free(data); } @@ -621,8 +621,8 @@ static void qtest_process_command(CharBackend *chr, gchar **words) out_len = MIN(out_len, len); } - address_space_rw(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, - data, len, true); + address_space_write(first_cpu->as, addr, MEMTXATTRS_UNSPECIFIED, data, + len); qtest_send_prefix(chr); qtest_send(chr, "OK\n"); diff --git a/scripts/coccinelle/exec_rw_const.cocci b/scripts/coccinelle/exec_rw_const.cocci new file mode 100644 index 0000000000..1a20296951 --- /dev/null +++ b/scripts/coccinelle/exec_rw_const.cocci @@ -0,0 +1,111 @@ +/* + Usage: + + spatch \ + --macro-file scripts/cocci-macro-file.h \ + --sp-file scripts/coccinelle/exec_rw_const.cocci \ + --keep-comments \ + --in-place \ + --dir . +*/ + +// Convert to boolean +@@ +expression E1, E2, E3, E4, E5; +@@ +( +- address_space_rw(E1, E2, E3, E4, E5, 0) ++ address_space_rw(E1, E2, E3, E4, E5, false) +| +- address_space_rw(E1, E2, E3, E4, E5, 1) ++ address_space_rw(E1, E2, E3, E4, E5, true) +| + +- cpu_physical_memory_rw(E1, E2, E3, 0) ++ cpu_physical_memory_rw(E1, E2, E3, false) +| +- cpu_physical_memory_rw(E1, E2, E3, 1) ++ cpu_physical_memory_rw(E1, E2, E3, true) +| + +- cpu_physical_memory_map(E1, E2, 0) ++ cpu_physical_memory_map(E1, E2, false) +| +- cpu_physical_memory_map(E1, E2, 1) ++ cpu_physical_memory_map(E1, E2, true) +) + +// Use address_space_write instead of casting to non-const +@@ +type T; +const T *V; +expression E1, E2, E3, E4; +@@ +( +- address_space_rw(E1, E2, E3, (T *)V, E4, 1) ++ address_space_write(E1, E2, E3, V, E4) +| +- address_space_rw(E1, E2, E3, (void *)V, E4, 1) ++ address_space_write(E1, E2, E3, V, E4) +) + +// Avoid uses of address_space_rw() with a constant is_write argument. +@@ +expression E1, E2, E3, E4, E5; +symbol true, false; +@@ +( +- address_space_rw(E1, E2, E3, E4, E5, false) ++ address_space_read(E1, E2, E3, E4, E5) +| +- address_space_rw(E1, E2, E3, E4, E5, true) ++ address_space_write(E1, E2, E3, E4, E5) +) + +// Avoid uses of cpu_physical_memory_rw() with a constant is_write argument. +@@ +expression E1, E2, E3; +@@ +( +- cpu_physical_memory_rw(E1, E2, E3, false) ++ cpu_physical_memory_read(E1, E2, E3) +| +- cpu_physical_memory_rw(E1, E2, E3, true) ++ cpu_physical_memory_write(E1, E2, E3) +) + +// Remove useless cast +@@ +expression E1, E2, E3, E4, E5, E6; +type T; +@@ +( +- address_space_rw(E1, E2, E3, (T *)(E4), E5, E6) ++ address_space_rw(E1, E2, E3, E4, E5, E6) +| +- address_space_read(E1, E2, E3, (T *)(E4), E5) ++ address_space_read(E1, E2, E3, E4, E5) +| +- address_space_write(E1, E2, E3, (T *)(E4), E5) ++ address_space_write(E1, E2, E3, E4, E5) +| +- address_space_write_rom(E1, E2, E3, (T *)(E4), E5) ++ address_space_write_rom(E1, E2, E3, E4, E5) +| + +- cpu_physical_memory_rw(E1, (T *)(E2), E3, E4) ++ cpu_physical_memory_rw(E1, E2, E3, E4) +| +- cpu_physical_memory_read(E1, (T *)(E2), E3) ++ cpu_physical_memory_read(E1, E2, E3) +| +- cpu_physical_memory_write(E1, (T *)(E2), E3) ++ cpu_physical_memory_write(E1, E2, E3) +| + +- dma_memory_read(E1, E2, (T *)(E3), E4) ++ dma_memory_read(E1, E2, E3, E4) +| +- dma_memory_write(E1, E2, (T *)(E3), E4) ++ dma_memory_write(E1, E2, E3, E4) +) diff --git a/scripts/git.orderfile b/scripts/git.orderfile index 1f747b583a..7cf22e0bf5 100644 --- a/scripts/git.orderfile +++ b/scripts/git.orderfile @@ -22,6 +22,9 @@ Makefile* qapi/*.json qga/*.json +# semantic patches +*.cocci + # headers *.h diff --git a/softmmu/vl.c b/softmmu/vl.c index 92c7b3a6e9..16ff5a16a3 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -56,6 +56,7 @@ #include "ui/input.h" #include "sysemu/sysemu.h" #include "sysemu/numa.h" +#include "sysemu/hostmem.h" #include "exec/gdbstub.h" #include "qemu/timer.h" #include "chardev/char.h" @@ -120,8 +121,6 @@ enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB; int display_opengl; const char* keyboard_layout = NULL; ram_addr_t ram_size; -const char *mem_path = NULL; -int mem_prealloc = 0; /* force preallocation of physical target memory */ bool enable_mlock = false; bool enable_cpu_pm = false; int nb_nics; @@ -2559,7 +2558,7 @@ static bool object_create_delayed(const char *type, QemuOpts *opts) } -static void set_memory_options(uint64_t *ram_slots, ram_addr_t *maxram_size, +static bool set_memory_options(uint64_t *ram_slots, ram_addr_t *maxram_size, MachineClass *mc) { uint64_t sz; @@ -2636,6 +2635,7 @@ static void set_memory_options(uint64_t *ram_slots, ram_addr_t *maxram_size, } loc_pop(&loc); + return !!mem_str; } static int global_init_func(void *opaque, QemuOpts *opts, Error **errp) @@ -2786,6 +2786,24 @@ static void configure_accelerators(const char *progname) } } +static void create_default_memdev(MachineState *ms, const char *path) +{ + Object *obj; + MachineClass *mc = MACHINE_GET_CLASS(ms); + + obj = object_new(path ? TYPE_MEMORY_BACKEND_FILE : TYPE_MEMORY_BACKEND_RAM); + if (path) { + object_property_set_str(obj, path, "mem-path", &error_fatal); + } + object_property_set_int(obj, ms->ram_size, "size", &error_fatal); + object_property_add_child(object_get_objects_root(), mc->default_ram_id, + obj, &error_fatal); + user_creatable_complete(USER_CREATABLE(obj), &error_fatal); + object_unref(obj); + object_property_set_str(OBJECT(ms), mc->default_ram_id, "memory-backend", + &error_fatal); +} + void qemu_init(int argc, char **argv, char **envp) { int i; @@ -2820,8 +2838,11 @@ void qemu_init(int argc, char **argv, char **envp) Error *err = NULL; bool list_data_dirs = false; char *dir, **dirs; + const char *mem_path = NULL; + bool have_custom_ram_size; BlockdevOptionsQueue bdo_queue = QSIMPLEQ_HEAD_INITIALIZER(bdo_queue); QemuPluginList plugin_list = QTAILQ_HEAD_INITIALIZER(plugin_list); + int mem_prealloc = 0; /* force preallocation of physical target memory */ os_set_line_buffering(); @@ -3779,7 +3800,8 @@ void qemu_init(int argc, char **argv, char **envp) machine_class = select_machine(); object_set_machine_compat_props(machine_class->compat_props); - set_memory_options(&ram_slots, &maxram_size, machine_class); + have_custom_ram_size = set_memory_options(&ram_slots, &maxram_size, + machine_class); os_daemonize(); @@ -3929,6 +3951,15 @@ void qemu_init(int argc, char **argv, char **envp) exit(1); } + if (mem_prealloc) { + char *val; + + val = g_strdup_printf("%d", current_machine->smp.cpus); + object_register_sugar_prop("memory-backend", "prealloc-threads", val); + g_free(val); + object_register_sugar_prop("memory-backend", "prealloc", "on"); + } + /* * Get the default machine options from the machine if it is not already * specified either by the configuration file or by the command line. @@ -4092,9 +4123,6 @@ void qemu_init(int argc, char **argv, char **envp) machine_opts = qemu_get_machine_opts(); qemu_opt_foreach(machine_opts, machine_set_property, current_machine, &error_fatal); - current_machine->ram_size = ram_size; - current_machine->maxram_size = maxram_size; - current_machine->ram_slots = ram_slots; /* * Note: uses machine properties such as kernel-irqchip, must run @@ -4205,14 +4233,6 @@ void qemu_init(int argc, char **argv, char **envp) tpm_init(); - if (!xen_enabled()) { - /* On 32-bit hosts, QEMU is limited by virtual address space */ - if (ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { - error_report("at most 2047 MB RAM can be simulated"); - exit(1); - } - } - blk_mig_init(); ram_mig_init(); dirty_bitmap_mig_init(); @@ -4257,8 +4277,40 @@ void qemu_init(int argc, char **argv, char **envp) if (cpu_option) { current_machine->cpu_type = parse_cpu_option(cpu_option); } + + if (current_machine->ram_memdev_id) { + Object *backend; + ram_addr_t backend_size; + + backend = object_resolve_path_type(current_machine->ram_memdev_id, + TYPE_MEMORY_BACKEND, NULL); + backend_size = object_property_get_uint(backend, "size", &error_abort); + if (have_custom_ram_size && backend_size != ram_size) { + error_report("Size specified by -m option must match size of " + "explicitly specified 'memory-backend' property"); + exit(EXIT_FAILURE); + } + ram_size = backend_size; + } + + if (!xen_enabled()) { + /* On 32-bit hosts, QEMU is limited by virtual address space */ + if (ram_size > (2047 << 20) && HOST_LONG_BITS == 32) { + error_report("at most 2047 MB RAM can be simulated"); + exit(1); + } + } + + current_machine->ram_size = ram_size; + current_machine->maxram_size = maxram_size; + current_machine->ram_slots = ram_slots; + parse_numa_opts(current_machine); + if (machine_class->default_ram_id && current_machine->ram_size && + numa_uses_legacy_mem() && !current_machine->ram_memdev_id) { + create_default_memdev(current_machine, mem_path); + } /* do monitor/qmp handling at preconfig state if requested */ qemu_main_loop(); diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c index 99f28f267f..792a128a6d 100644 --- a/target/i386/fpu_helper.c +++ b/target/i386/fpu_helper.c @@ -991,7 +991,11 @@ void helper_fxam_ST0(CPUX86State *env) env->fpus |= 0x200; /* C1 <-- 1 */ } - /* XXX: test fptags too */ + if (env->fptags[env->fpstt]) { + env->fpus |= 0x4100; /* Empty */ + return; + } + expdif = EXPD(temp); if (expdif == MAXEXPD) { if (MANTD(temp) == 0x8000000000000000ULL) { diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index a8b6e5aeb8..f9c83fff25 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -367,7 +367,7 @@ static int hax_accel_init(MachineState *ms) static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) { if (hft->direction < 2) { - cpu_physical_memory_rw(hft->gpa, (uint8_t *) &hft->value, hft->size, + cpu_physical_memory_rw(hft->gpa, &hft->value, hft->size, hft->direction); } else { /* @@ -376,8 +376,8 @@ static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) * hft->direction == 2: gpa ==> gpa2 */ uint64_t value; - cpu_physical_memory_rw(hft->gpa, (uint8_t *) &value, hft->size, 0); - cpu_physical_memory_rw(hft->gpa2, (uint8_t *) &value, hft->size, 1); + cpu_physical_memory_read(hft->gpa, &value, hft->size); + cpu_physical_memory_write(hft->gpa2, &value, hft->size); } return 0; diff --git a/target/i386/hvf/vmx.h b/target/i386/hvf/vmx.h index eb8894cd58..03d2c79b9c 100644 --- a/target/i386/hvf/vmx.h +++ b/target/i386/hvf/vmx.h @@ -125,10 +125,9 @@ static inline void macvm_set_cr0(hv_vcpuid_t vcpu, uint64_t cr0) if ((cr0 & CR0_PG) && (rvmcs(vcpu, VMCS_GUEST_CR4) & CR4_PAE) && !(efer & MSR_EFER_LME)) { - address_space_rw(&address_space_memory, - rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, - MEMTXATTRS_UNSPECIFIED, - (uint8_t *)pdpte, 32, 0); + address_space_read(&address_space_memory, + rvmcs(vcpu, VMCS_GUEST_CR3) & ~0x1f, + MEMTXATTRS_UNSPECIFIED, pdpte, 32); /* Only set PDPTE when appropriate. */ for (i = 0; i < 4; i++) { wvmcs(vcpu, VMCS_GUEST_PDPTE0 + i * 2, pdpte[i]); diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index d5a0efe718..65d4603dbf 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -88,8 +88,8 @@ static bool get_pt_entry(struct CPUState *cpu, struct gpt_translation *pt, } index = gpt_entry(pt->gva, level, pae); - address_space_rw(&address_space_memory, gpa + index * pte_size(pae), - MEMTXATTRS_UNSPECIFIED, (uint8_t *)&pte, pte_size(pae), 0); + address_space_read(&address_space_memory, gpa + index * pte_size(pae), + MEMTXATTRS_UNSPECIFIED, &pte, pte_size(pae)); pt->pte[level - 1] = pte; @@ -238,8 +238,8 @@ void vmx_write_mem(struct CPUState *cpu, target_ulong gva, void *data, int bytes if (!mmu_gva_to_gpa(cpu, gva, &gpa)) { VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva); } else { - address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, - data, copy, 1); + address_space_write(&address_space_memory, gpa, + MEMTXATTRS_UNSPECIFIED, data, copy); } bytes -= copy; @@ -259,8 +259,8 @@ void vmx_read_mem(struct CPUState *cpu, void *data, target_ulong gva, int bytes) if (!mmu_gva_to_gpa(cpu, gva, &gpa)) { VM_PANIC_EX("%s: mmu_gva_to_gpa %llx failed\n", __func__, gva); } - address_space_rw(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, - data, copy, 0); + address_space_read(&address_space_memory, gpa, MEMTXATTRS_UNSPECIFIED, + data, copy); bytes -= copy; gva += copy; diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c index 35601b8176..683d49d217 100644 --- a/target/i386/whpx-all.c +++ b/target/i386/whpx-all.c @@ -540,7 +540,7 @@ static HRESULT CALLBACK whpx_emu_ioport_callback( { MemTxAttrs attrs = { 0 }; address_space_rw(&address_space_io, IoAccess->Port, attrs, - (uint8_t *)&IoAccess->Data, IoAccess->AccessSize, + &IoAccess->Data, IoAccess->AccessSize, IoAccess->Direction); return S_OK; } diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index f8ad7d60fd..40b6d2b64d 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -344,8 +344,8 @@ enum { #define GET_C_LW_IMM(inst) ((extract32(inst, 6, 1) << 2) \ | (extract32(inst, 10, 3) << 3) \ | (extract32(inst, 5, 1) << 6)) -#define GET_C_LD_IMM(inst) ((extract32(inst, 10, 3) << 3) \ - | (extract32(inst, 5, 2) << 6)) +#define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ + | (extract16(inst, 5, 2) << 6)) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -363,7 +363,7 @@ enum { #define GET_C_RD(inst) GET_RD(inst) #define GET_C_RS1(inst) GET_RD(inst) #define GET_C_RS2(inst) extract32(inst, 2, 5) -#define GET_C_RS1S(inst) (8 + extract32(inst, 7, 3)) -#define GET_C_RS2S(inst) (8 + extract32(inst, 2, 3)) +#define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) +#define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 14dc71156b..d5de7f468a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -44,7 +44,6 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; target_ulong priv_ver; - uint32_t opcode; uint32_t mstatus_fs; uint32_t misa; uint32_t mem_idx; @@ -492,45 +491,45 @@ static void gen_set_rm(DisasContext *ctx, int rm) tcg_temp_free_i32(t0); } -static void decode_RV32_64C0(DisasContext *ctx) +static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) { - uint8_t funct3 = extract32(ctx->opcode, 13, 3); - uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode); - uint8_t rs1s = GET_C_RS1S(ctx->opcode); + uint8_t funct3 = extract16(opcode, 13, 3); + uint8_t rd_rs2 = GET_C_RS2S(opcode); + uint8_t rs1s = GET_C_RS1S(opcode); switch (funct3) { case 3: #if defined(TARGET_RISCV64) /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, - GET_C_LD_IMM(ctx->opcode)); + GET_C_LD_IMM(opcode)); #else /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, - GET_C_LW_IMM(ctx->opcode)); + GET_C_LW_IMM(opcode)); #endif break; case 7: #if defined(TARGET_RISCV64) /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, - GET_C_LD_IMM(ctx->opcode)); + GET_C_LD_IMM(opcode)); #else /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, - GET_C_LW_IMM(ctx->opcode)); + GET_C_LW_IMM(opcode)); #endif break; } } -static void decode_RV32_64C(DisasContext *ctx) +static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode) { - uint8_t op = extract32(ctx->opcode, 0, 2); + uint8_t op = extract16(opcode, 0, 2); switch (op) { case 0: - decode_RV32_64C0(ctx); + decode_RV32_64C0(ctx, opcode); break; } } @@ -709,22 +708,25 @@ static bool gen_shift(DisasContext *ctx, arg_r *a, /* Include the auto-generated decoder for 16 bit insn */ #include "decode_insn16.inc.c" -static void decode_opc(DisasContext *ctx) +static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) { /* check for compressed insn */ - if (extract32(ctx->opcode, 0, 2) != 3) { + if (extract16(opcode, 0, 2) != 3) { if (!has_ext(ctx, RVC)) { gen_exception_illegal(ctx); } else { ctx->pc_succ_insn = ctx->base.pc_next + 2; - if (!decode_insn16(ctx, ctx->opcode)) { + if (!decode_insn16(ctx, opcode)) { /* fall back to old decoder */ - decode_RV32_64C(ctx); + decode_RV32_64C(ctx, opcode); } } } else { + uint32_t opcode32 = opcode; + opcode32 = deposit32(opcode32, 16, 16, + translator_lduw(env, ctx->base.pc_next + 2)); ctx->pc_succ_insn = ctx->base.pc_next + 4; - if (!decode_insn32(ctx, ctx->opcode)) { + if (!decode_insn32(ctx, opcode32)) { gen_exception_illegal(ctx); } } @@ -776,9 +778,9 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *ctx = container_of(dcbase, DisasContext, base); CPURISCVState *env = cpu->env_ptr; + uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); - ctx->opcode = translator_ldl(env, ctx->base.pc_next); - decode_opc(ctx); + decode_opc(env, ctx, opcode16); ctx->base.pc_next = ctx->pc_succ_insn; if (ctx->base.is_jmp == DISAS_NEXT) { diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 1e9d6f20c1..3b58d10df3 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -393,7 +393,7 @@ static int mchk_store_vregs(CPUS390XState *env, uint64_t mcesao) MchkExtSaveArea *sa; int i; - sa = cpu_physical_memory_map(mcesao, &len, 1); + sa = cpu_physical_memory_map(mcesao, &len, true); if (!sa) { return -EFAULT; } diff --git a/target/s390x/helper.c b/target/s390x/helper.c index a3a49164e4..b810ad431e 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -151,7 +151,7 @@ LowCore *cpu_map_lowcore(CPUS390XState *env) LowCore *lowcore; hwaddr len = sizeof(LowCore); - lowcore = cpu_physical_memory_map(env->psa, &len, 1); + lowcore = cpu_physical_memory_map(env->psa, &len, true); if (len < sizeof(LowCore)) { cpu_abort(env_cpu(env), "Could not map lowcore\n"); @@ -246,7 +246,7 @@ int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch) hwaddr len = sizeof(*sa); int i; - sa = cpu_physical_memory_map(addr, &len, 1); + sa = cpu_physical_memory_map(addr, &len, true); if (!sa) { return -EFAULT; } @@ -298,7 +298,7 @@ int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len) hwaddr save = len; int i; - sa = cpu_physical_memory_map(addr, &save, 1); + sa = cpu_physical_memory_map(addr, &save, true); if (!sa) { return -EFAULT; } diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c index c9f3f34750..0be2f300bb 100644 --- a/target/s390x/mmu_helper.c +++ b/target/s390x/mmu_helper.c @@ -106,7 +106,7 @@ static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr, * We treat them as absolute addresses and don't wrap them. */ if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED, - (uint8_t *)entry, sizeof(*entry)) != + entry, sizeof(*entry)) != MEMTX_OK)) { return false; } diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7d782002e3..e2e25ebf7d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2794,13 +2794,26 @@ static void tcg_gen_req_mo(TCGBar type) } } +static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr) +{ +#ifdef CONFIG_PLUGIN + if (tcg_ctx->plugin_insn != NULL) { + /* Save a copy of the vaddr for use after a load. */ + TCGv temp = tcg_temp_new(); + tcg_gen_mov_tl(temp, vaddr); + return temp; + } +#endif + return vaddr; +} + static inline void plugin_gen_mem_callbacks(TCGv vaddr, uint16_t info) { #ifdef CONFIG_PLUGIN - if (tcg_ctx->plugin_insn == NULL) { - return; + if (tcg_ctx->plugin_insn != NULL) { + plugin_gen_empty_mem_callback(vaddr, info); + tcg_temp_free(vaddr); } - plugin_gen_empty_mem_callback(vaddr, info); #endif } @@ -2822,6 +2835,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) } } + addr = plugin_prep_mem_callbacks(addr); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); plugin_gen_mem_callbacks(addr, info); @@ -2868,6 +2882,7 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) memop &= ~MO_BSWAP; } + addr = plugin_prep_mem_callbacks(addr); gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); plugin_gen_mem_callbacks(addr, info); @@ -2905,6 +2920,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) } } + addr = plugin_prep_mem_callbacks(addr); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); plugin_gen_mem_callbacks(addr, info); @@ -2967,6 +2983,7 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) memop &= ~MO_BSWAP; } + addr = plugin_prep_mem_callbacks(addr); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); plugin_gen_mem_callbacks(addr, info); diff --git a/tests/plugin/bb.c b/tests/plugin/bb.c index f30bea08dc..df19fd359d 100644 --- a/tests/plugin/bb.c +++ b/tests/plugin/bb.c @@ -22,9 +22,9 @@ static bool do_inline; static void plugin_exit(qemu_plugin_id_t id, void *p) { - g_autofree gchar *out; - out = g_strdup_printf("bb's: %" PRIu64", insns: %" PRIu64 "\n", - bb_count, insn_count); + g_autofree gchar *out = g_strdup_printf( + "bb's: %" PRIu64", insns: %" PRIu64 "\n", + bb_count, insn_count); qemu_plugin_outs(out); } diff --git a/tests/plugin/howvec.c b/tests/plugin/howvec.c index 4ca555e123..3b9a6939f2 100644 --- a/tests/plugin/howvec.c +++ b/tests/plugin/howvec.c @@ -163,6 +163,13 @@ static gint cmp_exec_count(gconstpointer a, gconstpointer b) return ea->count > eb->count ? -1 : 1; } +static void free_record(gpointer data) +{ + InsnExecCount *rec = (InsnExecCount *) data; + g_free(rec->insn); + g_free(rec); +} + static void plugin_exit(qemu_plugin_id_t id, void *p) { g_autoptr(GString) report = g_string_new("Instruction Classes:\n"); @@ -195,30 +202,31 @@ static void plugin_exit(qemu_plugin_id_t id, void *p) counts = g_hash_table_get_values(insns); if (counts && g_list_next(counts)) { - GList *it; - g_string_append_printf(report,"Individual Instructions:\n"); + counts = g_list_sort(counts, cmp_exec_count); - it = g_list_sort(counts, cmp_exec_count); - - for (i = 0; i < limit && it->next; i++, it = it->next) { - InsnExecCount *rec = (InsnExecCount *) it->data; - g_string_append_printf(report, "Instr: %-24s\t(%ld hits)\t(op=%#08x/%s)\n", + for (i = 0; i < limit && g_list_next(counts); + i++, counts = g_list_next(counts)) { + InsnExecCount *rec = (InsnExecCount *) counts->data; + g_string_append_printf(report, + "Instr: %-24s\t(%ld hits)\t(op=%#08x/%s)\n", rec->insn, rec->count, rec->opcode, rec->class ? rec->class->class : "un-categorised"); } - g_list_free(it); + g_list_free(counts); } + g_hash_table_destroy(insns); + qemu_plugin_outs(report->str); } static void plugin_init(void) { - insns = g_hash_table_new(NULL, g_direct_equal); + insns = g_hash_table_new_full(NULL, g_direct_equal, NULL, &free_record); } static void vcpu_insn_exec_before(unsigned int cpu_index, void *udata) diff --git a/tests/plugin/insn.c b/tests/plugin/insn.c index 0a8f5a0000..a9a6e41237 100644 --- a/tests/plugin/insn.c +++ b/tests/plugin/insn.c @@ -44,8 +44,7 @@ static void vcpu_tb_trans(qemu_plugin_id_t id, struct qemu_plugin_tb *tb) static void plugin_exit(qemu_plugin_id_t id, void *p) { - g_autofree gchar *out; - out = g_strdup_printf("insns: %" PRIu64 "\n", insn_count); + g_autofree gchar *out = g_strdup_printf("insns: %" PRIu64 "\n", insn_count); qemu_plugin_outs(out); } diff --git a/tests/qemu-iotests/214 b/tests/qemu-iotests/214 index 3500e0c47a..af677d90b8 100755 --- a/tests/qemu-iotests/214 +++ b/tests/qemu-iotests/214 @@ -125,9 +125,9 @@ $QEMU_IO -c "write -P 0xcc $offset $data_size" "json:{\ sizeB=$($QEMU_IMG info --output=json "$TEST_IMG" | sed -n '/"actual-size":/ s/[^0-9]//gp') -if [ $sizeA -le $sizeB ] +if [ $sizeA -lt $sizeB ] then - echo "Compression ERROR" + echo "Compression ERROR ($sizeA < $sizeB)" fi $QEMU_IMG check --output=json "$TEST_IMG" | diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c index 17dd807d2a..2f9b7f663a 100644 --- a/tests/qtest/numa-test.c +++ b/tests/qtest/numa-test.c @@ -14,67 +14,60 @@ #include "qapi/qmp/qdict.h" #include "qapi/qmp/qlist.h" -static char *make_cli(const char *generic_cli, const char *test_cli) +static char *make_cli(const GString *generic_cli, const char *test_cli) { - return g_strdup_printf("%s %s", generic_cli ? generic_cli : "", test_cli); + return g_strdup_printf("%s %s", generic_cli->str, test_cli); } static void test_mon_explicit(const void *data) { - char *s; - char *cli; QTestState *qts; + g_autofree char *s = NULL; + g_autofree char *cli = NULL; - cli = make_cli(data, "-smp 8 " - "-numa node,nodeid=0,cpus=0-3 " - "-numa node,nodeid=1,cpus=4-7 "); + cli = make_cli(data, "-smp 8 -numa node,nodeid=0,memdev=ram,cpus=0-3 " + "-numa node,nodeid=1,cpus=4-7"); qts = qtest_init(cli); s = qtest_hmp(qts, "info numa"); g_assert(strstr(s, "node 0 cpus: 0 1 2 3")); g_assert(strstr(s, "node 1 cpus: 4 5 6 7")); - g_free(s); qtest_quit(qts); - g_free(cli); } -static void test_mon_default(const void *data) +static void test_def_cpu_split(const void *data) { - char *s; - char *cli; QTestState *qts; + g_autofree char *s = NULL; + g_autofree char *cli = NULL; - cli = make_cli(data, "-smp 8 -numa node -numa node"); + cli = make_cli(data, "-smp 8 -numa node,memdev=ram -numa node"); qts = qtest_init(cli); s = qtest_hmp(qts, "info numa"); g_assert(strstr(s, "node 0 cpus: 0 2 4 6")); g_assert(strstr(s, "node 1 cpus: 1 3 5 7")); - g_free(s); qtest_quit(qts); - g_free(cli); } static void test_mon_partial(const void *data) { - char *s; - char *cli; QTestState *qts; + g_autofree char *s = NULL; + g_autofree char *cli = NULL; cli = make_cli(data, "-smp 8 " - "-numa node,nodeid=0,cpus=0-1 " + "-numa node,nodeid=0,memdev=ram,cpus=0-1 " "-numa node,nodeid=1,cpus=4-5 "); qts = qtest_init(cli); s = qtest_hmp(qts, "info numa"); g_assert(strstr(s, "node 0 cpus: 0 1 2 3 6 7")); g_assert(strstr(s, "node 1 cpus: 4 5")); - g_free(s); qtest_quit(qts); - g_free(cli); } static QList *get_cpus(QTestState *qts, QDict **resp) @@ -87,13 +80,14 @@ static QList *get_cpus(QTestState *qts, QDict **resp) static void test_query_cpus(const void *data) { - char *cli; QDict *resp; QList *cpus; QObject *e; QTestState *qts; + g_autofree char *cli = NULL; - cli = make_cli(data, "-smp 8 -numa node,cpus=0-3 -numa node,cpus=4-7"); + cli = make_cli(data, "-smp 8 -numa node,memdev=ram,cpus=0-3 " + "-numa node,cpus=4-7"); qts = qtest_init(cli); cpus = get_cpus(qts, &resp); g_assert(cpus); @@ -120,19 +114,18 @@ static void test_query_cpus(const void *data) qobject_unref(resp); qtest_quit(qts); - g_free(cli); } static void pc_numa_cpu(const void *data) { - char *cli; QDict *resp; QList *cpus; QObject *e; QTestState *qts; + g_autofree char *cli = NULL; cli = make_cli(data, "-cpu pentium -smp 8,sockets=2,cores=2,threads=2 " - "-numa node,nodeid=0 -numa node,nodeid=1 " + "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " "-numa cpu,node-id=1,socket-id=0 " "-numa cpu,node-id=0,socket-id=1,core-id=0 " "-numa cpu,node-id=0,socket-id=1,core-id=1,thread-id=0 " @@ -174,19 +167,18 @@ static void pc_numa_cpu(const void *data) qobject_unref(resp); qtest_quit(qts); - g_free(cli); } static void spapr_numa_cpu(const void *data) { - char *cli; QDict *resp; QList *cpus; QObject *e; QTestState *qts; + g_autofree char *cli = NULL; cli = make_cli(data, "-smp 4,cores=4 " - "-numa node,nodeid=0 -numa node,nodeid=1 " + "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " "-numa cpu,node-id=0,core-id=0 " "-numa cpu,node-id=0,core-id=1 " "-numa cpu,node-id=0,core-id=2 " @@ -220,19 +212,18 @@ static void spapr_numa_cpu(const void *data) qobject_unref(resp); qtest_quit(qts); - g_free(cli); } static void aarch64_numa_cpu(const void *data) { - char *cli; QDict *resp; QList *cpus; QObject *e; QTestState *qts; + g_autofree char *cli = NULL; cli = make_cli(data, "-smp 2 " - "-numa node,nodeid=0 -numa node,nodeid=1 " + "-numa node,nodeid=0,memdev=ram -numa node,nodeid=1 " "-numa cpu,node-id=1,thread-id=0 " "-numa cpu,node-id=0,thread-id=1"); qts = qtest_init(cli); @@ -264,7 +255,6 @@ static void aarch64_numa_cpu(const void *data) qobject_unref(resp); qtest_quit(qts); - g_free(cli); } static void pc_dynamic_cpu_cfg(const void *data) @@ -273,13 +263,14 @@ static void pc_dynamic_cpu_cfg(const void *data) QDict *resp; QList *cpus; QTestState *qs; + g_autofree char *cli = NULL; - qs = qtest_initf("%s -nodefaults --preconfig -smp 2", - data ? (char *)data : ""); + cli = make_cli(data, "-nodefaults --preconfig -smp 2"); + qs = qtest_init(cli); /* create 2 numa nodes */ g_assert(!qmp_rsp_is_err(qtest_qmp(qs, "{ 'execute': 'set-numa-node'," - " 'arguments': { 'type': 'node', 'nodeid': 0 } }"))); + " 'arguments': { 'type': 'node', 'nodeid': 0, 'memdev': 'ram' } }"))); g_assert(!qmp_rsp_is_err(qtest_qmp(qs, "{ 'execute': 'set-numa-node'," " 'arguments': { 'type': 'node', 'nodeid': 1 } }"))); @@ -329,16 +320,19 @@ static void pc_dynamic_cpu_cfg(const void *data) static void pc_hmat_build_cfg(const void *data) { - QTestState *qs = qtest_initf("%s -nodefaults --preconfig -machine hmat=on " - "-smp 2,sockets=2 " - "-m 128M,slots=2,maxmem=1G " - "-object memory-backend-ram,size=64M,id=m0 " - "-object memory-backend-ram,size=64M,id=m1 " - "-numa node,nodeid=0,memdev=m0 " - "-numa node,nodeid=1,memdev=m1,initiator=0 " - "-numa cpu,node-id=0,socket-id=0 " - "-numa cpu,node-id=0,socket-id=1", - data ? (char *)data : ""); + QTestState *qs; + g_autofree char *cli = NULL; + + cli = make_cli(data, "-nodefaults --preconfig -machine hmat=on " + "-smp 2,sockets=2 " + "-m 128M,slots=2,maxmem=1G " + "-object memory-backend-ram,size=64M,id=m0 " + "-object memory-backend-ram,size=64M,id=m1 " + "-numa node,nodeid=0,memdev=m0 " + "-numa node,nodeid=1,memdev=m1,initiator=0 " + "-numa cpu,node-id=0,socket-id=0 " + "-numa cpu,node-id=0,socket-id=1"); + qs = qtest_init(cli); /* Fail: Initiator should be less than the number of nodes */ g_assert_true(qmp_rsp_is_err(qtest_qmp(qs, "{ 'execute': 'set-numa-node'," @@ -455,13 +449,16 @@ static void pc_hmat_build_cfg(const void *data) static void pc_hmat_off_cfg(const void *data) { - QTestState *qs = qtest_initf("%s -nodefaults --preconfig " - "-smp 2,sockets=2 " - "-m 128M,slots=2,maxmem=1G " - "-object memory-backend-ram,size=64M,id=m0 " - "-object memory-backend-ram,size=64M,id=m1 " - "-numa node,nodeid=0,memdev=m0", - data ? (char *)data : ""); + QTestState *qs; + g_autofree char *cli = NULL; + + cli = make_cli(data, "-nodefaults --preconfig " + "-smp 2,sockets=2 " + "-m 128M,slots=2,maxmem=1G " + "-object memory-backend-ram,size=64M,id=m0 " + "-object memory-backend-ram,size=64M,id=m1 " + "-numa node,nodeid=0,memdev=m0"); + qs = qtest_init(cli); /* * Fail: Enable HMAT with -machine hmat=on @@ -491,16 +488,19 @@ static void pc_hmat_off_cfg(const void *data) static void pc_hmat_erange_cfg(const void *data) { - QTestState *qs = qtest_initf("%s -nodefaults --preconfig -machine hmat=on " - "-smp 2,sockets=2 " - "-m 128M,slots=2,maxmem=1G " - "-object memory-backend-ram,size=64M,id=m0 " - "-object memory-backend-ram,size=64M,id=m1 " - "-numa node,nodeid=0,memdev=m0 " - "-numa node,nodeid=1,memdev=m1,initiator=0 " - "-numa cpu,node-id=0,socket-id=0 " - "-numa cpu,node-id=0,socket-id=1", - data ? (char *)data : ""); + QTestState *qs; + g_autofree char *cli = NULL; + + cli = make_cli(data, "-nodefaults --preconfig -machine hmat=on " + "-smp 2,sockets=2 " + "-m 128M,slots=2,maxmem=1G " + "-object memory-backend-ram,size=64M,id=m0 " + "-object memory-backend-ram,size=64M,id=m1 " + "-numa node,nodeid=0,memdev=m0 " + "-numa node,nodeid=1,memdev=m1,initiator=0 " + "-numa cpu,node-id=0,socket-id=0 " + "-numa cpu,node-id=0,socket-id=1"); + qs = qtest_init(cli); /* Can't store the compressed latency */ g_assert_false(qmp_rsp_is_err(qtest_qmp(qs, "{ 'execute': 'set-numa-node'," @@ -539,16 +539,22 @@ static void pc_hmat_erange_cfg(const void *data) int main(int argc, char **argv) { - const char *args = NULL; + g_autoptr(GString) args = g_string_new(NULL); const char *arch = qtest_get_arch(); - if (strcmp(arch, "aarch64") == 0) { - args = "-machine virt"; + if (g_str_equal(arch, "ppc64")) { + g_string_append(args, " -object memory-backend-ram,id=ram,size=512M"); + } else { + g_string_append(args, " -object memory-backend-ram,id=ram,size=128M"); + } + + if (g_str_equal(arch, "aarch64")) { + g_string_append(args, " -machine virt"); } g_test_init(&argc, &argv, NULL); - qtest_add_data_func("/numa/mon/default", args, test_mon_default); + qtest_add_data_func("/numa/mon/cpus/default", args, test_def_cpu_split); qtest_add_data_func("/numa/mon/cpus/explicit", args, test_mon_explicit); qtest_add_data_func("/numa/mon/cpus/partial", args, test_mon_partial); qtest_add_data_func("/numa/qmp/cpus/query-cpus", args, test_query_cpus); diff --git a/tests/rcutorture.c b/tests/rcutorture.c index 49311c82ea..732f03abda 100644 --- a/tests/rcutorture.c +++ b/tests/rcutorture.c @@ -65,8 +65,6 @@ #include "qemu/rcu.h" #include "qemu/thread.h" -long long n_reads = 0LL; -long n_updates = 0L; int nthreadsrunning; #define GOFLAG_INIT 0 @@ -78,11 +76,20 @@ static volatile int goflag = GOFLAG_INIT; #define RCU_READ_RUN 1000 #define NR_THREADS 100 -static QemuMutex counts_mutex; static QemuThread threads[NR_THREADS]; static struct rcu_reader_data *data[NR_THREADS]; static int n_threads; +/* + * Statistical counts + * + * These are the sum of local counters at the end of a run. + * Updates are protected by a mutex. + */ +static QemuMutex counts_mutex; +long long n_reads = 0LL; +long n_updates = 0L; + static void create_thread(void *(*func)(void *)) { if (n_threads >= NR_THREADS) { @@ -223,15 +230,15 @@ static void uperftest(int nupdaters, int duration) #define RCU_STRESS_PIPE_LEN 10 struct rcu_stress { - int pipe_count; + int age; /* how many update cycles while not rcu_stress_current */ int mbtest; }; struct rcu_stress rcu_stress_array[RCU_STRESS_PIPE_LEN] = { { 0 } }; struct rcu_stress *rcu_stress_current; -int rcu_stress_idx; - int n_mberror; + +/* Updates protected by counts_mutex */ long long rcu_stress_count[RCU_STRESS_PIPE_LEN + 1]; @@ -253,7 +260,7 @@ static void *rcu_read_stress_test(void *arg) while (goflag == GOFLAG_RUN) { rcu_read_lock(); p = atomic_rcu_read(&rcu_stress_current); - if (p->mbtest == 0) { + if (atomic_read(&p->mbtest) == 0) { n_mberror++; } rcu_read_lock(); @@ -261,7 +268,7 @@ static void *rcu_read_stress_test(void *arg) garbage++; } rcu_read_unlock(); - pc = p->pipe_count; + pc = atomic_read(&p->age); rcu_read_unlock(); if ((pc > RCU_STRESS_PIPE_LEN) || (pc < 0)) { pc = RCU_STRESS_PIPE_LEN; @@ -280,32 +287,52 @@ static void *rcu_read_stress_test(void *arg) return NULL; } +/* + * Stress Test Updater + * + * The updater cycles around updating rcu_stress_current to point at + * one of the rcu_stress_array_entries and resets it's age. It + * then increments the age of all the other entries. The age + * will be read under an rcu_read_lock() and distribution of values + * calculated. The final result gives an indication of how many + * previously current rcu_stress entries are in flight until the RCU + * cycle complete. + */ static void *rcu_update_stress_test(void *arg) { - int i; - struct rcu_stress *p; + int i, rcu_stress_idx = 0; + struct rcu_stress *cp = atomic_read(&rcu_stress_current); rcu_register_thread(); - *(struct rcu_reader_data **)arg = &rcu_reader; + while (goflag == GOFLAG_INIT) { g_usleep(1000); } + while (goflag == GOFLAG_RUN) { - i = rcu_stress_idx + 1; - if (i >= RCU_STRESS_PIPE_LEN) { - i = 0; + struct rcu_stress *p; + rcu_stress_idx++; + if (rcu_stress_idx >= RCU_STRESS_PIPE_LEN) { + rcu_stress_idx = 0; } - p = &rcu_stress_array[i]; - p->mbtest = 0; + p = &rcu_stress_array[rcu_stress_idx]; + /* catching up with ourselves would be a bug */ + assert(p != cp); + atomic_set(&p->mbtest, 0); smp_mb(); - p->pipe_count = 0; - p->mbtest = 1; + atomic_set(&p->age, 0); + atomic_set(&p->mbtest, 1); atomic_rcu_set(&rcu_stress_current, p); - rcu_stress_idx = i; + cp = p; + /* + * New RCU structure is now live, update pipe counts on old + * ones. + */ for (i = 0; i < RCU_STRESS_PIPE_LEN; i++) { if (i != rcu_stress_idx) { - rcu_stress_array[i].pipe_count++; + atomic_set(&rcu_stress_array[i].age, + rcu_stress_array[i].age + 1); } } synchronize_rcu(); @@ -338,7 +365,7 @@ static void stresstest(int nreaders, int duration) int i; rcu_stress_current = &rcu_stress_array[0]; - rcu_stress_current->pipe_count = 0; + rcu_stress_current->age = 0; rcu_stress_current->mbtest = 1; for (i = 0; i < nreaders; i++) { create_thread(rcu_read_stress_test); @@ -368,7 +395,7 @@ static void gtest_stress(int nreaders, int duration) int i; rcu_stress_current = &rcu_stress_array[0]; - rcu_stress_current->pipe_count = 0; + rcu_stress_current->age = 0; rcu_stress_current->mbtest = 1; for (i = 0; i < nreaders; i++) { create_thread(rcu_read_stress_test); @@ -413,7 +440,8 @@ static void gtest_stress_10_5(void) static void usage(int argc, char *argv[]) { - fprintf(stderr, "Usage: %s [nreaders [ perf | stress ] ]\n", argv[0]); + fprintf(stderr, "Usage: %s [nreaders [ [r|u]perf | stress [duration]]\n", + argv[0]); exit(-1); } diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target index 3c7421a356..b3cff3cad1 100644 --- a/tests/tcg/Makefile.target +++ b/tests/tcg/Makefile.target @@ -79,7 +79,7 @@ QEMU_OPTS= # If TCG debugging is enabled things are a lot slower ifeq ($(CONFIG_DEBUG_TCG),y) -TIMEOUT=45 +TIMEOUT=60 else TIMEOUT=15 endif @@ -137,7 +137,7 @@ PLUGINS=$(notdir $(wildcard $(PLUGIN_DIR)/*.so)) $(foreach p,$(PLUGINS), \ $(foreach t,$(TESTS),\ $(eval run-plugin-$(t)-with-$(p): $t $p) \ - $(eval run-plugin-$(t)-with-$(p): TIMEOUT=30) \ + $(eval run-plugin-$(t)-with-$(p): TIMEOUT=60) \ $(eval RUN_TESTS+=run-plugin-$(t)-with-$(p)))) endif diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index d2299b98b7..71f72cfbe3 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -70,4 +70,6 @@ pauth-3: $(call skip-test, "BUILD of $@", "missing compiler support") run-pauth-3: $(call skip-test, "RUN of pauth-3", "not built") +run-plugin-pauth-3-with-%: + $(call skip-test, "RUN of pauth-3 ($*)", "not built") endif diff --git a/tests/tcg/aarch64/pauth-4.c b/tests/tcg/aarch64/pauth-4.c index 1040e92aec..24a639e36c 100644 --- a/tests/tcg/aarch64/pauth-4.c +++ b/tests/tcg/aarch64/pauth-4.c @@ -1,25 +1,45 @@ #include <stdint.h> #include <assert.h> +#include <stdio.h> +#include <stdlib.h> + +#define TESTS 1000 int main() { - uintptr_t x, y; + int i, count = 0; + float perc; + void *base = malloc(TESTS); + + for (i = 0; i < TESTS; i++) { + uintptr_t in, x, y; + + in = i + (uintptr_t) base; + + asm("mov %0, %[in]\n\t" + "pacia %0, sp\n\t" /* sigill if pauth not supported */ + "eor %0, %0, #4\n\t" /* corrupt single bit */ + "mov %1, %0\n\t" + "autia %1, sp\n\t" /* validate corrupted pointer */ + "xpaci %0\n\t" /* strip pac from corrupted pointer */ + : /* out */ "=r"(x), "=r"(y) + : /* in */ [in] "r" (in) + : /* clobbers */); - asm("mov %0, lr\n\t" - "pacia %0, sp\n\t" /* sigill if pauth not supported */ - "eor %0, %0, #4\n\t" /* corrupt single bit */ - "mov %1, %0\n\t" - "autia %1, sp\n\t" /* validate corrupted pointer */ - "xpaci %0\n\t" /* strip pac from corrupted pointer */ - : "=r"(x), "=r"(y)); + /* + * Once stripped, the corrupted pointer is of the form 0x0000...wxyz. + * We expect the autia to indicate failure, producing a pointer of the + * form 0x000e....wxyz. Use xpaci and != for the test, rather than + * extracting explicit bits from the top, because the location of the + * error code "e" depends on the configuration of virtual memory. + */ + if (x != y) { + count++; + } - /* - * Once stripped, the corrupted pointer is of the form 0x0000...wxyz. - * We expect the autia to indicate failure, producing a pointer of the - * form 0x000e....wxyz. Use xpaci and != for the test, rather than - * extracting explicit bits from the top, because the location of the - * error code "e" depends on the configuration of virtual memory. - */ - assert(x != y); - return 0; + } + perc = (float) count / (float) TESTS; + printf("Checks Passed: %0.2f%%", perc * 100.0); + assert(perc > 0.95); + return 0; } diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 9eb6ba3b7e..eaaaff6233 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -228,7 +228,7 @@ for target in $target_list; do echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak fi if do_compiler "$target_compiler" $target_compiler_cflags \ - -march=-march=armv8.3-a -o $TMPE $TMPC; then + -march=armv8.3-a -o $TMPE $TMPC; then echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak fi ;; diff --git a/trace/control.c b/trace/control.c index 6c775e68eb..2ffe000818 100644 --- a/trace/control.c +++ b/trace/control.c @@ -226,10 +226,15 @@ void trace_init_file(const char *file) #ifdef CONFIG_TRACE_SIMPLE st_set_trace_file(file); #elif defined CONFIG_TRACE_LOG - /* If both the simple and the log backends are enabled, "--trace file" - * only applies to the simple backend; use "-D" for the log backend. + /* + * If both the simple and the log backends are enabled, "--trace file" + * only applies to the simple backend; use "-D" for the log + * backend. However we should only override -D if we actually have + * something to override it with. */ - qemu_set_log_filename(file, &error_fatal); + if (file) { + qemu_set_log_filename(file, &error_fatal); + } #else if (file) { fprintf(stderr, "error: --trace file=...: " diff --git a/util/oslib-posix.c b/util/oslib-posix.c index 5a291cc982..897e8f3ba6 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -76,6 +76,10 @@ static MemsetThread *memset_thread; static int memset_num_threads; static bool memset_thread_failed; +static QemuMutex page_mutex; +static QemuCond page_cond; +static bool threads_created_flag; + int qemu_get_thread_id(void) { #if defined(__linux__) @@ -403,6 +407,17 @@ static void *do_touch_pages(void *arg) MemsetThread *memset_args = (MemsetThread *)arg; sigset_t set, oldset; + /* + * On Linux, the page faults from the loop below can cause mmap_sem + * contention with allocation of the thread stacks. Do not start + * clearing until all threads have been created. + */ + qemu_mutex_lock(&page_mutex); + while(!threads_created_flag){ + qemu_cond_wait(&page_cond, &page_mutex); + } + qemu_mutex_unlock(&page_mutex); + /* unblock SIGBUS */ sigemptyset(&set); sigaddset(&set, SIGBUS); @@ -451,27 +466,28 @@ static inline int get_memset_num_threads(int smp_cpus) static bool touch_all_pages(char *area, size_t hpagesize, size_t numpages, int smp_cpus) { - size_t numpages_per_thread; - size_t size_per_thread; + size_t numpages_per_thread, leftover; char *addr = area; int i = 0; memset_thread_failed = false; + threads_created_flag = false; memset_num_threads = get_memset_num_threads(smp_cpus); memset_thread = g_new0(MemsetThread, memset_num_threads); - numpages_per_thread = (numpages / memset_num_threads); - size_per_thread = (hpagesize * numpages_per_thread); + numpages_per_thread = numpages / memset_num_threads; + leftover = numpages % memset_num_threads; for (i = 0; i < memset_num_threads; i++) { memset_thread[i].addr = addr; - memset_thread[i].numpages = (i == (memset_num_threads - 1)) ? - numpages : numpages_per_thread; + memset_thread[i].numpages = numpages_per_thread + (i < leftover); memset_thread[i].hpagesize = hpagesize; qemu_thread_create(&memset_thread[i].pgthread, "touch_pages", do_touch_pages, &memset_thread[i], QEMU_THREAD_JOINABLE); - addr += size_per_thread; - numpages -= numpages_per_thread; + addr += memset_thread[i].numpages * hpagesize; } + threads_created_flag = true; + qemu_cond_broadcast(&page_cond); + for (i = 0; i < memset_num_threads; i++) { qemu_thread_join(&memset_thread[i].pgthread); } |