diff options
| -rw-r--r-- | hw/intc/pnv_xive.c | 19 | ||||
| -rw-r--r-- | include/hw/ppc/pnv.h | 5 |
2 files changed, 24 insertions, 0 deletions
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 9798bd9e72..ec8349ee4a 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -372,6 +372,21 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } +/* + * One bit per thread id. The first register PC_THREAD_EN_REG0 covers + * the first cores 0-15 (normal) of the chip or 0-7 (fused). The + * second register covers cores 16-23 (normal) or 8-11 (fused). + */ +static bool pnv_xive_is_cpu_enabled(PnvXive *xive, PowerPCCPU *cpu) +{ + int pir = ppc_cpu_pir(cpu); + uint32_t fc = PNV9_PIR2FUSEDCORE(pir); + uint64_t reg = fc < 8 ? PC_THREAD_EN_REG0 : PC_THREAD_EN_REG1; + uint32_t bit = pir & 0x3f; + + return xive->regs[reg >> 3] & PPC_BIT(bit); +} + static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, @@ -391,6 +406,10 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, XiveTCTX *tctx; int ring; + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + continue; + } + tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); /* diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 03cb429f21..12b0169a40 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -99,6 +99,11 @@ typedef struct Pnv9Chip { PnvQuad *quads; } Pnv9Chip; +/* + * A SMT8 fused core is a pair of SMT4 cores. + */ +#define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) + typedef struct PnvChipClass { /*< private >*/ SysBusDeviceClass parent_class; |