diff options
| -rw-r--r-- | hw/alpha/dp264.c | 2 | ||||
| -rw-r--r-- | hw/hppa/machine.c | 2 | ||||
| -rw-r--r-- | hw/mips/fuloong2e.c | 1 | ||||
| -rw-r--r-- | hw/mips/malta.c | 2 | ||||
| -rw-r--r-- | hw/ppc/prep.c | 2 | ||||
| -rw-r--r-- | hw/sparc64/sun4u.c | 1 |
6 files changed, 0 insertions, 10 deletions
diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index f4349eba83..c502c8c62a 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -20,8 +20,6 @@ #include "qemu/datadir.h" #include "net/net.h" -#define MAX_IDE_BUS 2 - static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr) { if (((addr >> 41) & 3) == 2) { diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index 19ea7c2c66..de1cc7ab71 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -30,8 +30,6 @@ #include "qemu/log.h" #include "net/net.h" -#define MAX_IDE_BUS 2 - #define MIN_SEABIOS_HPPA_VERSION 6 /* require at least this fw version */ #define HPA_POWER_BUTTON (FIRMWARE_END - 0x10) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index b478483706..50c61f0e4a 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -49,7 +49,6 @@ /* Fuloong 2e has a 512k flash: Winbond W39L040AP70Z */ #define BIOS_SIZE (512 * KiB) -#define MAX_IDE_BUS 2 /* * PMON is not part of qemu and released with BSD license, anyone diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 7c3ad0974b..2d4341bd50 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -70,8 +70,6 @@ #define FLASH_SIZE 0x400000 -#define MAX_IDE_BUS 2 - typedef struct { MemoryRegion iomem; MemoryRegion iomem_lo; /* 0 - 0x900 */ diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index f08714f2ec..fcbe4c5837 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -50,8 +50,6 @@ /* SMP is not enabled, for now */ #define MAX_CPUS 1 -#define MAX_IDE_BUS 2 - #define CFG_ADDR 0xf0000510 #define KERNEL_LOAD_ADDR 0x01000000 diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 0e27715ac4..387181ff77 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -66,7 +66,6 @@ #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) #define PROM_FILENAME "openbios-sparc64" #define NVRAM_SIZE 0x2000 -#define MAX_IDE_BUS 2 #define BIOS_CFG_IOPORT 0x510 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) |