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-rw-r--r--docs/system/arm/aspeed.rst16
-rw-r--r--hw/arm/aspeed_ast2600.c51
-rw-r--r--hw/arm/aspeed_soc.c34
-rw-r--r--hw/misc/aspeed_lpc.c486
-rw-r--r--hw/misc/meson.build7
-rw-r--r--include/hw/arm/aspeed_soc.h3
-rw-r--r--include/hw/misc/aspeed_lpc.h47
7 files changed, 625 insertions, 19 deletions
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
index 690bada784..d1fb8f25b3 100644
--- a/docs/system/arm/aspeed.rst
+++ b/docs/system/arm/aspeed.rst
@@ -48,6 +48,7 @@ Supported devices
* UART
* Ethernet controllers
* Front LEDs (PCA9552 on I2C bus)
+ * LPC Peripheral Controller (a subset of subdevices are supported)
Missing devices
@@ -56,7 +57,6 @@ Missing devices
* Coprocessor support
* ADC (out of tree implementation)
* PWM and Fan Controller
- * LPC Bus Controller
* Slave GPIO Controller
* Super I/O Controller
* Hash/Crypto Engine
@@ -72,18 +72,22 @@ Missing devices
Boot options
------------
-The Aspeed machines can be started using the -kernel option to load a
-Linux kernel or from a firmware image which can be downloaded from the
-OpenPOWER jenkins :
+The Aspeed machines can be started using the ``-kernel`` option to
+load a Linux kernel or from a firmware. Images can be downloaded from
+the OpenBMC jenkins :
- https://openpower.xyz/
+ https://jenkins.openbmc.org/job/ci-openbmc/lastSuccessfulBuild/distro=ubuntu,label=docker-builder
+
+or directly from the OpenBMC GitHub release repository :
+
+ https://github.com/openbmc/openbmc/releases
The image should be attached as an MTD drive. Run :
.. code-block:: bash
$ qemu-system-arm -M romulus-bmc -nic user \
- -drive file=flash-romulus,format=raw,if=mtd -nographic
+ -drive file=obmc-phosphor-image-romulus.static.mtd,format=raw,if=mtd -nographic
Options specific to Aspeed machines are :
diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c
index bf31ca351f..bc87e754a3 100644
--- a/hw/arm/aspeed_ast2600.c
+++ b/hw/arm/aspeed_ast2600.c
@@ -65,7 +65,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = {
#define ASPEED_A7MPCORE_ADDR 0x40460000
-#define ASPEED_SOC_AST2600_MAX_IRQ 128
+#define AST2600_MAX_IRQ 197
/* Shared Peripheral Interrupt values below are offset by -32 from datasheet */
static const int aspeed_soc_ast2600_irqmap[] = {
@@ -98,13 +98,13 @@ static const int aspeed_soc_ast2600_irqmap[] = {
[ASPEED_DEV_WDT] = 24,
[ASPEED_DEV_PWM] = 44,
[ASPEED_DEV_LPC] = 35,
- [ASPEED_DEV_IBT] = 35, /* LPC */
+ [ASPEED_DEV_IBT] = 143,
[ASPEED_DEV_I2C] = 110, /* 110 -> 125 */
[ASPEED_DEV_ETH1] = 2,
[ASPEED_DEV_ETH2] = 3,
[ASPEED_DEV_ETH3] = 32,
[ASPEED_DEV_ETH4] = 33,
-
+ [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */
};
static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl)
@@ -211,6 +211,8 @@ static void aspeed_soc_ast2600_init(Object *obj)
object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0],
TYPE_SYSBUS_SDHCI);
+
+ object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
}
/*
@@ -241,8 +243,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
/* CPU */
for (i = 0; i < sc->num_cpus; i++) {
- object_property_set_int(OBJECT(&s->cpu[i]), "psci-conduit",
- QEMU_PSCI_CONDUIT_SMC, &error_abort);
if (sc->num_cpus > 1) {
object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
ASPEED_A7MPCORE_ADDR, &error_abort);
@@ -253,11 +253,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->cpu[i]), "cntfrq", 1125000000,
&error_abort);
- /*
- * TODO: the secondary CPUs are started and a boot helper
- * is needed when using -kernel
- */
-
if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
return;
}
@@ -267,7 +262,7 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(&s->a7mpcore), "num-cpu", sc->num_cpus,
&error_abort);
object_property_set_int(OBJECT(&s->a7mpcore), "num-irq",
- ASPEED_SOC_AST2600_MAX_IRQ + GIC_INTERNAL,
+ ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32),
&error_abort);
sysbus_realize(SYS_BUS_DEVICE(&s->a7mpcore), &error_abort);
@@ -469,6 +464,40 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->emmc), 0, sc->memmap[ASPEED_DEV_EMMC]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_EMMC));
+
+ /* LPC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
+
+ /* Connect the LPC IRQ to the GIC. It is otherwise unused. */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
+
+ /*
+ * On the AST2600 LPC subdevice IRQs are connected straight to the GIC.
+ *
+ * LPC subdevice IRQ sources are offset from 1 because the LPC model caters
+ * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ
+ * shared across the subdevices, and the shared IRQ output to the VIC is at
+ * offset 0.
+ */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
+ qdev_get_gpio_in(DEVICE(&s->a7mpcore),
+ sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4));
}
static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index 7eefd54ac0..057d053c84 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -112,7 +112,6 @@ static const int aspeed_soc_ast2400_irqmap[] = {
[ASPEED_DEV_WDT] = 27,
[ASPEED_DEV_PWM] = 28,
[ASPEED_DEV_LPC] = 8,
- [ASPEED_DEV_IBT] = 8, /* LPC */
[ASPEED_DEV_I2C] = 12,
[ASPEED_DEV_ETH1] = 2,
[ASPEED_DEV_ETH2] = 3,
@@ -211,6 +210,8 @@ static void aspeed_soc_init(Object *obj)
object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
TYPE_SYSBUS_SDHCI);
}
+
+ object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
}
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -393,6 +394,37 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp)
sc->memmap[ASPEED_DEV_SDHCI]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
+
+ /* LPC */
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
+
+ /* Connect the LPC IRQ to the VIC */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
+ aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
+
+ /*
+ * On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
+ * subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
+ * contrast, on the AST2600, the subdevice IRQs are connected straight to
+ * the GIC).
+ *
+ * LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
+ * to the VIC is at offset 0.
+ */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
+
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
+ qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
}
static Property aspeed_soc_properties[] = {
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
diff --git a/hw/misc/aspeed_lpc.c b/hw/misc/aspeed_lpc.c
new file mode 100644
index 0000000000..2dddb27c35
--- /dev/null
+++ b/hw/misc/aspeed_lpc.c
@@ -0,0 +1,486 @@
+/*
+ * ASPEED LPC Controller
+ *
+ * Copyright (C) 2017-2018 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/error-report.h"
+#include "hw/misc/aspeed_lpc.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "migration/vmstate.h"
+
+#define TO_REG(offset) ((offset) >> 2)
+
+#define HICR0 TO_REG(0x00)
+#define HICR0_LPC3E BIT(7)
+#define HICR0_LPC2E BIT(6)
+#define HICR0_LPC1E BIT(5)
+#define HICR1 TO_REG(0x04)
+#define HICR2 TO_REG(0x08)
+#define HICR2_IBFIE3 BIT(3)
+#define HICR2_IBFIE2 BIT(2)
+#define HICR2_IBFIE1 BIT(1)
+#define HICR3 TO_REG(0x0C)
+#define HICR4 TO_REG(0x10)
+#define HICR4_KCSENBL BIT(2)
+#define IDR1 TO_REG(0x24)
+#define IDR2 TO_REG(0x28)
+#define IDR3 TO_REG(0x2C)
+#define ODR1 TO_REG(0x30)
+#define ODR2 TO_REG(0x34)
+#define ODR3 TO_REG(0x38)
+#define STR1 TO_REG(0x3C)
+#define STR_OBF BIT(0)
+#define STR_IBF BIT(1)
+#define STR_CMD_DATA BIT(3)
+#define STR2 TO_REG(0x40)
+#define STR3 TO_REG(0x44)
+#define HICR5 TO_REG(0x80)
+#define HICR6 TO_REG(0x84)
+#define HICR7 TO_REG(0x88)
+#define HICR8 TO_REG(0x8C)
+#define HICRB TO_REG(0x100)
+#define HICRB_IBFIE4 BIT(1)
+#define HICRB_LPC4E BIT(0)
+#define IDR4 TO_REG(0x114)
+#define ODR4 TO_REG(0x118)
+#define STR4 TO_REG(0x11C)
+
+enum aspeed_kcs_channel_id {
+ kcs_channel_1 = 0,
+ kcs_channel_2,
+ kcs_channel_3,
+ kcs_channel_4,
+};
+
+static const enum aspeed_lpc_subdevice aspeed_kcs_subdevice_map[] = {
+ [kcs_channel_1] = aspeed_lpc_kcs_1,
+ [kcs_channel_2] = aspeed_lpc_kcs_2,
+ [kcs_channel_3] = aspeed_lpc_kcs_3,
+ [kcs_channel_4] = aspeed_lpc_kcs_4,
+};
+
+struct aspeed_kcs_channel {
+ enum aspeed_kcs_channel_id id;
+
+ int idr;
+ int odr;
+ int str;
+};
+
+static const struct aspeed_kcs_channel aspeed_kcs_channel_map[] = {
+ [kcs_channel_1] = {
+ .id = kcs_channel_1,
+ .idr = IDR1,
+ .odr = ODR1,
+ .str = STR1
+ },
+
+ [kcs_channel_2] = {
+ .id = kcs_channel_2,
+ .idr = IDR2,
+ .odr = ODR2,
+ .str = STR2
+ },
+
+ [kcs_channel_3] = {
+ .id = kcs_channel_3,
+ .idr = IDR3,
+ .odr = ODR3,
+ .str = STR3
+ },
+
+ [kcs_channel_4] = {
+ .id = kcs_channel_4,
+ .idr = IDR4,
+ .odr = ODR4,
+ .str = STR4
+ },
+};
+
+struct aspeed_kcs_register_data {
+ const char *name;
+ int reg;
+ const struct aspeed_kcs_channel *chan;
+};
+
+static const struct aspeed_kcs_register_data aspeed_kcs_registers[] = {
+ {
+ .name = "idr1",
+ .reg = IDR1,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_1],
+ },
+ {
+ .name = "odr1",
+ .reg = ODR1,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_1],
+ },
+ {
+ .name = "str1",
+ .reg = STR1,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_1],
+ },
+ {
+ .name = "idr2",
+ .reg = IDR2,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_2],
+ },
+ {
+ .name = "odr2",
+ .reg = ODR2,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_2],
+ },
+ {
+ .name = "str2",
+ .reg = STR2,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_2],
+ },
+ {
+ .name = "idr3",
+ .reg = IDR3,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_3],
+ },
+ {
+ .name = "odr3",
+ .reg = ODR3,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_3],
+ },
+ {
+ .name = "str3",
+ .reg = STR3,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_3],
+ },
+ {
+ .name = "idr4",
+ .reg = IDR4,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_4],
+ },
+ {
+ .name = "odr4",
+ .reg = ODR4,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_4],
+ },
+ {
+ .name = "str4",
+ .reg = STR4,
+ .chan = &aspeed_kcs_channel_map[kcs_channel_4],
+ },
+ { },
+};
+
+static const struct aspeed_kcs_register_data *
+aspeed_kcs_get_register_data_by_name(const char *name)
+{
+ const struct aspeed_kcs_register_data *pos = aspeed_kcs_registers;
+
+ while (pos->name) {
+ if (!strcmp(pos->name, name)) {
+ return pos;
+ }
+ pos++;
+ }
+
+ return NULL;
+}
+
+static const struct aspeed_kcs_channel *
+aspeed_kcs_get_channel_by_register(int reg)
+{
+ const struct aspeed_kcs_register_data *pos = aspeed_kcs_registers;
+
+ while (pos->name) {
+ if (pos->reg == reg) {
+ return pos->chan;
+ }
+ pos++;
+ }
+
+ return NULL;
+}
+
+static void aspeed_kcs_get_register_property(Object *obj,
+ Visitor *v,
+ const char *name,
+ void *opaque,
+ Error **errp)
+{
+ const struct aspeed_kcs_register_data *data;
+ AspeedLPCState *s = ASPEED_LPC(obj);
+ uint32_t val;
+
+ data = aspeed_kcs_get_register_data_by_name(name);
+ if (!data) {
+ return;
+ }
+
+ if (!strncmp("odr", name, 3)) {
+ s->regs[data->chan->str] &= ~STR_OBF;
+ }
+
+ val = s->regs[data->reg];
+
+ visit_type_uint32(v, name, &val, errp);
+}
+
+static bool aspeed_kcs_channel_enabled(AspeedLPCState *s,
+ const struct aspeed_kcs_channel *channel)
+{
+ switch (channel->id) {
+ case kcs_channel_1: return s->regs[HICR0] & HICR0_LPC1E;
+ case kcs_channel_2: return s->regs[HICR0] & HICR0_LPC2E;
+ case kcs_channel_3:
+ return (s->regs[HICR0] & HICR0_LPC3E) &&
+ (s->regs[HICR4] & HICR4_KCSENBL);
+ case kcs_channel_4: return s->regs[HICRB] & HICRB_LPC4E;
+ default: return false;
+ }
+}
+
+static bool
+aspeed_kcs_channel_ibf_irq_enabled(AspeedLPCState *s,
+ const struct aspeed_kcs_channel *channel)
+{
+ if (!aspeed_kcs_channel_enabled(s, channel)) {
+ return false;
+ }
+
+ switch (channel->id) {
+ case kcs_channel_1: return s->regs[HICR2] & HICR2_IBFIE1;
+ case kcs_channel_2: return s->regs[HICR2] & HICR2_IBFIE2;
+ case kcs_channel_3: return s->regs[HICR2] & HICR2_IBFIE3;
+ case kcs_channel_4: return s->regs[HICRB] & HICRB_IBFIE4;
+ default: return false;
+ }
+}
+
+static void aspeed_kcs_set_register_property(Object *obj,
+ Visitor *v,
+ const char *name,
+ void *opaque,
+ Error **errp)
+{
+ const struct aspeed_kcs_register_data *data;
+ AspeedLPCState *s = ASPEED_LPC(obj);
+ uint32_t val;
+
+ data = aspeed_kcs_get_register_data_by_name(name);
+ if (!data) {
+ return;
+ }
+
+ if (!visit_type_uint32(v, name, &val, errp)) {
+ return;
+ }
+
+ if (strncmp("str", name, 3)) {
+ s->regs[data->reg] = val;
+ }
+
+ if (!strncmp("idr", name, 3)) {
+ s->regs[data->chan->str] |= STR_IBF;
+ if (aspeed_kcs_channel_ibf_irq_enabled(s, data->chan)) {
+ enum aspeed_lpc_subdevice subdev;
+
+ subdev = aspeed_kcs_subdevice_map[data->chan->id];
+ qemu_irq_raise(s->subdevice_irqs[subdev]);
+ }
+ }
+}
+
+static void aspeed_lpc_set_irq(void *opaque, int irq, int level)
+{
+ AspeedLPCState *s = (AspeedLPCState *)opaque;
+
+ if (level) {
+ s->subdevice_irqs_pending |= BIT(irq);
+ } else {
+ s->subdevice_irqs_pending &= ~BIT(irq);
+ }
+
+ qemu_set_irq(s->irq, !!s->subdevice_irqs_pending);
+}
+
+static uint64_t aspeed_lpc_read(void *opaque, hwaddr offset, unsigned size)
+{
+ AspeedLPCState *s = ASPEED_LPC(opaque);
+ int reg = TO_REG(offset);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return 0;
+ }
+
+ switch (reg) {
+ case IDR1:
+ case IDR2:
+ case IDR3:
+ case IDR4:
+ {
+ const struct aspeed_kcs_channel *channel;
+
+ channel = aspeed_kcs_get_channel_by_register(reg);
+ if (s->regs[channel->str] & STR_IBF) {
+ enum aspeed_lpc_subdevice subdev;
+
+ subdev = aspeed_kcs_subdevice_map[channel->id];
+ qemu_irq_lower(s->subdevice_irqs[subdev]);
+ }
+
+ s->regs[channel->str] &= ~STR_IBF;
+ break;
+ }
+ default:
+ break;
+ }
+
+ return s->regs[reg];
+}
+
+static void aspeed_lpc_write(void *opaque, hwaddr offset, uint64_t data,
+ unsigned int size)
+{
+ AspeedLPCState *s = ASPEED_LPC(opaque);
+ int reg = TO_REG(offset);
+
+ if (reg >= ARRAY_SIZE(s->regs)) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
+ __func__, offset);
+ return;
+ }
+
+
+ switch (reg) {
+ case ODR1:
+ case ODR2:
+ case ODR3:
+ case ODR4:
+ s->regs[aspeed_kcs_get_channel_by_register(reg)->str] |= STR_OBF;
+ break;
+ default:
+ break;
+ }
+
+ s->regs[reg] = data;
+}
+
+static const MemoryRegionOps aspeed_lpc_ops = {
+ .read = aspeed_lpc_read,
+ .write = aspeed_lpc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 4,
+ },
+};
+
+static void aspeed_lpc_reset(DeviceState *dev)
+{
+ struct AspeedLPCState *s = ASPEED_LPC(dev);
+
+ s->subdevice_irqs_pending = 0;
+
+ memset(s->regs, 0, sizeof(s->regs));
+
+ s->regs[HICR7] = s->hicr7;
+}
+
+static void aspeed_lpc_realize(DeviceState *dev, Error **errp)
+{
+ AspeedLPCState *s = ASPEED_LPC(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+
+ sysbus_init_irq(sbd, &s->irq);
+ sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_1]);
+ sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_2]);
+ sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_3]);
+ sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_4]);
+ sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_ibt]);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_lpc_ops, s,
+ TYPE_ASPEED_LPC, 0x1000);
+
+ sysbus_init_mmio(sbd, &s->iomem);
+
+ qdev_init_gpio_in(dev, aspeed_lpc_set_irq, ASPEED_LPC_NR_SUBDEVS);
+}
+
+static void aspeed_lpc_init(Object *obj)
+{
+ object_property_add(obj, "idr1", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "odr1", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "str1", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "idr2", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "odr2", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "str2", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "idr3", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "odr3", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "str3", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "idr4", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "odr4", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+ object_property_add(obj, "str4", "uint32", aspeed_kcs_get_register_property,
+ aspeed_kcs_set_register_property, NULL, NULL);
+}
+
+static const VMStateDescription vmstate_aspeed_lpc = {
+ .name = TYPE_ASPEED_LPC,
+ .version_id = 2,
+ .minimum_version_id = 2,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AspeedLPCState, ASPEED_LPC_NR_REGS),
+ VMSTATE_UINT32(subdevice_irqs_pending, AspeedLPCState),
+ VMSTATE_END_OF_LIST(),
+ }
+};
+
+static Property aspeed_lpc_properties[] = {
+ DEFINE_PROP_UINT32("hicr7", AspeedLPCState, hicr7, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void aspeed_lpc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = aspeed_lpc_realize;
+ dc->reset = aspeed_lpc_reset;
+ dc->desc = "Aspeed LPC Controller",
+ dc->vmsd = &vmstate_aspeed_lpc;
+ device_class_set_props(dc, aspeed_lpc_properties);
+}
+
+static const TypeInfo aspeed_lpc_info = {
+ .name = TYPE_ASPEED_LPC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(AspeedLPCState),
+ .class_init = aspeed_lpc_class_init,
+ .instance_init = aspeed_lpc_init,
+};
+
+static void aspeed_lpc_register_types(void)
+{
+ type_register_static(&aspeed_lpc_info);
+}
+
+type_init(aspeed_lpc_register_types);
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
index e30a555db5..00356cf12e 100644
--- a/hw/misc/meson.build
+++ b/hw/misc/meson.build
@@ -103,7 +103,12 @@ softmmu_ss.add(when: 'CONFIG_ARMSSE_MHU', if_true: files('armsse-mhu.c'))
softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true: files('pvpanic-isa.c'))
softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c'))
softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c'))
-softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_scu.c', 'aspeed_sdmc.c', 'aspeed_xdma.c'))
+softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
+ 'aspeed_lpc.c',
+ 'aspeed_scu.c',
+ 'aspeed_sdmc.c',
+ 'aspeed_xdma.c'))
+
softmmu_ss.add(when: 'CONFIG_MSF2', if_true: files('msf2-sysreg.c'))
softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_rng.c'))
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 11cfe6e358..9359d6da33 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -28,6 +28,7 @@
#include "hw/sd/aspeed_sdhci.h"
#include "hw/usb/hcd-ehci.h"
#include "qom/object.h"
+#include "hw/misc/aspeed_lpc.h"
#define ASPEED_SPIS_NUM 2
#define ASPEED_EHCIS_NUM 2
@@ -61,6 +62,7 @@ struct AspeedSoCState {
AspeedGPIOState gpio_1_8v;
AspeedSDHCIState sdhci;
AspeedSDHCIState emmc;
+ AspeedLPCState lpc;
};
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -130,6 +132,7 @@ enum {
ASPEED_DEV_SDRAM,
ASPEED_DEV_XDMA,
ASPEED_DEV_EMMC,
+ ASPEED_DEV_KCS,
};
#endif /* ASPEED_SOC_H */
diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h
new file mode 100644
index 0000000000..df418cfcd3
--- /dev/null
+++ b/include/hw/misc/aspeed_lpc.h
@@ -0,0 +1,47 @@
+/*
+ * ASPEED LPC Controller
+ *
+ * Copyright (C) 2017-2018 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef ASPEED_LPC_H
+#define ASPEED_LPC_H
+
+#include "hw/sysbus.h"
+
+#include <stdint.h>
+
+#define TYPE_ASPEED_LPC "aspeed.lpc"
+#define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC)
+
+#define ASPEED_LPC_NR_REGS (0x260 >> 2)
+
+enum aspeed_lpc_subdevice {
+ aspeed_lpc_kcs_1 = 0,
+ aspeed_lpc_kcs_2,
+ aspeed_lpc_kcs_3,
+ aspeed_lpc_kcs_4,
+ aspeed_lpc_ibt,
+};
+
+#define ASPEED_LPC_NR_SUBDEVS 5
+
+typedef struct AspeedLPCState {
+ /* <private> */
+ SysBusDevice parent;
+
+ /*< public >*/
+ MemoryRegion iomem;
+ qemu_irq irq;
+
+ qemu_irq subdevice_irqs[ASPEED_LPC_NR_SUBDEVS];
+ uint32_t subdevice_irqs_pending;
+
+ uint32_t regs[ASPEED_LPC_NR_REGS];
+ uint32_t hicr7;
+} AspeedLPCState;
+
+#endif /* _ASPEED_LPC_H_ */
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-28 07:31:51 +0000