diff options
| -rw-r--r-- | target-sparc/helper.h | 1 | ||||
| -rw-r--r-- | target-sparc/translate.c | 32 | ||||
| -rw-r--r-- | target-sparc/vis_helper.c | 12 |
3 files changed, 26 insertions, 19 deletions
diff --git a/target-sparc/helper.h b/target-sparc/helper.h index 3ee12a9c55..faaf8dc7ad 100644 --- a/target-sparc/helper.h +++ b/target-sparc/helper.h @@ -125,7 +125,6 @@ DEF_HELPER_1(fqtoi, s32, env) DEF_HELPER_2(fstox, s64, env, f32) DEF_HELPER_2(fdtox, s64, env, f64) DEF_HELPER_1(fqtox, s64, env) -DEF_HELPER_3(faligndata, i64, env, i64, i64) DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64) DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_CONST | TCG_CALL_PURE, i64, i64, i64) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 50fc587865..93185402fd 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2338,6 +2338,31 @@ static void gen_alignaddr(TCGv dst, TCGv s1, TCGv s2, bool left) tcg_temp_free(tmp); } + +static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2) +{ + TCGv t1, t2, shift; + + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + shift = tcg_temp_new(); + + tcg_gen_andi_tl(shift, gsr, 7); + tcg_gen_shli_tl(shift, shift, 3); + tcg_gen_shl_tl(t1, s1, shift); + + /* A shift of 64 does not produce 0 in TCG. Divide this into a + shift of (up to 63) followed by a constant shift of 1. */ + tcg_gen_xori_tl(shift, shift, 63); + tcg_gen_shr_tl(t2, s2, shift); + tcg_gen_shri_tl(t2, t2, 1); + + tcg_gen_or_tl(dst, t1, t2); + + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(shift); +} #endif #define CHECK_IU_FEATURE(dc, FEATURE) \ @@ -4307,12 +4332,7 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x048: /* VIS I faligndata */ CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - cpu_dst_64 = gen_dest_fpr_D(); - gen_helper_faligndata(cpu_dst_64, cpu_env, - cpu_src1_64, cpu_src2_64); - gen_store_fpr_D(dc, rd, cpu_dst_64); + gen_gsr_fop_DDD(dc, rd, rs1, rs2, gen_faligndata); break; case 0x04b: /* VIS I fpmerge */ CHECK_FPU_FEATURE(dc, VIS1); diff --git a/target-sparc/vis_helper.c b/target-sparc/vis_helper.c index 7830120991..a992c293af 100644 --- a/target-sparc/vis_helper.c +++ b/target-sparc/vis_helper.c @@ -41,18 +41,6 @@ target_ulong helper_array8(target_ulong pixel_addr, target_ulong cubesize) GET_FIELD_SP(pixel_addr, 11, 12); } -uint64_t helper_faligndata(CPUState *env, uint64_t src1, uint64_t src2) -{ - uint64_t tmp; - - tmp = src1 << ((env->gsr & 7) * 8); - /* on many architectures a shift of 64 does nothing */ - if ((env->gsr & 7) != 0) { - tmp |= src2 >> (64 - (env->gsr & 7) * 8); - } - return tmp; -} - #ifdef HOST_WORDS_BIGENDIAN #define VIS_B64(n) b[7 - (n)] #define VIS_W64(n) w[3 - (n)] |