diff options
| -rw-r--r-- | hw/riscv/Kconfig | 1 | ||||
| -rw-r--r-- | hw/riscv/sifive_u.c | 30 | ||||
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 11 |
3 files changed, 42 insertions, 0 deletions
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 9032cb0cbd..e53ab1efa5 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -22,6 +22,7 @@ config SIFIVE_U select CADENCE select HART select SIFIVE + select SIFIVE_PDMA select UNIMP config SPIKE diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2bc3992989..79975372ef 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -14,6 +14,7 @@ * 4) GPIO (General Purpose Input/Output Controller) * 5) OTP (One-Time Programmable) memory with stored serial number * 6) GEM (Gigabit Ethernet Controller) and management block + * 7) DMA (Direct Memory Access Controller) * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -73,6 +74,7 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] = { 0x1000, 0xf000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_L2CC] = { 0x2010000, 0x1000 }, + [SIFIVE_U_PDMA] = { 0x3000000, 0x100000 }, [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, @@ -303,6 +305,22 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); g_free(nodename); + nodename = g_strdup_printf("/soc/dma@%lx", + (long)memmap[SIFIVE_U_PDMA].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", + SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, + SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, + SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_PDMA].base, + 0x0, memmap[SIFIVE_U_PDMA].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-pdma"); + g_free(nodename); + nodename = g_strdup_printf("/soc/cache-controller@%lx", (long)memmap[SIFIVE_U_L2CC].base); qemu_fdt_add_subnode(fdt, nodename); @@ -627,6 +645,7 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); + object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); } static void sifive_u_soc_realize(DeviceState *dev, Error **errp) @@ -730,6 +749,17 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) SIFIVE_U_GPIO_IRQ0 + i)); } + /* PDMA */ + sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base); + + /* Connect PDMA interrupts to the PLIC */ + for (i = 0; i < SIFIVE_PDMA_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, + qdev_get_gpio_in(DEVICE(s->plic), + SIFIVE_U_PDMA_IRQ0 + i)); + } + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { return; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index d3c0c00d10..793000a2ed 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,6 +19,7 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H +#include "hw/dma/sifive_pdma.h" #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" @@ -43,6 +44,7 @@ typedef struct SiFiveUSoCState { SiFiveUPRCIState prci; SIFIVEGPIOState gpio; SiFiveUOTPState otp; + SiFivePDMAState dma; CadenceGEMState gem; uint32_t serial; @@ -72,6 +74,7 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_L2CC, + SIFIVE_U_PDMA, SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, @@ -108,6 +111,14 @@ enum { SIFIVE_U_GPIO_IRQ13 = 20, SIFIVE_U_GPIO_IRQ14 = 21, SIFIVE_U_GPIO_IRQ15 = 22, + SIFIVE_U_PDMA_IRQ0 = 23, + SIFIVE_U_PDMA_IRQ1 = 24, + SIFIVE_U_PDMA_IRQ2 = 25, + SIFIVE_U_PDMA_IRQ3 = 26, + SIFIVE_U_PDMA_IRQ4 = 27, + SIFIVE_U_PDMA_IRQ5 = 28, + SIFIVE_U_PDMA_IRQ6 = 29, + SIFIVE_U_PDMA_IRQ7 = 30, SIFIVE_U_GEM_IRQ = 0x35 }; |