diff options
| -rw-r--r-- | hw/riscv/sifive_u.c | 23 | ||||
| -rw-r--r-- | include/hw/riscv/sifive_u.h | 2 |
2 files changed, 25 insertions, 0 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index d80b203cc1..7eefe9796a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -79,6 +79,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, char ethclk_names[] = "pclk\0hclk\0tx_clk"; uint32_t plic_phandle, ethclk_phandle, phandle = 1; uint32_t uartclk_phandle; + uint32_t hfclk_phandle, rtcclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -97,6 +98,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + hfclk_phandle = phandle++; + nodename = g_strdup_printf("/hfclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_HFCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + + rtcclk_phandle = phandle++; + nodename = g_strdup_printf("/rtcclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_RTCCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + nodename = g_strdup_printf("/memory@%lx", (long)memmap[SIFIVE_U_DRAM].base); qemu_fdt_add_subnode(fdt, nodename); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 6b2b5b68e2..24418145aa 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -69,6 +69,8 @@ enum { enum { SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_HFCLK_FREQ = 33333333, + SIFIVE_U_RTCCLK_FREQ = 1000000, SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; |