diff options
| -rw-r--r-- | hw/intc/pnv_xive.c | 40 | ||||
| -rw-r--r-- | hw/ppc/pnv.c | 14 | ||||
| -rw-r--r-- | include/hw/ppc/pnv.h | 3 |
3 files changed, 40 insertions, 17 deletions
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index 95e9de312c..db9d9c11a8 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -439,31 +439,37 @@ static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, return count; } +/* + * The TIMA MMIO space is shared among the chips and to identify the + * chip from which the access is being done, we extract the chip id + * from the PIR. + */ +static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) +{ + int pir = ppc_cpu_pir(cpu); + PnvChip *chip; + PnvXive *xive; + + chip = pnv_get_chip(PNV9_PIR2CHIP(pir)); + assert(chip); + xive = &PNV9_CHIP(chip)->xive; + + if (!pnv_xive_is_cpu_enabled(xive, cpu)) { + xive_error(xive, "IC: CPU %x is not enabled", pir); + } + return xive; +} + static XiveTCTX *pnv_xive_get_tctx(XiveRouter *xrtr, CPUState *cs) { PowerPCCPU *cpu = POWERPC_CPU(cs); - XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc); - PnvXive *xive = NULL; - CPUPPCState *env = &cpu->env; - int pir = env->spr_cb[SPR_PIR].default_value; + PnvXive *xive = pnv_xive_tm_get_xive(cpu); - /* - * Perform an extra check on the HW thread enablement. - * - * The TIMA is shared among the chips and to identify the chip - * from which the access is being done, we extract the chip id - * from the PIR. - */ - xive = pnv_xive_get_ic((pir >> 8) & 0xf); if (!xive) { return NULL; } - if (!(xive->regs[PC_THREAD_EN_REG0 >> 3] & PPC_BIT(pir & 0x3f))) { - xive_error(PNV_XIVE(xrtr), "IC: CPU %x is not enabled", pir); - } - - return tctx; + return XIVE_TCTX(pnv_cpu_state(cpu)->intc); } /* diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5b8b07f6ae..fa656858b2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1472,6 +1472,20 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, return total_count; } +PnvChip *pnv_get_chip(uint32_t chip_id) +{ + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + int i; + + for (i = 0; i < pnv->num_chips; i++) { + PnvChip *chip = pnv->chips[i]; + if (chip->chip_id == chip_id) { + return chip; + } + } + return NULL; +} + static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index a58cfea3f2..3a7bc3c57e 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -103,6 +103,7 @@ typedef struct Pnv9Chip { * A SMT8 fused core is a pair of SMT4 cores. */ #define PNV9_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf) +#define PNV9_PIR2CHIP(pir) (((pir) >> 8) & 0x7f) typedef struct PnvChipClass { /*< private >*/ @@ -197,6 +198,8 @@ static inline bool pnv_is_power9(PnvMachineState *pnv) return pnv_chip_is_power9(pnv->chips[0]); } +PnvChip *pnv_get_chip(uint32_t chip_id); + #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL |