diff options
| -rw-r--r-- | target-ppc/cpu.h | 10 | ||||
| -rw-r--r-- | target-ppc/translate.c | 6 |
2 files changed, 12 insertions, 4 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 9d4e43cf1f..5282533b38 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2415,6 +2415,16 @@ static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) return msr & (1ULL << MSR_SF); } +/** + * Check whether register rx is in the range between start and + * start + nregs (as needed by the LSWX and LSWI instructions) + */ +static inline bool lsw_reg_in_range(int start, int nregs, int rx) +{ + return (start + nregs <= 32 && rx >= start && rx < start + nregs) || + (start + nregs > 32 && (rx >= start || rx < start + nregs - 32)); +} + extern void (*cpu_ppc_hypercall)(PowerPCCPU *); #include "exec/exec-all.h" diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 6f0e7b4fac..b3860ecdea 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -3227,10 +3227,8 @@ static void gen_lswi(DisasContext *ctx) if (nb == 0) nb = 32; - nr = nb / 4; - if (unlikely(((start + nr) > 32 && - start <= ra && (start + nr - 32) > ra) || - ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) { + nr = (nb + 3) / 4; + if (unlikely(lsw_reg_in_range(start, nr, ra))) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); return; } |