diff options
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | block.c | 3 | ||||
| -rw-r--r-- | net/tap.c | 7 | ||||
| -rw-r--r-- | qemu-char.c | 4 | ||||
| -rw-r--r-- | qemu-sockets.c | 5 | ||||
| -rw-r--r-- | target-mips/translate.c | 42 | ||||
| -rw-r--r-- | target-openrisc/cpu.h | 18 | ||||
| -rw-r--r-- | tcg/arm/tcg-target.c | 98 | ||||
| -rw-r--r-- | tcg/tcg.c | 2 | ||||
| -rw-r--r-- | tci.c | 4 | ||||
| -rw-r--r-- | ui/vnc.c | 2 |
11 files changed, 113 insertions, 74 deletions
@@ -286,7 +286,7 @@ distclean: clean for d in $(TARGET_DIRS) $(QEMULIBS); do \ rm -rf $$d || exit 1 ; \ done - test -f pixman/config.log && make -C pixman distclean + if test -f pixman/config.log; then make -C pixman distclean; fi KEYMAPS=da en-gb et fr fr-ch is lt modifiers no pt-br sv \ ar de en-us fi fr-be hr it lv nl pl ru th \ @@ -787,7 +787,8 @@ int bdrv_open(BlockDriverState *bs, const char *filename, int flags, BlockDriver *drv) { int ret; - char tmp_filename[PATH_MAX]; + /* TODO: extra byte is a hack to ensure MAX_PATH space on Windows. */ + char tmp_filename[PATH_MAX + 1]; if (flags & BDRV_O_SNAPSHOT) { BlockDriverState *bs1; @@ -341,6 +341,13 @@ static TAPState *net_tap_fd_init(NetClientState *peer, s->using_vnet_hdr = 0; s->has_ufo = tap_probe_has_ufo(s->fd); tap_set_offload(&s->nc, 0, 0, 0, 0, 0); + /* + * Make sure host header length is set correctly in tap: + * it might have been modified by another instance of qemu. + */ + if (tap_probe_vnet_hdr_len(s->fd, s->host_vnet_hdr_len)) { + tap_fd_set_vnet_hdr_len(s->fd, s->host_vnet_hdr_len); + } tap_read_poll(s, 1); s->vhost_net = NULL; return s; diff --git a/qemu-char.c b/qemu-char.c index 88f40254b7..242b799909 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -134,9 +134,9 @@ static void qemu_chr_fire_open_event(void *opaque) void qemu_chr_generic_open(CharDriverState *s) { if (s->open_timer == NULL) { - s->open_timer = qemu_new_timer_ms(vm_clock, + s->open_timer = qemu_new_timer_ms(rt_clock, qemu_chr_fire_open_event, s); - qemu_mod_timer(s->open_timer, qemu_get_clock_ms(vm_clock) - 1); + qemu_mod_timer(s->open_timer, qemu_get_clock_ms(rt_clock) - 1); } } diff --git a/qemu-sockets.c b/qemu-sockets.c index cfed9c5a5b..d314cf1d1b 100644 --- a/qemu-sockets.c +++ b/qemu-sockets.c @@ -529,8 +529,9 @@ static InetSocketAddress *inet_parse(const char *str, Error **errp) optstr = str + pos; h = strstr(optstr, ",to="); if (h) { - if (1 != sscanf(str, "%d%n", &to, &pos) || - (str[pos] != '\0' && str[pos] != ',')) { + h += 4; + if (sscanf(h, "%d%n", &to, &pos) != 1 || + (h[pos] != '\0' && h[pos] != ',')) { error_setg(errp, "error parsing to= argument"); goto fail; } diff --git a/target-mips/translate.c b/target-mips/translate.c index 8b438f8bb0..71c55bcadb 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -10239,9 +10239,19 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx, return n_bytes; } -/* microMIPS extension to MIPS32 */ +/* microMIPS extension to MIPS32/MIPS64 */ -/* microMIPS32 major opcodes */ +/* + * microMIPS32/microMIPS64 major opcodes + * + * 1. MIPS Architecture for Programmers Volume II-B: + * The microMIPS32 Instruction Set (Revision 3.05) + * + * Table 6.2 microMIPS32 Encoding of Major Opcode Field + * + * 2. MIPS Architecture For Programmers Volume II-A: + * The MIPS64 Instruction Set (Revision 3.51) + */ enum { POOL32A = 0x00, @@ -10268,9 +10278,10 @@ enum { POOL16D = 0x13, ORI32 = 0x14, POOL32F = 0x15, - POOL32S = 0x16, - DADDIU32 = 0x17, + POOL32S = 0x16, /* MIPS64 */ + DADDIU32 = 0x17, /* MIPS64 */ + /* 0x1f is reserved */ POOL32C = 0x18, LWGP16 = 0x19, LW16 = 0x1a, @@ -10278,7 +10289,6 @@ enum { XORI32 = 0x1c, JALS32 = 0x1d, ADDIUPC = 0x1e, - POOL48A = 0x1f, /* 0x20 is reserved */ RES_20 = 0x20, @@ -10307,8 +10317,8 @@ enum { B16 = 0x33, ANDI32 = 0x34, J32 = 0x35, - SD32 = 0x36, - LD32 = 0x37, + SD32 = 0x36, /* MIPS64 */ + LD32 = 0x37, /* MIPS64 */ /* 0x38 and 0x39 are reserved */ RES_38 = 0x38, @@ -10359,6 +10369,19 @@ enum { /* POOL32AXF encoding of minor opcode field extension */ +/* + * 1. MIPS Architecture for Programmers Volume II-B: + * The microMIPS32 Instruction Set (Revision 3.05) + * + * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field + * + * 2. MIPS Architecture for Programmers VolumeIV-e: + * The MIPS DSP Application-Specific Extension + * to the microMIPS32 Architecture (Revision 2.34) + * + * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field + */ + enum { /* bits 11..6 */ TEQ = 0x00, @@ -10371,6 +10394,8 @@ enum { MFC0 = 0x03, MTC0 = 0x0b, + /* begin of microMIPS32 DSP */ + /* bits 13..12 for 0x01 */ MFHI_ACC = 0x0, MFLO_ACC = 0x1, @@ -10387,6 +10412,8 @@ enum { MULT_ACC = 0x0, MULTU_ACC = 0x1, + /* end of microMIPS32 DSP */ + /* bits 15..12 for 0x2c */ SEB = 0x2, SEH = 0x3, @@ -12356,7 +12383,6 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b case LB32: case LH32: case DADDIU32: - case POOL48A: /* ??? */ case LWC132: case LDC132: case LD32: diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index d42ffb09b6..ebb5ad3124 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -89,24 +89,6 @@ enum { /* Interrupt */ #define NR_IRQS 32 -/* Registers */ -enum { - R0 = 0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, - R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, - R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, - R31 -}; - -/* Register aliases */ -enum { - R_ZERO = R0, - R_SP = R1, - R_FP = R2, - R_LR = R9, - R_RV = R11, - R_RVH = R12 -}; - /* Unit presece register */ enum { UPR_UP = (1 << 0), diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index e790bf04b4..47612fe260 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -611,6 +611,22 @@ static inline void tcg_out_bswap16(TCGContext *s, int cond, int rd, int rn) } } +/* swap the two low bytes assuming that the two high input bytes and the + two high output bit can hold any value. */ +static inline void tcg_out_bswap16st(TCGContext *s, int cond, int rd, int rn) +{ + if (use_armv6_instructions) { + /* rev16 */ + tcg_out32(s, 0x06bf0fb0 | (cond << 28) | (rd << 12) | rn); + } else { + tcg_out_dat_reg(s, cond, ARITH_MOV, + TCG_REG_R8, 0, rn, SHIFT_IMM_LSR(8)); + tcg_out_dat_imm(s, cond, ARITH_AND, TCG_REG_R8, TCG_REG_R8, 0xff); + tcg_out_dat_reg(s, cond, ARITH_ORR, + rd, TCG_REG_R8, rn, SHIFT_IMM_LSL(8)); + } +} + static inline void tcg_out_bswap32(TCGContext *s, int cond, int rd, int rn) { if (use_armv6_instructions) { @@ -639,6 +655,22 @@ static inline void tcg_out_ld32_12(TCGContext *s, int cond, (rn << 16) | (rd << 12) | ((-im) & 0xfff)); } +/* Offset pre-increment with base writeback. */ +static inline void tcg_out_ld32_12wb(TCGContext *s, int cond, + int rd, int rn, tcg_target_long im) +{ + /* ldr with writeback and both register equals is UNPREDICTABLE */ + assert(rd != rn); + + if (im >= 0) { + tcg_out32(s, (cond << 28) | 0x05b00000 | + (rn << 16) | (rd << 12) | (im & 0xfff)); + } else { + tcg_out32(s, (cond << 28) | 0x05300000 | + (rn << 16) | (rd << 12) | ((-im) & 0xfff)); + } +} + static inline void tcg_out_st32_12(TCGContext *s, int cond, int rd, int rn, tcg_target_long im) { @@ -1071,7 +1103,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) { int addr_reg, data_reg, data_reg2, bswap; #ifdef CONFIG_SOFTMMU - int mem_index, s_bits; + int mem_index, s_bits, tlb_offset; TCGReg argreg; # if TARGET_LONG_BITS == 64 int addr_reg2; @@ -1111,19 +1143,15 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1); tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); - /* In the - * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_read))] - * below, the offset is likely to exceed 12 bits if mem_index != 0 and - * not exceed otherwise, so use an - * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table) - * before. - */ - if (mem_index) + /* We assume that the offset is contained within 20 bits. */ + tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read); + assert(tlb_offset & ~0xfffff == 0); + if (tlb_offset > 0xfff) { tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0, - (mem_index << (TLB_SHIFT & 1)) | - ((16 - (TLB_SHIFT >> 1)) << 8)); - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0, - offsetof(CPUArchState, tlb_table[0][0].addr_read)); + 0xa00 | (tlb_offset >> 12)); + tlb_offset &= 0xfff; + } + tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset); tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1, TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); /* Check alignment. */ @@ -1131,15 +1159,14 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_out_dat_imm(s, COND_EQ, ARITH_TST, 0, addr_reg, (1 << s_bits) - 1); # if TARGET_LONG_BITS == 64 - /* XXX: possibly we could use a block data load or writeback in - * the first access. */ - tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, - offsetof(CPUArchState, tlb_table[0][0].addr_read) + 4); + /* XXX: possibly we could use a block data load in the first access. */ + tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4); tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0)); # endif tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, - offsetof(CPUArchState, tlb_table[0][0].addend)); + offsetof(CPUTLBEntry, addend) + - offsetof(CPUTLBEntry, addr_read)); switch (opc) { case 0: @@ -1288,7 +1315,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) { int addr_reg, data_reg, data_reg2, bswap; #ifdef CONFIG_SOFTMMU - int mem_index, s_bits; + int mem_index, s_bits, tlb_offset; TCGReg argreg; # if TARGET_LONG_BITS == 64 int addr_reg2; @@ -1325,19 +1352,15 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) TCG_REG_R0, TCG_REG_R8, CPU_TLB_SIZE - 1); tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_AREG0, TCG_REG_R0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS)); - /* In the - * ldr r1 [r0, #(offsetof(CPUArchState, tlb_table[mem_index][0].addr_write))] - * below, the offset is likely to exceed 12 bits if mem_index != 0 and - * not exceed otherwise, so use an - * add r0, r0, #(mem_index * sizeof *CPUArchState.tlb_table) - * before. - */ - if (mem_index) + /* We assume that the offset is contained within 20 bits. */ + tlb_offset = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write); + assert(tlb_offset & ~0xfffff == 0); + if (tlb_offset > 0xfff) { tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R0, TCG_REG_R0, - (mem_index << (TLB_SHIFT & 1)) | - ((16 - (TLB_SHIFT >> 1)) << 8)); - tcg_out_ld32_12(s, COND_AL, TCG_REG_R1, TCG_REG_R0, - offsetof(CPUArchState, tlb_table[0][0].addr_write)); + 0xa00 | (tlb_offset >> 12)); + tlb_offset &= 0xfff; + } + tcg_out_ld32_12wb(s, COND_AL, TCG_REG_R1, TCG_REG_R0, tlb_offset); tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0, TCG_REG_R1, TCG_REG_R8, SHIFT_IMM_LSL(TARGET_PAGE_BITS)); /* Check alignment. */ @@ -1345,15 +1368,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_out_dat_imm(s, COND_EQ, ARITH_TST, 0, addr_reg, (1 << s_bits) - 1); # if TARGET_LONG_BITS == 64 - /* XXX: possibly we could use a block data load or writeback in - * the first access. */ - tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, - offsetof(CPUArchState, tlb_table[0][0].addr_write) + 4); + /* XXX: possibly we could use a block data load in the first access. */ + tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, 4); tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0, TCG_REG_R1, addr_reg2, SHIFT_IMM_LSL(0)); # endif tcg_out_ld32_12(s, COND_EQ, TCG_REG_R1, TCG_REG_R0, - offsetof(CPUArchState, tlb_table[0][0].addend)); + offsetof(CPUTLBEntry, addend) + - offsetof(CPUTLBEntry, addr_write)); switch (opc) { case 0: @@ -1361,7 +1383,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) break; case 1: if (bswap) { - tcg_out_bswap16(s, COND_EQ, TCG_REG_R0, data_reg); + tcg_out_bswap16st(s, COND_EQ, TCG_REG_R0, data_reg); tcg_out_st16_r(s, COND_EQ, TCG_REG_R0, addr_reg, TCG_REG_R1); } else { tcg_out_st16_r(s, COND_EQ, data_reg, addr_reg, TCG_REG_R1); @@ -1447,7 +1469,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) break; case 1: if (bswap) { - tcg_out_bswap16(s, COND_AL, TCG_REG_R0, data_reg); + tcg_out_bswap16st(s, COND_AL, TCG_REG_R0, data_reg); tcg_out_st16_8(s, COND_AL, TCG_REG_R0, addr_reg, 0); } else { tcg_out_st16_8(s, COND_AL, data_reg, addr_reg, 0); @@ -1615,7 +1615,7 @@ static inline void temp_dead(TCGContext *s, int temp) if (ts->val_type == TEMP_VAL_REG) { s->reg_to_temp[ts->reg] = -1; } - if (temp < s->nb_globals || (ts->temp_local && ts->mem_allocated)) { + if (temp < s->nb_globals || ts->temp_local) { ts->val_type = TEMP_VAL_MEM; } else { ts->val_type = TEMP_VAL_DEAD; @@ -338,9 +338,9 @@ static uint64_t tci_read_ri64(uint8_t **tb_ptr) } #endif -static target_ulong tci_read_label(uint8_t **tb_ptr) +static tcg_target_ulong tci_read_label(uint8_t **tb_ptr) { - target_ulong label = tci_read_i(tb_ptr); + tcg_target_ulong label = tci_read_i(tb_ptr); assert(label != 0); return label; } @@ -2945,7 +2945,7 @@ void vnc_display_open(DisplayState *ds, const char *display, Error **errp) #endif } else if (strncmp(options, "lossy", 5) == 0) { vs->lossy = true; - } else if (strncmp(options, "non-adapative", 13) == 0) { + } else if (strncmp(options, "non-adaptive", 12) == 0) { vs->non_adaptive = true; } else if (strncmp(options, "share=", 6) == 0) { if (strncmp(options+6, "ignore", 6) == 0) { |