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-rw-r--r--pc-bios/bios-pq/0016-use-correct-mask-to-size-pci-option-rom-bar.patch33
-rw-r--r--pc-bios/bios-pq/series1
-rw-r--r--pc-bios/bios.binbin131072 -> 131072 bytes
3 files changed, 34 insertions, 0 deletions
diff --git a/pc-bios/bios-pq/0016-use-correct-mask-to-size-pci-option-rom-bar.patch b/pc-bios/bios-pq/0016-use-correct-mask-to-size-pci-option-rom-bar.patch
new file mode 100644
index 0000000000..556a0bda79
--- /dev/null
+++ b/pc-bios/bios-pq/0016-use-correct-mask-to-size-pci-option-rom-bar.patch
@@ -0,0 +1,33 @@
+Subject: [PATCH] bios: Use the correct mask to size the PCI option ROM BAR
+From: Alex Williamson <alex.williamson@hp.com>
+
+Bit 0 is the enable bit, which we not only don't want to set, but
+it will stick and make us think it's an I/O port resource.
+
+Signed-off-by: Alex Williamson <alex.williamson@hp.com>
+Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
+---
+
+diff --git a/bios/rombios32.c b/bios/rombios32.c
+index d7e18e9..f861f81 100644
+--- a/bios/rombios32.c
++++ b/bios/rombios32.c
+@@ -985,11 +985,13 @@ static void pci_bios_init_device(PCIDevice *d)
+ int ofs;
+ uint32_t val, size ;
+
+- if (i == PCI_ROM_SLOT)
++ if (i == PCI_ROM_SLOT) {
+ ofs = 0x30;
+- else
++ pci_config_writel(d, ofs, 0xfffffffe);
++ } else {
+ ofs = 0x10 + i * 4;
+- pci_config_writel(d, ofs, 0xffffffff);
++ pci_config_writel(d, ofs, 0xffffffff);
++ }
+ val = pci_config_readl(d, ofs);
+ if (val != 0) {
+ size = (~(val & ~0xf)) + 1;
+
+
diff --git a/pc-bios/bios-pq/series b/pc-bios/bios-pq/series
index aa5a3753ed..c7c7f67e0d 100644
--- a/pc-bios/bios-pq/series
+++ b/pc-bios/bios-pq/series
@@ -13,3 +13,4 @@
0013_fix-non-acpi-timer-interrupt-routing.patch
0014_add-srat-acpi-table-support.patch
0015_enable-power-button-even-generation.patch
+0016-use-correct-mask-to-size-pci-option-rom-bar.patch
diff --git a/pc-bios/bios.bin b/pc-bios/bios.bin
index 8aa5b713ca..6c8bc9f6ce 100644
--- a/pc-bios/bios.bin
+++ b/pc-bios/bios.bin
Binary files differ