aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
Diffstat
-rw-r--r--exec-all.h1
-rw-r--r--target-alpha/cpu.h22
-rw-r--r--target-alpha/exec.h20
-rw-r--r--target-arm/cpu.h13
-rw-r--r--target-arm/exec.h12
-rw-r--r--target-cris/cpu.h11
-rw-r--r--target-cris/exec.h11
-rw-r--r--target-i386/cpu.h47
-rw-r--r--target-i386/exec.h46
-rw-r--r--target-lm32/cpu.h13
-rw-r--r--target-lm32/exec.h11
-rw-r--r--target-m68k/cpu.h12
-rw-r--r--target-m68k/exec.h11
-rw-r--r--target-microblaze/cpu.h13
-rw-r--r--target-microblaze/exec.h11
-rw-r--r--target-mips/cpu.h24
-rw-r--r--target-mips/exec.h22
-rw-r--r--target-ppc/cpu.h12
-rw-r--r--target-ppc/exec.h11
-rw-r--r--target-s390x/cpu.h11
-rw-r--r--target-s390x/exec.h12
-rw-r--r--target-sh4/cpu.h13
-rw-r--r--target-sh4/exec.h11
-rw-r--r--target-sparc/cpu.h14
-rw-r--r--target-sparc/exec.h14
-rw-r--r--target-unicore32/cpu.h6
-rw-r--r--target-unicore32/exec.h6
-rw-r--r--xen-mapcache-stub.c1
28 files changed, 213 insertions, 198 deletions
diff --git a/exec-all.h b/exec-all.h
index efef1cd8ba..21a69d68ad 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -40,6 +40,7 @@ typedef ram_addr_t tb_page_addr_t;
#define DISAS_UPDATE 2 /* cpu state was modified dynamically */
#define DISAS_TB_JUMP 3 /* only pc was modified statically */
+struct TranslationBlock;
typedef struct TranslationBlock TranslationBlock;
/* XXX: make safe guess about sizes */
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
index e98b32513c..411bd55328 100644
--- a/target-alpha/cpu.h
+++ b/target-alpha/cpu.h
@@ -492,4 +492,26 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
}
#endif
+static inline bool cpu_has_work(CPUState *env)
+{
+ /* Here we are checking to see if the CPU should wake up from HALT.
+ We will have gotten into this state only for WTINT from PALmode. */
+ /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
+ asleep even if (some) interrupts have been asserted. For now,
+ assume that if a CPU really wants to stay asleep, it will mask
+ interrupts at the chipset level, which will prevent these bits
+ from being set in the first place. */
+ return env->interrupt_request & (CPU_INTERRUPT_HARD
+ | CPU_INTERRUPT_TIMER
+ | CPU_INTERRUPT_SMP
+ | CPU_INTERRUPT_MCHK);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+}
+
#endif /* !defined (__CPU_ALPHA_H__) */
diff --git a/target-alpha/exec.h b/target-alpha/exec.h
index 0f9b827015..f5089963b8 100644
--- a/target-alpha/exec.h
+++ b/target-alpha/exec.h
@@ -37,24 +37,4 @@ register struct CPUAlphaState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
-static inline bool cpu_has_work(CPUState *env)
-{
- /* Here we are checking to see if the CPU should wake up from HALT.
- We will have gotten into this state only for WTINT from PALmode. */
- /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
- asleep even if (some) interrupts have been asserted. For now,
- assume that if a CPU really wants to stay asleep, it will mask
- interrupts at the chipset level, which will prevent these bits
- from being set in the first place. */
- return env->interrupt_request & (CPU_INTERRUPT_HARD
- | CPU_INTERRUPT_TIMER
- | CPU_INTERRUPT_SMP
- | CPU_INTERRUPT_MCHK);
-}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
#endif /* !defined (__ALPHA_EXEC_H__) */
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 01f5b57fbc..116131eef8 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -512,4 +512,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
}
}
+static inline bool cpu_has_work(CPUState *env)
+{
+ return env->interrupt_request &
+ (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->regs[15] = tb->pc;
+}
+
#endif
diff --git a/target-arm/exec.h b/target-arm/exec.h
index 9c31418a14..007b7cb6df 100644
--- a/target-arm/exec.h
+++ b/target-arm/exec.h
@@ -24,20 +24,8 @@ register struct CPUARMState *env asm(AREG0);
#include "cpu.h"
#include "exec-all.h"
-static inline bool cpu_has_work(CPUState *env)
-{
- return env->interrupt_request &
- (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
-}
-
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
void raise_exception(int);
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->regs[15] = tb->pc;
-}
-
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 2bc35e4975..ecb0df1d33 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -268,4 +268,15 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
#define cpu_list cris_cpu_list
void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf);
+static inline bool cpu_has_work(CPUState *env)
+{
+ return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+}
#endif
diff --git a/target-cris/exec.h b/target-cris/exec.h
index 70d99d184f..9838159172 100644
--- a/target-cris/exec.h
+++ b/target-cris/exec.h
@@ -27,14 +27,3 @@ register struct CPUCRISState *env asm(AREG0);
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
-
-static inline bool cpu_has_work(CPUState *env)
-{
- return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
-}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 656d360716..9819b5fdb9 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -957,6 +957,36 @@ static inline int cpu_mmu_index (CPUState *env)
return (env->hflags & HF_CPL_MASK) == 3 ? 1 : 0;
}
+#undef EAX
+#define EAX (env->regs[R_EAX])
+#undef ECX
+#define ECX (env->regs[R_ECX])
+#undef EDX
+#define EDX (env->regs[R_EDX])
+#undef EBX
+#define EBX (env->regs[R_EBX])
+#undef ESP
+#define ESP (env->regs[R_ESP])
+#undef EBP
+#define EBP (env->regs[R_EBP])
+#undef ESI
+#define ESI (env->regs[R_ESI])
+#undef EDI
+#define EDI (env->regs[R_EDI])
+#undef EIP
+#define EIP (env->eip)
+#define DF (env->df)
+
+#define CC_SRC (env->cc_src)
+#define CC_DST (env->cc_dst)
+#define CC_OP (env->cc_op)
+
+/* float macros */
+#define FT0 (env->ft0)
+#define ST0 (env->fpregs[env->fpstt].d)
+#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
+#define ST1 ST(1)
+
/* translate.c */
void optimize_flags_init(void);
@@ -981,6 +1011,23 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
#include "hw/apic.h"
#endif
+static inline bool cpu_has_work(CPUState *env)
+{
+ return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (env->eflags & IF_MASK)) ||
+ (env->interrupt_request & (CPU_INTERRUPT_NMI |
+ CPU_INTERRUPT_INIT |
+ CPU_INTERRUPT_SIPI |
+ CPU_INTERRUPT_MCE));
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->eip = tb->pc - tb->cs_base;
+}
+
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
diff --git a/target-i386/exec.h b/target-i386/exec.h
index 77bb356d7d..90a6b36882 100644
--- a/target-i386/exec.h
+++ b/target-i386/exec.h
@@ -33,36 +33,6 @@ register struct CPUX86State *env asm(AREG0);
#include "qemu-common.h"
#include "qemu-log.h"
-#undef EAX
-#define EAX (env->regs[R_EAX])
-#undef ECX
-#define ECX (env->regs[R_ECX])
-#undef EDX
-#define EDX (env->regs[R_EDX])
-#undef EBX
-#define EBX (env->regs[R_EBX])
-#undef ESP
-#define ESP (env->regs[R_ESP])
-#undef EBP
-#define EBP (env->regs[R_EBP])
-#undef ESI
-#define ESI (env->regs[R_ESI])
-#undef EDI
-#define EDI (env->regs[R_EDI])
-#undef EIP
-#define EIP (env->eip)
-#define DF (env->df)
-
-#define CC_SRC (env->cc_src)
-#define CC_DST (env->cc_dst)
-#define CC_OP (env->cc_op)
-
-/* float macros */
-#define FT0 (env->ft0)
-#define ST0 (env->fpregs[env->fpstt].d)
-#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
-#define ST1 ST(1)
-
#include "cpu.h"
#include "exec-all.h"
@@ -160,16 +130,6 @@ static inline void load_eflags(int eflags, int update_mask)
(eflags & update_mask) | 0x2;
}
-static inline bool cpu_has_work(CPUState *env)
-{
- return ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
- (env->eflags & IF_MASK)) ||
- (env->interrupt_request & (CPU_INTERRUPT_NMI |
- CPU_INTERRUPT_INIT |
- CPU_INTERRUPT_SIPI |
- CPU_INTERRUPT_MCE));
-}
-
/* load efer and update the corresponding hflags. XXX: do consistency
checks with cpuid bits ? */
static inline void cpu_load_efer(CPUState *env, uint64_t val)
@@ -181,9 +141,3 @@ static inline void cpu_load_efer(CPUState *env, uint64_t val)
if (env->efer & MSR_EFER_SVME)
env->hflags |= HF_SVME_MASK;
}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->eip = tb->pc - tb->cs_base;
-}
-
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 8e2d26b995..876b5be2bd 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -241,4 +241,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
*cs_base = 0;
*flags = 0;
}
+
+static inline bool cpu_has_work(CPUState *env)
+{
+ return env->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+}
+
#endif
diff --git a/target-lm32/exec.h b/target-lm32/exec.h
index 83ddb6587f..61eb914cfa 100644
--- a/target-lm32/exec.h
+++ b/target-lm32/exec.h
@@ -24,11 +24,6 @@ register struct CPULM32State *env asm(AREG0);
#include "cpu.h"
#include "exec-all.h"
-static inline bool cpu_has_work(CPUState *env)
-{
- return env->interrupt_request & CPU_INTERRUPT_HARD;
-}
-
static inline int cpu_halted(CPUState *env)
{
if (!env->halted) {
@@ -42,9 +37,3 @@ static inline int cpu_halted(CPUState *env)
}
return EXCP_HALTED;
}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index 4d8ba287b1..e0f9b32014 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -255,4 +255,16 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
| ((env->macsr >> 4) & 0xf); /* Bits 0-3 */
}
+static inline bool cpu_has_work(CPUState *env)
+{
+ return env->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+}
+
#endif
diff --git a/target-m68k/exec.h b/target-m68k/exec.h
index f7abbf4d26..568260c3dd 100644
--- a/target-m68k/exec.h
+++ b/target-m68k/exec.h
@@ -27,14 +27,3 @@ register struct CPUM68KState *env asm(AREG0);
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
-
-static inline bool cpu_has_work(CPUState *env)
-{
- return env->interrupt_request & (CPU_INTERRUPT_HARD);
-}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
-}
-
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 78fe14ff35..51a13e38d1 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -350,4 +350,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
int is_asi, int size);
#endif
+
+static inline bool cpu_has_work(CPUState *env)
+{
+ return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->sregs[SR_PC] = tb->pc;
+}
+
#endif
diff --git a/target-microblaze/exec.h b/target-microblaze/exec.h
index bb2b7db0b0..b7f85cf3af 100644
--- a/target-microblaze/exec.h
+++ b/target-microblaze/exec.h
@@ -26,14 +26,3 @@ register struct CPUMBState *env asm(AREG0);
#if !defined(CONFIG_USER_ONLY)
#include "softmmu_exec.h"
#endif
-
-static inline bool cpu_has_work(CPUState *env)
-{
- return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
-}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->sregs[SR_PC] = tb->pc;
-}
-
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 0b98d10266..b0ac4da5a7 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -656,4 +656,28 @@ static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
env->tls_value = newtls;
}
+static inline int cpu_has_work(CPUState *env)
+{
+ int has_work = 0;
+
+ /* It is implementation dependent if non-enabled interrupts
+ wake-up the CPU, however most of the implementations only
+ check for interrupts that can be taken. */
+ if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ cpu_mips_hw_interrupts_pending(env)) {
+ has_work = 1;
+ }
+
+ return has_work;
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->active_tc.PC = tb->pc;
+ env->hflags &= ~MIPS_HFLAG_BMASK;
+ env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
+}
+
#endif /* !defined (__MIPS_CPU_H__) */
diff --git a/target-mips/exec.h b/target-mips/exec.h
index e908c3f04b..a3a7262a84 100644
--- a/target-mips/exec.h
+++ b/target-mips/exec.h
@@ -17,21 +17,6 @@ register struct CPUMIPSState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
-static inline bool cpu_has_work(CPUState *env)
-{
- int has_work = 0;
-
- /* It is implementation dependent if non-enabled interrupts
- wake-up the CPU, however most of the implementations only
- check for interrupts that can be taken. */
- if ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
- cpu_mips_hw_interrupts_pending(env)) {
- has_work = 1;
- }
-
- return has_work;
-}
-
static inline void compute_hflags(CPUState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
@@ -73,11 +58,4 @@ static inline void compute_hflags(CPUState *env)
}
}
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->active_tc.PC = tb->pc;
- env->hflags &= ~MIPS_HFLAG_BMASK;
- env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
-}
-
#endif /* !defined(__QEMU_MIPS_EXEC_H__) */
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8e4582f6ab..6d60d14769 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1999,4 +1999,16 @@ static inline ppcemb_tlb_t *booke206_get_tlbe(CPUState *env, const int tlbn,
extern void (*cpu_ppc_hypercall)(CPUState *);
+static inline bool cpu_has_work(CPUState *env)
+{
+ return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->nip = tb->pc;
+}
+
#endif /* !defined (__CPU_PPC_H__) */
diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index 81c3c547f8..1e144bee3b 100644
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -32,15 +32,4 @@ register struct CPUPPCState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
-static inline bool cpu_has_work(CPUState *env)
-{
- return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD);
-}
-
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->nip = tb->pc;
-}
-
#endif /* !defined (__PPC_H__) */
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
index b5e587fbe6..d48a9b7a0c 100644
--- a/target-s390x/cpu.h
+++ b/target-s390x/cpu.h
@@ -962,4 +962,15 @@ static inline void cpu_inject_ext(CPUState *env, uint32_t code, uint32_t param,
cpu_interrupt(env, CPU_INTERRUPT_HARD);
}
+static inline bool cpu_has_work(CPUState *env)
+{
+ return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
+ (env->psw.mask & PSW_MASK_EXT);
+}
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb)
+{
+ env->psw.addr = tb->pc;
+}
+
#endif
diff --git a/target-s390x/exec.h b/target-s390x/exec.h
index 9ababe174f..d40640b675 100644
--- a/target-s390x/exec.h
+++ b/target-s390x/exec.h
@@ -29,12 +29,6 @@ register struct CPUS390XState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
-static inline bool cpu_has_work(CPUState *env)
-{
- return (env->interrupt_request & CPU_INTERRUPT_HARD) &&
- (env->psw.mask & PSW_MASK_EXT);
-}
-
static inline void regs_to_env(void)
{
}
@@ -42,9 +36,3 @@ static inline void regs_to_env(void)
static inline void env_to_regs(void)
{
}
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock* tb)
-{
- env->psw.addr = tb->pc;
-}
-
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 74ff97a908..00e32f2b10 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -361,4 +361,17 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
}
+static inline bool cpu_has_work(CPUState *env)
+{
+ return env->interrupt_request & CPU_INTERRUPT_HARD;
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+ env->flags = tb->flags;
+}
+
#endif /* _CPU_SH4_H */
diff --git a/target-sh4/exec.h b/target-sh4/exec.h
index ff068c550e..a537672981 100644
--- a/target-sh4/exec.h
+++ b/target-sh4/exec.h
@@ -27,19 +27,8 @@ register struct CPUSH4State *env asm(AREG0);
#include "cpu.h"
#include "exec-all.h"
-static inline bool cpu_has_work(CPUState *env)
-{
- return env->interrupt_request & CPU_INTERRUPT_HARD;
-}
-
#ifndef CONFIG_USER_ONLY
#include "softmmu_exec.h"
#endif
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
- env->flags = tb->flags;
-}
-
#endif /* _EXEC_SH4_H */
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 94321f8392..4edae78ca3 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -662,4 +662,18 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
/* helper.c */
void do_interrupt(CPUState *env);
+static inline bool cpu_has_work(CPUState *env1)
+{
+ return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
+ cpu_interrupts_enabled(env1);
+}
+
+#include "exec-all.h"
+
+static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
+{
+ env->pc = tb->pc;
+ env->npc = tb->cs_base;
+}
+
#endif
diff --git a/target-sparc/exec.h b/target-sparc/exec.h
index c1ac2fd8b3..2395b0092f 100644
--- a/target-sparc/exec.h
+++ b/target-sparc/exec.h
@@ -12,18 +12,4 @@ register struct CPUSPARCState *env asm(AREG0);
#include "softmmu_exec.h"
#endif /* !defined(CONFIG_USER_ONLY) */
-/* op_helper.c */
-static inline bool cpu_has_work(CPUState *env1)
-{
- return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
- cpu_interrupts_enabled(env1);
-}
-
-
-static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
-{
- env->pc = tb->pc;
- env->npc = tb->cs_base;
-}
-
#endif
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index 1e10049f89..981760734f 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -179,4 +179,10 @@ void uc32_translate_init(void);
void do_interrupt(CPUState *);
void switch_mode(CPUState_UniCore32 *, int);
+static inline bool cpu_has_work(CPUState *env)
+{
+ return env->interrupt_request &
+ (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
+}
+
#endif /* __CPU_UC32_H__ */
diff --git a/target-unicore32/exec.h b/target-unicore32/exec.h
index ce4132fc89..6b9b499645 100644
--- a/target-unicore32/exec.h
+++ b/target-unicore32/exec.h
@@ -26,12 +26,6 @@ static inline void regs_to_env(void)
{
}
-static inline bool cpu_has_work(CPUState *env)
-{
- return env->interrupt_request &
- (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
-}
-
static inline int cpu_halted(CPUState *env)
{
if (!env->halted) {
diff --git a/xen-mapcache-stub.c b/xen-mapcache-stub.c
index 8a2380a151..5eb3dac366 100644
--- a/xen-mapcache-stub.c
+++ b/xen-mapcache-stub.c
@@ -8,6 +8,7 @@
#include "config.h"
+#include "cpu.h"
#include "exec-all.h"
#include "qemu-common.h"
#include "cpu-common.h"
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-27 06:44:57 +0000