+ image: docker:stable

+ - docker:stable-dind

+ python3 \

+ARM ACPI Subsystem

+M: Shannon Zhao <shannon.zhaosl@gmail.com>

+L: qemu-arm@nongnu.org

+S: Maintained

+F: hw/arm/virt-acpi-build.c

+

+RISC-V ACPI Subsystem

+M: Sunil V L <sunilvl@ventanamicro.com>

+L: qemu-riscv@nongnu.org

+S: Maintained

+F: hw/riscv/virt-acpi-build.c

+

+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml

+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/arm-core.xml gdb-xml/arm-vfp.xml gdb-xml/arm-vfp3.xml gdb-xml/arm-vfp-sysregs.xml gdb-xml/arm-neon.xml gdb-xml/arm-m-profile.xml gdb-xml/arm-m-profile-mve.xml gdb-xml/aarch64-pauth.xml

+TARGET_XML_FILES= gdb-xml/aarch64-core.xml gdb-xml/aarch64-fpu.xml gdb-xml/aarch64-pauth.xml

+ { "ctzw", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },

+ ``smp_mb_acquire()``, ``smp_mb_release()``, ``smp_read_barrier_depends()``,

+ ``smp_mb__before_rmw()``, ``smp_mb__after_rmw()``;

+ the ordering enforced by read-modify-write operations.

+ Fixing this requires a full memory barrier between the write of ``x`` and

+ the read of ``y``. QEMU provides ``smp_mb__before_rmw()`` and

+ ``smp_mb__after_rmw()``; they act both as an optimization,

+ avoiding the memory barrier on processors where it is unnecessary,

+ and as a clarification of this corner case of the C11 memory model:

+

+ +--------------------------------+

+ | QEMU (correct) |

+ +================================+

+ | :: |

+ | |

+ | a = qatomic_fetch_add(&x, 2);|

+ | smp_mb__after_rmw(); |

+ | b = qatomic_read(&y); |

+ +--------------------------------+

+

+ In the common case where only one thread writes ``x``, it is also possible

+ to write it like this:

+<?xml version="1.0"?>

+<!-- Copyright (C) 2018-2022 Free Software Foundation, Inc.

+

+ Copying and distribution of this file, with or without modification,

+ are permitted in any medium without royalty provided the copyright

+ notice and this notice are preserved. -->

+

+<!DOCTYPE feature SYSTEM "gdb-target.dtd">

+<feature name="org.gnu.gdb.aarch64.pauth">

+ <reg name="pauth_dmask" bitsize="64"/>

+ <reg name="pauth_cmask" bitsize="64"/>

+ <reg name="pauth_dmask_high" bitsize="64"/>

+ <reg name="pauth_cmask_high" bitsize="64"/>

+</feature>

+

+ [AW_H3_DEV_TWI1] = 0x01c2b000,

+ [AW_H3_DEV_TWI2] = 0x01c2b400,

+ [AW_H3_DEV_R_TWI] = 0x01f02400,

+ AW_H3_GIC_SPI_TWI1 = 7,

+ AW_H3_GIC_SPI_TWI2 = 8,

+ AW_H3_GIC_SPI_R_TWI = 44,

+ object_initialize_child(obj, "twi0", &s->i2c0, TYPE_AW_I2C_SUN6I);

+ object_initialize_child(obj, "twi1", &s->i2c1, TYPE_AW_I2C_SUN6I);

+ object_initialize_child(obj, "twi2", &s->i2c2, TYPE_AW_I2C_SUN6I);

+ object_initialize_child(obj, "r_twi", &s->r_twi, TYPE_AW_I2C_SUN6I);

+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c1), &error_fatal);

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c1), 0, s->memmap[AW_H3_DEV_TWI1]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c1), 0,

+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI1));

+

+ sysbus_realize(SYS_BUS_DEVICE(&s->i2c2), &error_fatal);

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->i2c2), 0, s->memmap[AW_H3_DEV_TWI2]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c2), 0,

+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TWI2));

+

+ sysbus_realize(SYS_BUS_DEVICE(&s->r_twi), &error_fatal);

+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->r_twi), 0, s->memmap[AW_H3_DEV_R_TWI]);

+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->r_twi), 0,

+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_R_TWI));

+

+

+ /* Unpack the image if it is a EFI zboot image */

+ if (unpack_efi_zboot_image(&buffer, &size) < 0) {

+ g_free(buffer);

+ return -1;

+ }

+

+#via-ac97.c

+via_ac97_codec_write(uint8_t addr, uint16_t val) "0x%x <- 0x%x"

+via_ac97_sgd_fetch(uint32_t curr, uint32_t addr, char stop, char eol, char flag, uint32_t len) "curr=0x%x addr=0x%x %c%c%c len=%d"

+via_ac97_sgd_read(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d -> 0x%"PRIx64

+via_ac97_sgd_write(uint64_t addr, unsigned size, uint64_t val) "0x%"PRIx64" %d <- 0x%"PRIx64

+ * Copyright (c) 2022-2023 BALATON Zoltan

+ *

+ * TODO: This is only a basic implementation of one audio playback channel

+ * more functionality should be added here.

+#include "qemu/log.h"

+#include "ac97.h"

+#include "trace.h"

+

+#define CLEN_IS_EOL(x) ((x)->clen & BIT(31))

+#define CLEN_IS_FLAG(x) ((x)->clen & BIT(30))

+#define CLEN_IS_STOP(x) ((x)->clen & BIT(29))

+#define CLEN_LEN(x) ((x)->clen & 0xffffff)

+

+#define STAT_ACTIVE BIT(7)

+#define STAT_PAUSED BIT(6)

+#define STAT_TRIG BIT(3)

+#define STAT_STOP BIT(2)

+#define STAT_EOL BIT(1)

+#define STAT_FLAG BIT(0)

+

+#define CNTL_START BIT(7)

+#define CNTL_TERM BIT(6)

+#define CNTL_PAUSE BIT(3)

+

+static void open_voice_out(ViaAC97State *s);

+

+static uint16_t codec_rates[] = { 8000, 11025, 16000, 22050, 32000, 44100,

+ 48000 };

+

+#define CODEC_REG(s, o) ((s)->codec_regs[(o) / 2])

+#define CODEC_VOL(vol, mask) ((255 * ((vol) & mask)) / mask)

+

+static void codec_volume_set_out(ViaAC97State *s)

+{

+ int lvol, rvol, mute;

+

+ lvol = 255 - CODEC_VOL(CODEC_REG(s, AC97_Master_Volume_Mute) >> 8, 0x1f);

+ lvol *= 255 - CODEC_VOL(CODEC_REG(s, AC97_PCM_Out_Volume_Mute) >> 8, 0x1f);

+ lvol /= 255;

+ rvol = 255 - CODEC_VOL(CODEC_REG(s, AC97_Master_Volume_Mute), 0x1f);

+ rvol *= 255 - CODEC_VOL(CODEC_REG(s, AC97_PCM_Out_Volume_Mute), 0x1f);

+ rvol /= 255;

+ mute = CODEC_REG(s, AC97_Master_Volume_Mute) >> MUTE_SHIFT;

+ mute |= CODEC_REG(s, AC97_PCM_Out_Volume_Mute) >> MUTE_SHIFT;

+ AUD_set_volume_out(s->vo, mute, lvol, rvol);

+}

+

+static void codec_reset(ViaAC97State *s)

+{

+ memset(s->codec_regs, 0, sizeof(s->codec_regs));

+ CODEC_REG(s, AC97_Reset) = 0x6a90;

+ CODEC_REG(s, AC97_Master_Volume_Mute) = 0x8000;

+ CODEC_REG(s, AC97_Headphone_Volume_Mute) = 0x8000;

+ CODEC_REG(s, AC97_Master_Volume_Mono_Mute) = 0x8000;

+ CODEC_REG(s, AC97_Phone_Volume_Mute) = 0x8008;

+ CODEC_REG(s, AC97_Mic_Volume_Mute) = 0x8008;

+ CODEC_REG(s, AC97_Line_In_Volume_Mute) = 0x8808;

+ CODEC_REG(s, AC97_CD_Volume_Mute) = 0x8808;

+ CODEC_REG(s, AC97_Video_Volume_Mute) = 0x8808;

+ CODEC_REG(s, AC97_Aux_Volume_Mute) = 0x8808;

+ CODEC_REG(s, AC97_PCM_Out_Volume_Mute) = 0x8808;

+ CODEC_REG(s, AC97_Record_Gain_Mute) = 0x8000;

+ CODEC_REG(s, AC97_Powerdown_Ctrl_Stat) = 0x000f;

+ CODEC_REG(s, AC97_Extended_Audio_ID) = 0x0a05;

+ CODEC_REG(s, AC97_Extended_Audio_Ctrl_Stat) = 0x0400;

+ CODEC_REG(s, AC97_PCM_Front_DAC_Rate) = 48000;

+ CODEC_REG(s, AC97_PCM_LR_ADC_Rate) = 48000;

+ /* Sigmatel 9766 (STAC9766) */

+ CODEC_REG(s, AC97_Vendor_ID1) = 0x8384;

+ CODEC_REG(s, AC97_Vendor_ID2) = 0x7666;

+}

+

+static uint16_t codec_read(ViaAC97State *s, uint8_t addr)

+{

+ return CODEC_REG(s, addr);

+}

+

+static void codec_write(ViaAC97State *s, uint8_t addr, uint16_t val)

+{

+ trace_via_ac97_codec_write(addr, val);

+ switch (addr) {

+ case AC97_Reset:

+ codec_reset(s);

+ return;

+ case AC97_Master_Volume_Mute:

+ case AC97_PCM_Out_Volume_Mute:

+ if (addr == AC97_Master_Volume_Mute) {

+ if (val & BIT(13)) {

+ val |= 0x1f00;

+ }

+ if (val & BIT(5)) {

+ val |= 0x1f;

+ }

+ }

+ CODEC_REG(s, addr) = val & 0x9f1f;

+ codec_volume_set_out(s);

+ return;

+ case AC97_Extended_Audio_Ctrl_Stat:

+ CODEC_REG(s, addr) &= ~EACS_VRA;

+ CODEC_REG(s, addr) |= val & EACS_VRA;

+ if (!(val & EACS_VRA)) {

+ CODEC_REG(s, AC97_PCM_Front_DAC_Rate) = 48000;

+ CODEC_REG(s, AC97_PCM_LR_ADC_Rate) = 48000;

+ open_voice_out(s);

+ }

+ return;

+ case AC97_PCM_Front_DAC_Rate:

+ case AC97_PCM_LR_ADC_Rate:

+ if (CODEC_REG(s, AC97_Extended_Audio_Ctrl_Stat) & EACS_VRA) {

+ int i;

+ uint16_t rate = val;

+

+ for (i = 0; i < ARRAY_SIZE(codec_rates) - 1; i++) {

+ if (rate < codec_rates[i] +

+ (codec_rates[i + 1] - codec_rates[i]) / 2) {

+ rate = codec_rates[i];

+ break;

+ }

+ }

+ if (rate > 48000) {

+ rate = 48000;

+ }

+ CODEC_REG(s, addr) = rate;

+ open_voice_out(s);

+ }

+ return;

+ case AC97_Powerdown_Ctrl_Stat:

+ CODEC_REG(s, addr) = (val & 0xff00) | (CODEC_REG(s, addr) & 0xff);

+ return;

+ case AC97_Extended_Audio_ID:

+ case AC97_Vendor_ID1:

+ case AC97_Vendor_ID2:

+ /* Read only registers */

+ return;

+ default:

+ qemu_log_mask(LOG_UNIMP,

+ "via-ac97: Unimplemented codec register 0x%x\n", addr);

+ CODEC_REG(s, addr) = val;

+ }

+}

+

+static void fetch_sgd(ViaAC97SGDChannel *c, PCIDevice *d)

+{

+ uint32_t b[2];

+

+ if (c->curr < c->base) {

+ c->curr = c->base;

+ }

+ if (unlikely(pci_dma_read(d, c->curr, b, sizeof(b)) != MEMTX_OK)) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "via-ac97: DMA error reading SGD table\n");

+ return;

+ }

+ c->addr = le32_to_cpu(b[0]);

+ c->clen = le32_to_cpu(b[1]);

+ trace_via_ac97_sgd_fetch(c->curr, c->addr, CLEN_IS_STOP(c) ? 'S' : '-',

+ CLEN_IS_EOL(c) ? 'E' : '-',

+ CLEN_IS_FLAG(c) ? 'F' : '-', CLEN_LEN(c));

+}

+

+static void out_cb(void *opaque, int avail)

+{

+ ViaAC97State *s = opaque;

+ ViaAC97SGDChannel *c = &s->aur;

+ int temp, to_copy, copied;

+ bool stop = false;

+ uint8_t tmpbuf[4096];

+

+ if (c->stat & STAT_PAUSED) {

+ return;

+ }

+ c->stat |= STAT_ACTIVE;

+ while (avail && !stop) {

+ if (!c->clen) {

+ fetch_sgd(c, &s->dev);

+ }

+ temp = MIN(CLEN_LEN(c), avail);

+ while (temp) {

+ to_copy = MIN(temp, sizeof(tmpbuf));

+ pci_dma_read(&s->dev, c->addr, tmpbuf, to_copy);

+ copied = AUD_write(s->vo, tmpbuf, to_copy);

+ if (!copied) {

+ stop = true;

+ break;

+ }

+ temp -= copied;

+ avail -= copied;

+ c->addr += copied;

+ c->clen -= copied;

+ }

+ if (CLEN_LEN(c) == 0) {

+ c->curr += 8;

+ if (CLEN_IS_EOL(c)) {

+ c->stat |= STAT_EOL;

+ if (c->type & CNTL_START) {

+ c->curr = c->base;

+ c->stat |= STAT_PAUSED;

+ } else {

+ c->stat &= ~STAT_ACTIVE;

+ AUD_set_active_out(s->vo, 0);

+ }

+ if (c->type & STAT_EOL) {

+ pci_set_irq(&s->dev, 1);

+ }

+ }

+ if (CLEN_IS_FLAG(c)) {

+ c->stat |= STAT_FLAG;

+ c->stat |= STAT_PAUSED;

+ if (c->type & STAT_FLAG) {

+ pci_set_irq(&s->dev, 1);

+ }

+ }

+ if (CLEN_IS_STOP(c)) {

+ c->stat |= STAT_STOP;

+ c->stat |= STAT_PAUSED;

+ }

+ c->clen = 0;

+ stop = true;

+ }

+ }

+}

+

+static void open_voice_out(ViaAC97State *s)

+{

+ struct audsettings as = {

+ .freq = CODEC_REG(s, AC97_PCM_Front_DAC_Rate),

+ .nchannels = s->aur.type & BIT(4) ? 2 : 1,

+ .fmt = s->aur.type & BIT(5) ? AUDIO_FORMAT_S16 : AUDIO_FORMAT_S8,

+ .endianness = 0,

+ };

+ s->vo = AUD_open_out(&s->card, s->vo, "via-ac97.out", s, out_cb, &as);

+}

+

+static uint64_t sgd_read(void *opaque, hwaddr addr, unsigned size)

+{

+ ViaAC97State *s = opaque;

+ uint64_t val = 0;

+

+ switch (addr) {

+ case 0:

+ val = s->aur.stat;

+ if (s->aur.type & CNTL_START) {

+ val |= STAT_TRIG;

+ }

+ break;

+ case 1:

+ val = s->aur.stat & STAT_PAUSED ? BIT(3) : 0;

+ break;

+ case 2:

+ val = s->aur.type;

+ break;

+ case 4:

+ val = s->aur.curr;

+ break;

+ case 0xc:

+ val = CLEN_LEN(&s->aur);

+ break;

+ case 0x10:

+ /* silence unimplemented log message that happens at every IRQ */

+ break;

+ case 0x80:

+ val = s->ac97_cmd;

+ break;

+ case 0x84:

+ val = s->aur.stat & STAT_FLAG;

+ if (s->aur.stat & STAT_EOL) {

+ val |= BIT(4);

+ }

+ if (s->aur.stat & STAT_STOP) {

+ val |= BIT(8);

+ }

+ if (s->aur.stat & STAT_ACTIVE) {

+ val |= BIT(12);

+ }

+ break;

+ default:

+ qemu_log_mask(LOG_UNIMP, "via-ac97: Unimplemented register read 0x%"

+ HWADDR_PRIx"\n", addr);

+ }

+ trace_via_ac97_sgd_read(addr, size, val);

+ return val;

+}

+

+static void sgd_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)

+{

+ ViaAC97State *s = opaque;

+

+ trace_via_ac97_sgd_write(addr, size, val);

+ switch (addr) {

+ case 0:

+ if (val & STAT_STOP) {

+ s->aur.stat &= ~STAT_PAUSED;

+ }

+ if (val & STAT_EOL) {

+ s->aur.stat &= ~(STAT_EOL | STAT_PAUSED);

+ if (s->aur.type & STAT_EOL) {

+ pci_set_irq(&s->dev, 0);

+ }

+ }

+ if (val & STAT_FLAG) {

+ s->aur.stat &= ~(STAT_FLAG | STAT_PAUSED);

+ if (s->aur.type & STAT_FLAG) {

+ pci_set_irq(&s->dev, 0);

+ }

+ }

+ break;

+ case 1:

+ if (val & CNTL_START) {

+ AUD_set_active_out(s->vo, 1);

+ s->aur.stat = STAT_ACTIVE;

+ }

+ if (val & CNTL_TERM) {

+ AUD_set_active_out(s->vo, 0);

+ s->aur.stat &= ~(STAT_ACTIVE | STAT_PAUSED);

+ s->aur.clen = 0;

+ }

+ if (val & CNTL_PAUSE) {

+ AUD_set_active_out(s->vo, 0);

+ s->aur.stat &= ~STAT_ACTIVE;

+ s->aur.stat |= STAT_PAUSED;

+ } else if (!(val & CNTL_PAUSE) && (s->aur.stat & STAT_PAUSED)) {

+ AUD_set_active_out(s->vo, 1);

+ s->aur.stat |= STAT_ACTIVE;

+ s->aur.stat &= ~STAT_PAUSED;

+ }

+ break;

+ case 2:

+ {

+ uint32_t oldval = s->aur.type;

+ s->aur.type = val;

+ if ((oldval & 0x30) != (val & 0x30)) {

+ open_voice_out(s);

+ }

+ break;

+ }

+ case 4:

+ s->aur.base = val & ~1ULL;

+ s->aur.curr = s->aur.base;

+ break;

+ case 0x80:

+ if (val >> 30) {

+ /* we only have primary codec */

+ break;

+ }

+ if (val & BIT(23)) { /* read reg */

+ s->ac97_cmd = val & 0xc0ff0000ULL;

+ s->ac97_cmd |= codec_read(s, (val >> 16) & 0x7f);

+ s->ac97_cmd |= BIT(25); /* data valid */

+ } else {

+ s->ac97_cmd = val & 0xc0ffffffULL;

+ codec_write(s, (val >> 16) & 0x7f, val);

+ }

+ break;

+ case 0xc:

+ case 0x84:

+ /* Read only */

+ break;

+ default:

+ qemu_log_mask(LOG_UNIMP, "via-ac97: Unimplemented register write 0x%"

+ HWADDR_PRIx"\n", addr);

+ }

+}

+

+static const MemoryRegionOps sgd_ops = {

+ .read = sgd_read,

+ .write = sgd_write,

+ .endianness = DEVICE_LITTLE_ENDIAN,

+};

+

+static uint64_t fm_read(void *opaque, hwaddr addr, unsigned size)

+{

+ qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d\n", __func__, addr, size);

+ return 0;

+}

+

+static void fm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)

+{

+ qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d <= 0x%"PRIX64"\n",

+ __func__, addr, size, val);

+}

+

+static const MemoryRegionOps fm_ops = {

+ .read = fm_read,

+ .write = fm_write,

+ .endianness = DEVICE_LITTLE_ENDIAN,

+};

+

+static uint64_t midi_read(void *opaque, hwaddr addr, unsigned size)

+{

+ qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d\n", __func__, addr, size);

+ return 0;

+}

+

+static void midi_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)

+{

+ qemu_log_mask(LOG_UNIMP, "%s: 0x%"HWADDR_PRIx" %d <= 0x%"PRIX64"\n",

+ __func__, addr, size, val);

+}

+

+static const MemoryRegionOps midi_ops = {

+ .read = midi_read,

+ .write = midi_write,

+ .endianness = DEVICE_LITTLE_ENDIAN,

+};

+

+static void via_ac97_reset(DeviceState *dev)

+{

+ ViaAC97State *s = VIA_AC97(dev);

+

+ codec_reset(s);

+}

+ ViaAC97State *s = VIA_AC97(pci_dev);

+ Object *o = OBJECT(s);

+

+ /*

+ * Command register Bus Master bit is documented to be fixed at 0 but it's

+ * needed for PCI DMA to work in QEMU. The pegasos2 firmware writes 0 here

+ * and the AmigaOS driver writes 1 only enabling IO bit which works on

+ * real hardware. So set it here and fix it to 1 to allow DMA.

+ */

+ pci_set_word(pci_dev->config + PCI_COMMAND, PCI_COMMAND_MASTER);

+ pci_set_word(pci_dev->wmask + PCI_COMMAND, PCI_COMMAND_IO);

+ pci_set_byte(pci_dev->config + 0x40, 1); /* codec ready */

+

+ memory_region_init_io(&s->sgd, o, &sgd_ops, s, "via-ac97.sgd", 256);

+ pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->sgd);

+ memory_region_init_io(&s->fm, o, &fm_ops, s, "via-ac97.fm", 4);

+ pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->fm);

+ memory_region_init_io(&s->midi, o, &midi_ops, s, "via-ac97.midi", 4);

+ pci_register_bar(pci_dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->midi);

+

+ AUD_register_card ("via-ac97", &s->card);

+static void via_ac97_exit(PCIDevice *dev)

+{

+ ViaAC97State *s = VIA_AC97(dev);

+

+ AUD_close_out(&s->card, s->vo);

+ AUD_remove_card(&s->card);

+}

+

+static Property via_ac97_properties[] = {

+ DEFINE_AUDIO_PROPERTIES(ViaAC97State, card),

+ DEFINE_PROP_END_OF_LIST(),

+};

+

+ k->exit = via_ac97_exit;

+ device_class_set_props(dc, via_ac97_properties);

+ dc->reset = via_ac97_reset;

+ .instance_size = sizeof(ViaAC97State),

+/* The PE/COFF MS-DOS stub magic number */

+#define EFI_PE_MSDOS_MAGIC "MZ"

+

+/*

+ * The Linux header magic number for a EFI PE/COFF

+ * image targetting an unspecified architecture.

+ */

+#define EFI_PE_LINUX_MAGIC "\xcd\x23\x82\x81"

+

+/*

+ * Bootable Linux kernel images may be packaged as EFI zboot images, which are

+ * self-decompressing executables when loaded via EFI. The compressed payload

+ * can also be extracted from the image and decompressed by a non-EFI loader.

+ *

+ * The de facto specification for this format is at the following URL:

+ *

+ * https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/firmware/efi/libstub/zboot-header.S

+ *

+ * This definition is based on Linux upstream commit 29636a5ce87beba.

+ */

+struct linux_efi_zboot_header {

+ uint8_t msdos_magic[2]; /* PE/COFF 'MZ' magic number */

+ uint8_t reserved0[2];

+ uint8_t zimg[4]; /* "zimg" for Linux EFI zboot images */

+ uint32_t payload_offset; /* LE offset to compressed payload */

+ uint32_t payload_size; /* LE size of the compressed payload */

+ uint8_t reserved1[8];

+ char compression_type[32]; /* Compression type, NUL terminated */

+ uint8_t linux_magic[4]; /* Linux header magic */

+ uint32_t pe_header_offset; /* LE offset to the PE header */

+};

+

+/*

+ * Check whether *buffer points to a Linux EFI zboot image in memory.

+ *

+ * If it does, attempt to decompress it to a new buffer, and free the old one.

+ * If any of this fails, return an error to the caller.

+ *

+ * If the image is not a Linux EFI zboot image, do nothing and return success.

+ */

+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size)

+{

+ const struct linux_efi_zboot_header *header;

+ uint8_t *data = NULL;

+ int ploff, plsize;

+ ssize_t bytes;

+

+ /* ignore if this is too small to be a EFI zboot image */

+ if (*size < sizeof(*header)) {

+ return 0;

+ }

+

+ header = (struct linux_efi_zboot_header *)*buffer;

+

+ /* ignore if this is not a Linux EFI zboot image */

+ if (memcmp(&header->msdos_magic, EFI_PE_MSDOS_MAGIC, 2) != 0 ||

+ memcmp(&header->zimg, "zimg", 4) != 0 ||

+ memcmp(&header->linux_magic, EFI_PE_LINUX_MAGIC, 4) != 0) {

+ return 0;

+ }

+

+ if (strcmp(header->compression_type, "gzip") != 0) {

+ fprintf(stderr,

+ "unable to handle EFI zboot image with \"%.*s\" compression\n",

+ (int)sizeof(header->compression_type) - 1,

+ header->compression_type);

+ return -1;

+ }

+

+ ploff = ldl_le_p(&header->payload_offset);

+ plsize = ldl_le_p(&header->payload_size);

+

+ if (ploff < 0 || plsize < 0 || ploff + plsize > *size) {

+ fprintf(stderr, "unable to handle corrupt EFI zboot image\n");

+ return -1;

+ }

+

+ data = g_malloc(LOAD_IMAGE_MAX_GUNZIP_BYTES);

+ bytes = gunzip(data, LOAD_IMAGE_MAX_GUNZIP_BYTES, *buffer + ploff, plsize);

+ if (bytes < 0) {

+ fprintf(stderr, "failed to decompress EFI zboot image\n");

+ g_free(data);

+ return -1;

+ }

+

+ g_free(*buffer);

+ *buffer = g_realloc(data, bytes);

+ *size = bytes;

+ return bytes;

+}

+

+ uint8_t use_pixman;

+ if (overlap && (s->use_pixman & BIT(2))) {

+ } else if (!overlap && (s->use_pixman & BIT(1))) {

+ } else {

+ fallback = true;

+ if (!(s->use_pixman & BIT(0)) || (width == 1 && height == 1) ||

+ DEFINE_PROP_UINT8("x-pixman", SM501SysBusState, state.use_pixman, 7),

+ DEFINE_PROP_UINT8("x-pixman", SM501PCIState, state.use_pixman, 7),

+static void sm501_pci_init(Object *o)

+{

+ object_property_set_description(o, "x-pixman", "Use pixman for: "

+ "1: fill, 2: blit, 4: overlap blit");

+}

+

+ .instance_init = sm501_pci_init,

+

+ if (!s->irq_clear_inverted && !(s->cntr & TWI_CNTR_INT_FLAG)) {

+ /* Write 0 to clear this flag */

+ qemu_irq_lower(s->irq);

+ } else if (s->irq_clear_inverted && (s->cntr & TWI_CNTR_INT_FLAG)) {

+ /* Write 1 to clear this flag */

+ s->cntr &= ~TWI_CNTR_INT_FLAG;

+

+static void allwinner_i2c_sun6i_init(Object *obj)

+{

+ AWI2CState *s = AW_I2C(obj);

+

+ s->irq_clear_inverted = true;

+}

+

+static const TypeInfo allwinner_i2c_sun6i_type_info = {

+ .name = TYPE_AW_I2C_SUN6I,

+ .parent = TYPE_SYS_BUS_DEVICE,

+ .instance_size = sizeof(AWI2CState),

+ .instance_init = allwinner_i2c_sun6i_init,

+ .class_init = allwinner_i2c_class_init,

+};

+

+ type_register_static(&allwinner_i2c_sun6i_type_info);

+ xen_igd_reserve_slot(pcms->bus);

+ if (s->ltim || (s->elcr & mask)) {

+ if (!s->ltim && !(s->elcr & (1 << irq))) {

+ s->ltim = 0;

+ s->ltim = val & 8;

+ /* Note: ELCR and LTIM are not reset */

+static bool ltim_state_needed(void *opaque)

+{

+ PICCommonState *s = PIC_COMMON(opaque);

+

+ return !!s->ltim;

+}

+

+static const VMStateDescription vmstate_pic_ltim = {

+ .name = "i8259/ltim",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .needed = ltim_state_needed,

+ .fields = (VMStateField[]) {

+ VMSTATE_UINT8(ltim, PICCommonState),

+ VMSTATE_END_OF_LIST()

+ }

+};

+

+ },

+ .subsections = (const VMStateDescription*[]) {

+ &vmstate_pic_ltim,

+ NULL

+ DEFINE_PROP_UINT32("num-vp", MIPSGICState, num_vps, 1),

+ DEFINE_PROP_UINT32("num-irq", MIPSGICState, num_irq, 256),

+ CPUState *cpu = cpu_by_arch_id(hartid);

+ CPUState *cpu = cpu_by_arch_id(hartid);

+ CPUState *cpu = cpu_by_arch_id(mtimer->hartid_base + i);

+ RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(s->hartid_base + i));

+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);

+ CPUState *cpu = cpu_by_arch_id(hartid);

+ CPUState *cpu = cpu_by_arch_id(hartid);

+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);

+ RISCVCPU *cpu = RISCV_CPU(cpu_by_arch_id(aplic->hartid_base + i));

+ CPUState *cpu = cpu_by_arch_id(hartid_base + i);

+ RISCVCPU *rcpu = RISCV_CPU(cpu_by_arch_id(imsic->hartid));

+ CPUState *cpu = cpu_by_arch_id(imsic->hartid);

+ CPUState *cpu = cpu_by_arch_id(hartid);

+static void i82378_request_out0_irq(void *opaque, int irq, int level)

+{

+ I82378State *s = opaque;

+ qemu_set_irq(s->cpu_intr, level);

+}

+

+ s->isa_irqs_in = i8259_init(isabus,

+ qemu_allocate_irq(i82378_request_out0_irq,

+ s, 0));

+via_pm_read(uint32_t addr, uint32_t val, int len) "addr 0x%x val 0x%x len 0x%x"

+ ViaAC97State ac97;

+static void via_isa_request_i8259_irq(void *opaque, int irq, int level)

+{

+ ViaISAState *s = opaque;

+ qemu_set_irq(s->cpu_intr, level);

+}

+

+static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num)

+{

+ switch (irq_num) {

+ case 0:

+ return s->dev.config[0x55] >> 4;

+ case 1:

+ return s->dev.config[0x56] & 0xf;

+ case 2:

+ return s->dev.config[0x56] >> 4;

+ case 3:

+ return s->dev.config[0x57] >> 4;

+ }

+ return 0;

+}

+

+static void via_isa_set_pci_irq(void *opaque, int irq_num, int level)

+{

+ ViaISAState *s = opaque;

+ PCIBus *bus = pci_get_bus(&s->dev);

+ int i, pic_level, pic_irq = via_isa_get_pci_irq(s, irq_num);

+

+ /* IRQ 0: disabled, IRQ 2,8,13: reserved */

+ if (!pic_irq) {

+ return;

+ }

+ if (unlikely(pic_irq == 2 || pic_irq == 8 || pic_irq == 13)) {

+ qemu_log_mask(LOG_GUEST_ERROR, "Invalid ISA IRQ routing");

+ }

+

+ /* The pic level is the logical OR of all the PCI irqs mapped to it. */

+ pic_level = 0;

+ for (i = 0; i < PCI_NUM_PINS; i++) {

+ if (pic_irq == via_isa_get_pci_irq(s, i)) {

+ pic_level |= pci_bus_get_irq_level(bus, i);

+ }

+ }

+ /* Now we change the pic irq level according to the via irq mappings. */

+ qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level);

+}

+

+ qemu_irq *isa_irq;

+ isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1);

+ s->isa_irqs_in = i8259_init(isa_bus, *isa_irq);

+ qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM_PINS);

+

+ object_property_set_uint(OBJECT(&s->cps), "num-vp", machine->smp.cpus,

+ for (int i = 0; i < s->num_vp; i++) {

+ MIPSCPU *cpu = MIPS_CPU(object_new(s->cpu_type));

+ CPUMIPSState *env = &cpu->env;

+ object_property_set_link(OBJECT(&s->itu), "cpu[0]",

+ OBJECT(first_cpu), &error_abort);

+ object_property_set_uint(OBJECT(&s->itu), "num-fifo", 16,

+ object_property_set_uint(OBJECT(&s->itu), "num-semaphores", 16,

+ object_property_set_uint(OBJECT(&s->cpc), "num-vp", s->num_vp,

+ object_property_set_uint(OBJECT(&s->gic), "num-vp", s->num_vp,

+ object_property_set_uint(OBJECT(&s->gic), "num-irq", 128,

+ gcr_base = MIPS_CPU(first_cpu)->env.CP0_CMGCRBase << 4;

+ object_property_set_uint(OBJECT(&s->gcr), "num-vp", s->num_vp,

+ object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,

+ /* Order check of the COMPUTING flag after setting IRQFACT. */

+ smp_mb__after_rmw();

+ /* Clear COMPUTING flag before checking IRQFACT. */

+ smp_mb__after_rmw();

+

+ DEFINE_PROP_UINT32("num-vp", MIPSGCRState, num_vps, 1),

+ if (tag->saar) {

+ address = (tag->saar[0] & 0xFFFFFFFFE000ULL) << 4;

+ size = 1ULL << ((tag->saar[0] >> 1) & 0x1f);

+ is_enabled = tag->saar[0] & 1;

+ if (s->saar) {

+ CPUMIPSState *env;

+ if (!s->cpu0) {

+ error_setg(errp, "Missing 'cpu[0]' property");

+ return;

+ }

+

+ env = &s->cpu0->env;

+ if (env->saarp) {

+ s->saar = env->CP0_SAAR;

+ }

+ if (s->saar) {

+ s->saar[0] = 0x11 << 1;

+ DEFINE_PROP_UINT32("num-fifo", MIPSITUState, num_fifo,

+ DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores,

+ DEFINE_PROP_LINK("cpu[0]", MIPSITUState, cpu0, TYPE_MIPS_CPU, MIPSCPU *),

+ [NVME_FDP_MODE] = true,

+ [NVME_FDP_EVENTS] = true,

+ [NVME_FDP_MODE] = NVME_FEAT_CAP_CHANGE,

+ [NVME_FDP_EVENTS] = NVME_FEAT_CAP_CHANGE | NVME_FEAT_CAP_NS,

+ [NVME_ADM_CMD_DIRECTIVE_RECV] = NVME_CMD_EFF_CSUPP,

+ [NVME_ADM_CMD_DIRECTIVE_SEND] = NVME_CMD_EFF_CSUPP,

+ [NVME_CMD_IO_MGMT_RECV] = NVME_CMD_EFF_CSUPP,

+ [NVME_CMD_IO_MGMT_SEND] = NVME_CMD_EFF_CSUPP | NVME_CMD_EFF_LBCC,

+static inline uint64_t nvme_get_timestamp(const NvmeCtrl *n);

+static inline uint16_t nvme_make_pid(NvmeNamespace *ns, uint16_t rg,

+ uint16_t ph)

+{

+ uint16_t rgif = ns->endgrp->fdp.rgif;

+

+ if (!rgif) {

+ return ph;

+ }

+

+ return (rg << (16 - rgif)) | ph;

+}

+

+static inline bool nvme_ph_valid(NvmeNamespace *ns, uint16_t ph)

+{

+ return ph < ns->fdp.nphs;

+}

+

+static inline bool nvme_rg_valid(NvmeEnduranceGroup *endgrp, uint16_t rg)

+{

+ return rg < endgrp->fdp.nrg;

+}

+

+static inline uint16_t nvme_pid2ph(NvmeNamespace *ns, uint16_t pid)

+{

+ uint16_t rgif = ns->endgrp->fdp.rgif;

+

+ if (!rgif) {

+ return pid;

+ }

+

+ return pid & ((1 << (15 - rgif)) - 1);

+}

+

+static inline uint16_t nvme_pid2rg(NvmeNamespace *ns, uint16_t pid)

+{

+ uint16_t rgif = ns->endgrp->fdp.rgif;

+

+ if (!rgif) {

+ return 0;

+ }

+

+ return pid >> (16 - rgif);

+}

+

+static inline bool nvme_parse_pid(NvmeNamespace *ns, uint16_t pid,

+ uint16_t *ph, uint16_t *rg)

+{

+ *rg = nvme_pid2rg(ns, pid);

+ *ph = nvme_pid2ph(ns, pid);

+

+ return nvme_ph_valid(ns, *ph) && nvme_rg_valid(ns->endgrp, *rg);

+}

+

+static NvmeFdpEvent *nvme_fdp_alloc_event(NvmeCtrl *n, NvmeFdpEventBuffer *ebuf)

+{

+ NvmeFdpEvent *ret = NULL;

+ bool is_full = ebuf->next == ebuf->start && ebuf->nelems;

+

+ ret = &ebuf->events[ebuf->next++];

+ if (unlikely(ebuf->next == NVME_FDP_MAX_EVENTS)) {

+ ebuf->next = 0;

+ }

+ if (is_full) {

+ ebuf->start = ebuf->next;

+ } else {

+ ebuf->nelems++;

+ }

+

+ memset(ret, 0, sizeof(NvmeFdpEvent));

+ ret->timestamp = nvme_get_timestamp(n);

+

+ return ret;

+}

+

+static inline int log_event(NvmeRuHandle *ruh, uint8_t event_type)

+{

+ return (ruh->event_filter >> nvme_fdp_evf_shifts[event_type]) & 0x1;

+}

+

+static bool nvme_update_ruh(NvmeCtrl *n, NvmeNamespace *ns, uint16_t pid)

+{

+ NvmeEnduranceGroup *endgrp = ns->endgrp;

+ NvmeRuHandle *ruh;

+ NvmeReclaimUnit *ru;

+ NvmeFdpEvent *e = NULL;

+ uint16_t ph, rg, ruhid;

+

+ if (!nvme_parse_pid(ns, pid, &ph, &rg)) {

+ return false;

+ }

+

+ ruhid = ns->fdp.phs[ph];

+

+ ruh = &endgrp->fdp.ruhs[ruhid];

+ ru = &ruh->rus[rg];

+

+ if (ru->ruamw) {

+ if (log_event(ruh, FDP_EVT_RU_NOT_FULLY_WRITTEN)) {

+ e = nvme_fdp_alloc_event(n, &endgrp->fdp.host_events);

+ e->type = FDP_EVT_RU_NOT_FULLY_WRITTEN;

+ e->flags = FDPEF_PIV | FDPEF_NSIDV | FDPEF_LV;

+ e->pid = cpu_to_le16(pid);

+ e->nsid = cpu_to_le32(ns->params.nsid);

+ e->rgid = cpu_to_le16(rg);

+ e->ruhid = cpu_to_le16(ruhid);

+ }

+

+ /* log (eventual) GC overhead of prematurely swapping the RU */

+ nvme_fdp_stat_inc(&endgrp->fdp.mbmw, nvme_l2b(ns, ru->ruamw));

+ }

+

+ ru->ruamw = ruh->ruamw;

+

+ return true;

+}

+

+static void nvme_do_write_fdp(NvmeCtrl *n, NvmeRequest *req, uint64_t slba,

+ uint32_t nlb)

+{

+ NvmeNamespace *ns = req->ns;

+ NvmeRwCmd *rw = (NvmeRwCmd *)&req->cmd;

+ uint64_t data_size = nvme_l2b(ns, nlb);

+ uint32_t dw12 = le32_to_cpu(req->cmd.cdw12);

+ uint8_t dtype = (dw12 >> 20) & 0xf;

+ uint16_t pid = le16_to_cpu(rw->dspec);

+ uint16_t ph, rg, ruhid;

+ NvmeReclaimUnit *ru;

+

+ if (dtype != NVME_DIRECTIVE_DATA_PLACEMENT ||

+ !nvme_parse_pid(ns, pid, &ph, &rg)) {

+ ph = 0;

+ rg = 0;

+ }

+

+ ruhid = ns->fdp.phs[ph];

+ ru = &ns->endgrp->fdp.ruhs[ruhid].rus[rg];

+

+ nvme_fdp_stat_inc(&ns->endgrp->fdp.hbmw, data_size);

+ nvme_fdp_stat_inc(&ns->endgrp->fdp.mbmw, data_size);

+

+ while (nlb) {

+ if (nlb < ru->ruamw) {

+ ru->ruamw -= nlb;

+ break;

+ }

+

+ nlb -= ru->ruamw;

+ nvme_update_ruh(n, ns, pid);

+ }

+}

+

+ } else if (ns->endgrp && ns->endgrp->fdp.enabled) {

+ nvme_do_write_fdp(n, req, slba, nlb);

+static uint16_t nvme_io_mgmt_recv_ruhs(NvmeCtrl *n, NvmeRequest *req,

+ size_t len)

+{

+ NvmeNamespace *ns = req->ns;

+ NvmeEnduranceGroup *endgrp;

+ NvmeRuhStatus *hdr;

+ NvmeRuhStatusDescr *ruhsd;

+ unsigned int nruhsd;

+ uint16_t rg, ph, *ruhid;

+ size_t trans_len;

+ g_autofree uint8_t *buf = NULL;

+

+ if (!n->subsys) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ if (ns->params.nsid == 0 || ns->params.nsid == 0xffffffff) {

+ return NVME_INVALID_NSID | NVME_DNR;

+ }

+

+ if (!n->subsys->endgrp.fdp.enabled) {

+ return NVME_FDP_DISABLED | NVME_DNR;

+ }

+

+ endgrp = ns->endgrp;

+

+ nruhsd = ns->fdp.nphs * endgrp->fdp.nrg;

+ trans_len = sizeof(NvmeRuhStatus) + nruhsd * sizeof(NvmeRuhStatusDescr);

+ buf = g_malloc(trans_len);

+

+ trans_len = MIN(trans_len, len);

+

+ hdr = (NvmeRuhStatus *)buf;

+ ruhsd = (NvmeRuhStatusDescr *)(buf + sizeof(NvmeRuhStatus));

+

+ hdr->nruhsd = cpu_to_le16(nruhsd);

+

+ ruhid = ns->fdp.phs;

+

+ for (ph = 0; ph < ns->fdp.nphs; ph++, ruhid++) {

+ NvmeRuHandle *ruh = &endgrp->fdp.ruhs[*ruhid];

+

+ for (rg = 0; rg < endgrp->fdp.nrg; rg++, ruhsd++) {

+ uint16_t pid = nvme_make_pid(ns, rg, ph);

+

+ ruhsd->pid = cpu_to_le16(pid);

+ ruhsd->ruhid = *ruhid;

+ ruhsd->earutr = 0;

+ ruhsd->ruamw = cpu_to_le64(ruh->rus[rg].ruamw);

+ }

+ }

+

+ return nvme_c2h(n, buf, trans_len, req);

+}

+

+static uint16_t nvme_io_mgmt_recv(NvmeCtrl *n, NvmeRequest *req)

+{

+ NvmeCmd *cmd = &req->cmd;

+ uint32_t cdw10 = le32_to_cpu(cmd->cdw10);

+ uint32_t numd = le32_to_cpu(cmd->cdw11);

+ uint8_t mo = (cdw10 & 0xff);

+ size_t len = (numd + 1) << 2;

+

+ switch (mo) {

+ case NVME_IOMR_MO_NOP:

+ return 0;

+ case NVME_IOMR_MO_RUH_STATUS:

+ return nvme_io_mgmt_recv_ruhs(n, req, len);

+ default:

+ return NVME_INVALID_FIELD | NVME_DNR;

+ };

+}

+

+static uint16_t nvme_io_mgmt_send_ruh_update(NvmeCtrl *n, NvmeRequest *req)

+{

+ NvmeCmd *cmd = &req->cmd;

+ NvmeNamespace *ns = req->ns;

+ uint32_t cdw10 = le32_to_cpu(cmd->cdw10);

+ uint16_t ret = NVME_SUCCESS;

+ uint32_t npid = (cdw10 >> 1) + 1;

+ unsigned int i = 0;

+ g_autofree uint16_t *pids = NULL;

+ uint32_t maxnpid = n->subsys->endgrp.fdp.nrg * n->subsys->endgrp.fdp.nruh;

+

+ if (unlikely(npid >= MIN(NVME_FDP_MAXPIDS, maxnpid))) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ pids = g_new(uint16_t, npid);

+

+ ret = nvme_h2c(n, pids, npid * sizeof(uint16_t), req);

+ if (ret) {

+ return ret;

+ }

+

+ for (; i < npid; i++) {

+ if (!nvme_update_ruh(n, ns, pids[i])) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+ }

+

+ return ret;

+}

+

+static uint16_t nvme_io_mgmt_send(NvmeCtrl *n, NvmeRequest *req)

+{

+ NvmeCmd *cmd = &req->cmd;

+ uint32_t cdw10 = le32_to_cpu(cmd->cdw10);

+ uint8_t mo = (cdw10 & 0xff);

+

+ switch (mo) {

+ case NVME_IOMS_MO_NOP:

+ return 0;

+ case NVME_IOMS_MO_RUH_UPDATE:

+ return nvme_io_mgmt_send_ruh_update(n, req);

+ default:

+ return NVME_INVALID_FIELD | NVME_DNR;

+ };

+}

+

+ case NVME_CMD_IO_MGMT_RECV:

+ return nvme_io_mgmt_recv(n, req);

+ case NVME_CMD_IO_MGMT_SEND:

+ return nvme_io_mgmt_send(n, req);

+ stats->units_read += s->nr_bytes[BLOCK_ACCT_READ];

+ stats->units_written += s->nr_bytes[BLOCK_ACCT_WRITE];

+ uint64_t u_read, u_written;

+ u_read = DIV_ROUND_UP(stats.units_read >> BDRV_SECTOR_BITS, 1000);

+ u_written = DIV_ROUND_UP(stats.units_written >> BDRV_SECTOR_BITS, 1000);

+

+ smart.data_units_read[0] = cpu_to_le64(u_read);

+ smart.data_units_written[0] = cpu_to_le64(u_written);

+static uint16_t nvme_endgrp_info(NvmeCtrl *n, uint8_t rae, uint32_t buf_len,

+ uint64_t off, NvmeRequest *req)

+{

+ uint32_t dw11 = le32_to_cpu(req->cmd.cdw11);

+ uint16_t endgrpid = (dw11 >> 16) & 0xffff;

+ struct nvme_stats stats = {};

+ NvmeEndGrpLog info = {};

+ int i;

+

+ if (!n->subsys || endgrpid != 0x1) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ if (off >= sizeof(info)) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ for (i = 1; i <= NVME_MAX_NAMESPACES; i++) {

+ NvmeNamespace *ns = nvme_subsys_ns(n->subsys, i);

+ if (!ns) {

+ continue;

+ }

+

+ nvme_set_blk_stats(ns, &stats);

+ }

+

+ info.data_units_read[0] =

+ cpu_to_le64(DIV_ROUND_UP(stats.units_read / 1000000000, 1000000000));

+ info.data_units_written[0] =

+ cpu_to_le64(DIV_ROUND_UP(stats.units_written / 1000000000, 1000000000));

+ info.media_units_written[0] =

+ cpu_to_le64(DIV_ROUND_UP(stats.units_written / 1000000000, 1000000000));

+

+ info.host_read_commands[0] = cpu_to_le64(stats.read_commands);

+ info.host_write_commands[0] = cpu_to_le64(stats.write_commands);

+

+ buf_len = MIN(sizeof(info) - off, buf_len);

+

+ return nvme_c2h(n, (uint8_t *)&info + off, buf_len, req);

+}

+

+

+static size_t sizeof_fdp_conf_descr(size_t nruh, size_t vss)

+{

+ size_t entry_siz = sizeof(NvmeFdpDescrHdr) + nruh * sizeof(NvmeRuhDescr)

+ + vss;

+ return ROUND_UP(entry_siz, 8);

+}

+

+static uint16_t nvme_fdp_confs(NvmeCtrl *n, uint32_t endgrpid, uint32_t buf_len,

+ uint64_t off, NvmeRequest *req)

+{

+ uint32_t log_size, trans_len;

+ g_autofree uint8_t *buf = NULL;

+ NvmeFdpDescrHdr *hdr;

+ NvmeRuhDescr *ruhd;

+ NvmeEnduranceGroup *endgrp;

+ NvmeFdpConfsHdr *log;

+ size_t nruh, fdp_descr_size;

+ int i;

+

+ if (endgrpid != 1 || !n->subsys) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ endgrp = &n->subsys->endgrp;

+

+ if (endgrp->fdp.enabled) {

+ nruh = endgrp->fdp.nruh;

+ } else {

+ nruh = 1;

+ }

+

+ fdp_descr_size = sizeof_fdp_conf_descr(nruh, FDPVSS);

+ log_size = sizeof(NvmeFdpConfsHdr) + fdp_descr_size;

+

+ if (off >= log_size) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ trans_len = MIN(log_size - off, buf_len);

+

+ buf = g_malloc0(log_size);

+ log = (NvmeFdpConfsHdr *)buf;

+ hdr = (NvmeFdpDescrHdr *)(log + 1);

+ ruhd = (NvmeRuhDescr *)(buf + sizeof(*log) + sizeof(*hdr));

+

+ log->num_confs = cpu_to_le16(0);

+ log->size = cpu_to_le32(log_size);

+

+ hdr->descr_size = cpu_to_le16(fdp_descr_size);

+ if (endgrp->fdp.enabled) {

+ hdr->fdpa = FIELD_DP8(hdr->fdpa, FDPA, VALID, 1);

+ hdr->fdpa = FIELD_DP8(hdr->fdpa, FDPA, RGIF, endgrp->fdp.rgif);

+ hdr->nrg = cpu_to_le16(endgrp->fdp.nrg);

+ hdr->nruh = cpu_to_le16(endgrp->fdp.nruh);

+ hdr->maxpids = cpu_to_le16(NVME_FDP_MAXPIDS - 1);

+ hdr->nnss = cpu_to_le32(NVME_MAX_NAMESPACES);

+ hdr->runs = cpu_to_le64(endgrp->fdp.runs);

+

+ for (i = 0; i < nruh; i++) {

+ ruhd->ruht = NVME_RUHT_INITIALLY_ISOLATED;

+ ruhd++;

+ }

+ } else {

+ /* 1 bit for RUH in PIF -> 2 RUHs max. */

+ hdr->nrg = cpu_to_le16(1);

+ hdr->nruh = cpu_to_le16(1);

+ hdr->maxpids = cpu_to_le16(NVME_FDP_MAXPIDS - 1);

+ hdr->nnss = cpu_to_le32(1);

+ hdr->runs = cpu_to_le64(96 * MiB);

+

+ ruhd->ruht = NVME_RUHT_INITIALLY_ISOLATED;

+ }

+

+ return nvme_c2h(n, (uint8_t *)buf + off, trans_len, req);

+}

+

+static uint16_t nvme_fdp_ruh_usage(NvmeCtrl *n, uint32_t endgrpid,

+ uint32_t dw10, uint32_t dw12,

+ uint32_t buf_len, uint64_t off,

+ NvmeRequest *req)

+{

+ NvmeRuHandle *ruh;

+ NvmeRuhuLog *hdr;

+ NvmeRuhuDescr *ruhud;

+ NvmeEnduranceGroup *endgrp;

+ g_autofree uint8_t *buf = NULL;

+ uint32_t log_size, trans_len;

+ uint16_t i;

+

+ if (endgrpid != 1 || !n->subsys) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ endgrp = &n->subsys->endgrp;

+

+ if (!endgrp->fdp.enabled) {

+ return NVME_FDP_DISABLED | NVME_DNR;

+ }

+

+ log_size = sizeof(NvmeRuhuLog) + endgrp->fdp.nruh * sizeof(NvmeRuhuDescr);

+

+ if (off >= log_size) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ trans_len = MIN(log_size - off, buf_len);

+

+ buf = g_malloc0(log_size);

+ hdr = (NvmeRuhuLog *)buf;

+ ruhud = (NvmeRuhuDescr *)(hdr + 1);

+

+ ruh = endgrp->fdp.ruhs;

+ hdr->nruh = cpu_to_le16(endgrp->fdp.nruh);

+

+ for (i = 0; i < endgrp->fdp.nruh; i++, ruhud++, ruh++) {

+ ruhud->ruha = ruh->ruha;

+ }

+

+ return nvme_c2h(n, (uint8_t *)buf + off, trans_len, req);

+}

+

+static uint16_t nvme_fdp_stats(NvmeCtrl *n, uint32_t endgrpid, uint32_t buf_len,

+ uint64_t off, NvmeRequest *req)

+{

+ NvmeEnduranceGroup *endgrp;

+ NvmeFdpStatsLog log = {};

+ uint32_t trans_len;

+

+ if (off >= sizeof(NvmeFdpStatsLog)) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ if (endgrpid != 1 || !n->subsys) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ if (!n->subsys->endgrp.fdp.enabled) {

+ return NVME_FDP_DISABLED | NVME_DNR;

+ }

+

+ endgrp = &n->subsys->endgrp;

+

+ trans_len = MIN(sizeof(log) - off, buf_len);

+

+ /* spec value is 128 bit, we only use 64 bit */

+ log.hbmw[0] = cpu_to_le64(endgrp->fdp.hbmw);

+ log.mbmw[0] = cpu_to_le64(endgrp->fdp.mbmw);

+ log.mbe[0] = cpu_to_le64(endgrp->fdp.mbe);

+

+ return nvme_c2h(n, (uint8_t *)&log + off, trans_len, req);

+}

+

+static uint16_t nvme_fdp_events(NvmeCtrl *n, uint32_t endgrpid,

+ uint32_t buf_len, uint64_t off,

+ NvmeRequest *req)

+{

+ NvmeEnduranceGroup *endgrp;

+ NvmeCmd *cmd = &req->cmd;

+ bool host_events = (cmd->cdw10 >> 8) & 0x1;

+ uint32_t log_size, trans_len;

+ NvmeFdpEventBuffer *ebuf;

+ g_autofree NvmeFdpEventsLog *elog = NULL;

+ NvmeFdpEvent *event;

+

+ if (endgrpid != 1 || !n->subsys) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ endgrp = &n->subsys->endgrp;

+

+ if (!endgrp->fdp.enabled) {

+ return NVME_FDP_DISABLED | NVME_DNR;

+ }

+

+ if (host_events) {

+ ebuf = &endgrp->fdp.host_events;

+ } else {

+ ebuf = &endgrp->fdp.ctrl_events;

+ }

+

+ log_size = sizeof(NvmeFdpEventsLog) + ebuf->nelems * sizeof(NvmeFdpEvent);

+ trans_len = MIN(log_size - off, buf_len);

+ elog = g_malloc0(log_size);

+ elog->num_events = cpu_to_le32(ebuf->nelems);

+ event = (NvmeFdpEvent *)(elog + 1);

+

+ if (ebuf->nelems && ebuf->start == ebuf->next) {

+ unsigned int nelems = (NVME_FDP_MAX_EVENTS - ebuf->start);

+ /* wrap over, copy [start;NVME_FDP_MAX_EVENTS[ and [0; next[ */

+ memcpy(event, &ebuf->events[ebuf->start],

+ sizeof(NvmeFdpEvent) * nelems);

+ memcpy(event + nelems, ebuf->events,

+ sizeof(NvmeFdpEvent) * ebuf->next);

+ } else if (ebuf->start < ebuf->next) {

+ memcpy(event, &ebuf->events[ebuf->start],

+ sizeof(NvmeFdpEvent) * (ebuf->next - ebuf->start));

+ }

+

+ return nvme_c2h(n, (uint8_t *)elog + off, trans_len, req);

+}

+

+ uint32_t numdl, numdu, lspi;

+ lspi = (dw11 >> 16);

+ case NVME_LOG_ENDGRP:

+ return nvme_endgrp_info(n, rae, len, off, req);

+ case NVME_LOG_FDP_CONFS:

+ return nvme_fdp_confs(n, lspi, len, off, req);

+ case NVME_LOG_FDP_RUH_USAGE:

+ return nvme_fdp_ruh_usage(n, lspi, dw10, dw12, len, off, req);

+ case NVME_LOG_FDP_STATS:

+ return nvme_fdp_stats(n, lspi, len, off, req);

+ case NVME_LOG_FDP_EVENTS:

+ return nvme_fdp_events(n, lspi, len, off, req);

+static int nvme_get_feature_fdp(NvmeCtrl *n, uint32_t endgrpid,

+ uint32_t *result)

+{

+ *result = 0;

+

+ if (!n->subsys || !n->subsys->endgrp.fdp.enabled) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ *result = FIELD_DP16(0, FEAT_FDP, FDPE, 1);

+ *result = FIELD_DP16(*result, FEAT_FDP, CONF_NDX, 0);

+

+ return NVME_SUCCESS;

+}

+

+static uint16_t nvme_get_feature_fdp_events(NvmeCtrl *n, NvmeNamespace *ns,

+ NvmeRequest *req, uint32_t *result)

+{

+ NvmeCmd *cmd = &req->cmd;

+ uint32_t cdw11 = le32_to_cpu(cmd->cdw11);

+ uint16_t ph = cdw11 & 0xffff;

+ uint8_t noet = (cdw11 >> 16) & 0xff;

+ uint16_t ruhid, ret;

+ uint32_t nentries = 0;

+ uint8_t s_events_ndx = 0;

+ size_t s_events_siz = sizeof(NvmeFdpEventDescr) * noet;

+ g_autofree NvmeFdpEventDescr *s_events = g_malloc0(s_events_siz);

+ NvmeRuHandle *ruh;

+ NvmeFdpEventDescr *s_event;

+

+ if (!n->subsys || !n->subsys->endgrp.fdp.enabled) {

+ return NVME_FDP_DISABLED | NVME_DNR;

+ }

+

+ if (!nvme_ph_valid(ns, ph)) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ ruhid = ns->fdp.phs[ph];

+ ruh = &n->subsys->endgrp.fdp.ruhs[ruhid];

+

+ assert(ruh);

+

+ if (unlikely(noet == 0)) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ for (uint8_t event_type = 0; event_type < FDP_EVT_MAX; event_type++) {

+ uint8_t shift = nvme_fdp_evf_shifts[event_type];

+ if (!shift && event_type) {

+ /*

+ * only first entry (event_type == 0) has a shift value of 0

+ * other entries are simply unpopulated.

+ */

+ continue;

+ }

+

+ nentries++;

+

+ s_event = &s_events[s_events_ndx];

+ s_event->evt = event_type;

+ s_event->evta = (ruh->event_filter >> shift) & 0x1;

+

+ /* break if all `noet` entries are filled */

+ if ((++s_events_ndx) == noet) {

+ break;

+ }

+ }

+

+ ret = nvme_c2h(n, s_events, s_events_siz, req);

+ if (ret) {

+ return ret;

+ }

+

+ *result = nentries;

+ return NVME_SUCCESS;

+}

+

+ uint16_t endgrpid = 0, ret = NVME_SUCCESS;

+ case NVME_FDP_MODE:

+ endgrpid = dw11 & 0xff;

+

+ if (endgrpid != 0x1) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ ret = nvme_get_feature_fdp(n, endgrpid, &result);

+ if (ret) {

+ return ret;

+ }

+ goto out;

+ case NVME_FDP_EVENTS:

+ if (!nvme_nsid_valid(n, nsid)) {

+ return NVME_INVALID_NSID | NVME_DNR;

+ }

+

+ ns = nvme_ns(n, nsid);

+ if (unlikely(!ns)) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ ret = nvme_get_feature_fdp_events(n, ns, req, &result);

+ if (ret) {

+ return ret;

+ }

+ goto out;

+ case NVME_FDP_MODE:

+ endgrpid = dw11 & 0xff;

+

+ if (endgrpid != 0x1) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ ret = nvme_get_feature_fdp(n, endgrpid, &result);

+ if (ret) {

+ return ret;

+ }

+ goto out;

+

+ break;

+ return ret;

+static uint16_t nvme_set_feature_fdp_events(NvmeCtrl *n, NvmeNamespace *ns,

+ NvmeRequest *req)

+{

+ NvmeCmd *cmd = &req->cmd;

+ uint32_t cdw11 = le32_to_cpu(cmd->cdw11);

+ uint16_t ph = cdw11 & 0xffff;

+ uint8_t noet = (cdw11 >> 16) & 0xff;

+ uint16_t ret, ruhid;

+ uint8_t enable = le32_to_cpu(cmd->cdw12) & 0x1;

+ uint8_t event_mask = 0;

+ unsigned int i;

+ g_autofree uint8_t *events = g_malloc0(noet);

+ NvmeRuHandle *ruh = NULL;

+

+ assert(ns);

+

+ if (!n->subsys || !n->subsys->endgrp.fdp.enabled) {

+ return NVME_FDP_DISABLED | NVME_DNR;

+ }

+

+ if (!nvme_ph_valid(ns, ph)) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ ruhid = ns->fdp.phs[ph];

+ ruh = &n->subsys->endgrp.fdp.ruhs[ruhid];

+

+ ret = nvme_h2c(n, events, noet, req);

+ if (ret) {

+ return ret;

+ }

+

+ for (i = 0; i < noet; i++) {

+ event_mask |= (1 << nvme_fdp_evf_shifts[events[i]]);

+ }

+

+ if (enable) {

+ ruh->event_filter |= event_mask;

+ } else {

+ ruh->event_filter = ruh->event_filter & ~event_mask;

+ }

+

+ return NVME_SUCCESS;

+}

+

+ case NVME_FDP_MODE:

+ /* spec: abort with cmd seq err if there's one or more NS' in endgrp */

+ return NVME_CMD_SEQ_ERROR | NVME_DNR;

+ case NVME_FDP_EVENTS:

+ return nvme_set_feature_fdp_events(n, ns, req);

+static uint16_t nvme_directive_send(NvmeCtrl *n, NvmeRequest *req)

+{

+ return NVME_INVALID_FIELD | NVME_DNR;

+}

+

+static uint16_t nvme_directive_receive(NvmeCtrl *n, NvmeRequest *req)

+{

+ NvmeNamespace *ns;

+ uint32_t dw10 = le32_to_cpu(req->cmd.cdw10);

+ uint32_t dw11 = le32_to_cpu(req->cmd.cdw11);

+ uint32_t nsid = le32_to_cpu(req->cmd.nsid);

+ uint8_t doper, dtype;

+ uint32_t numd, trans_len;

+ NvmeDirectiveIdentify id = {

+ .supported = 1 << NVME_DIRECTIVE_IDENTIFY,

+ .enabled = 1 << NVME_DIRECTIVE_IDENTIFY,

+ };

+

+ numd = dw10 + 1;

+ doper = dw11 & 0xff;

+ dtype = (dw11 >> 8) & 0xff;

+

+ trans_len = MIN(sizeof(NvmeDirectiveIdentify), numd << 2);

+

+ if (nsid == NVME_NSID_BROADCAST || dtype != NVME_DIRECTIVE_IDENTIFY ||

+ doper != NVME_DIRECTIVE_RETURN_PARAMS) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ ns = nvme_ns(n, nsid);

+ if (!ns) {

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ switch (dtype) {

+ case NVME_DIRECTIVE_IDENTIFY:

+ switch (doper) {

+ case NVME_DIRECTIVE_RETURN_PARAMS:

+ if (ns->endgrp->fdp.enabled) {

+ id.supported |= 1 << NVME_DIRECTIVE_DATA_PLACEMENT;

+ id.enabled |= 1 << NVME_DIRECTIVE_DATA_PLACEMENT;

+ id.persistent |= 1 << NVME_DIRECTIVE_DATA_PLACEMENT;

+ }

+

+ return nvme_c2h(n, (uint8_t *)&id, trans_len, req);

+

+ default:

+ return NVME_INVALID_FIELD | NVME_DNR;

+ }

+

+ default:

+ return NVME_INVALID_FIELD;

+ }

+}

+

+ case NVME_ADM_CMD_DIRECTIVE_SEND:

+ return nvme_directive_send(n, req);

+ case NVME_ADM_CMD_DIRECTIVE_RECV:

+ return nvme_directive_receive(n, req);

+ uint32_t ctratt;

+ ctratt = NVME_CTRATT_ELBAS;

+ cpu_to_le16(NVME_OACS_NS_MGMT | NVME_OACS_FORMAT | NVME_OACS_DBBUF |

+ NVME_OACS_DIRECTIVES);

+ ctratt |= NVME_CTRATT_ENDGRPS;

+

+ id->endgidmax = cpu_to_le16(0x1);

+

+ if (n->subsys->endgrp.fdp.enabled) {

+ ctratt |= NVME_CTRATT_FDPS;

+ }

+ id->ctratt = cpu_to_le32(ctratt);

+

+#include "qemu/cutils.h"

+#include "qemu/bitops.h"

+static NvmeRuHandle *nvme_find_ruh_by_attr(NvmeEnduranceGroup *endgrp,

+ uint8_t ruha, uint16_t *ruhid)

+{

+ for (uint16_t i = 0; i < endgrp->fdp.nruh; i++) {

+ NvmeRuHandle *ruh = &endgrp->fdp.ruhs[i];

+

+ if (ruh->ruha == ruha) {

+ *ruhid = i;

+ return ruh;

+ }

+ }

+

+ return NULL;

+}

+

+static bool nvme_ns_init_fdp(NvmeNamespace *ns, Error **errp)

+{

+ NvmeEnduranceGroup *endgrp = ns->endgrp;

+ NvmeRuHandle *ruh;

+ uint8_t lbafi = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);

+ unsigned int *ruhid, *ruhids;

+ char *r, *p, *token;

+ uint16_t *ph;

+

+ if (!ns->params.fdp.ruhs) {

+ ns->fdp.nphs = 1;

+ ph = ns->fdp.phs = g_new(uint16_t, 1);

+

+ ruh = nvme_find_ruh_by_attr(endgrp, NVME_RUHA_CTRL, ph);

+ if (!ruh) {

+ ruh = nvme_find_ruh_by_attr(endgrp, NVME_RUHA_UNUSED, ph);

+ if (!ruh) {

+ error_setg(errp, "no unused reclaim unit handles left");

+ return false;

+ }

+

+ ruh->ruha = NVME_RUHA_CTRL;

+ ruh->lbafi = lbafi;

+ ruh->ruamw = endgrp->fdp.runs >> ns->lbaf.ds;

+

+ for (uint16_t rg = 0; rg < endgrp->fdp.nrg; rg++) {

+ ruh->rus[rg].ruamw = ruh->ruamw;

+ }

+ } else if (ruh->lbafi != lbafi) {

+ error_setg(errp, "lba format index of controller assigned "

+ "reclaim unit handle does not match namespace lba "

+ "format index");

+ return false;

+ }

+

+ return true;

+ }

+

+ ruhid = ruhids = g_new0(unsigned int, endgrp->fdp.nruh);

+ r = p = strdup(ns->params.fdp.ruhs);

+

+ /* parse the placement handle identifiers */

+ while ((token = qemu_strsep(&p, ";")) != NULL) {

+ ns->fdp.nphs += 1;

+ if (ns->fdp.nphs > NVME_FDP_MAXPIDS ||

+ ns->fdp.nphs == endgrp->fdp.nruh) {

+ error_setg(errp, "too many placement handles");

+ free(r);

+ return false;

+ }

+

+ if (qemu_strtoui(token, NULL, 0, ruhid++) < 0) {

+ error_setg(errp, "cannot parse reclaim unit handle identifier");

+ free(r);

+ return false;

+ }

+ }

+

+ free(r);

+

+ ph = ns->fdp.phs = g_new(uint16_t, ns->fdp.nphs);

+

+ ruhid = ruhids;

+

+ /* verify the identifiers */

+ for (unsigned int i = 0; i < ns->fdp.nphs; i++, ruhid++, ph++) {

+ if (*ruhid >= endgrp->fdp.nruh) {

+ error_setg(errp, "invalid reclaim unit handle identifier");

+ return false;

+ }

+

+ ruh = &endgrp->fdp.ruhs[*ruhid];

+

+ switch (ruh->ruha) {

+ case NVME_RUHA_UNUSED:

+ ruh->ruha = NVME_RUHA_HOST;

+ ruh->lbafi = lbafi;

+ ruh->ruamw = endgrp->fdp.runs >> ns->lbaf.ds;

+

+ for (uint16_t rg = 0; rg < endgrp->fdp.nrg; rg++) {

+ ruh->rus[rg].ruamw = ruh->ruamw;

+ }

+

+ break;

+

+ case NVME_RUHA_HOST:

+ if (ruh->lbafi != lbafi) {

+ error_setg(errp, "lba format index of host assigned"

+ "reclaim unit handle does not match namespace "

+ "lba format index");

+ return false;

+ }

+

+ break;

+

+ case NVME_RUHA_CTRL:

+ error_setg(errp, "reclaim unit handle is controller assigned");

+ return false;

+

+ default:

+ abort();

+ }

+

+ *ph = *ruhid;

+ }

+

+ return true;

+}

+

+ if (ns->params.zoned && ns->endgrp && ns->endgrp->fdp.enabled) {

+ error_setg(errp, "cannot be a zoned- in an FDP configuration");

+ return -1;

+ }

+

+ if (ns->endgrp && ns->endgrp->fdp.enabled) {

+ if (!nvme_ns_init_fdp(ns, errp)) {

+ return -1;

+ }

+ }

+

+

+ if (ns->endgrp && ns->endgrp->fdp.enabled) {

+ g_free(ns->fdp.phs);

+ }

+ ns->subsys = subsys;

+ ns->endgrp = &subsys->endgrp;

+ ns->id_ns.endgid = cpu_to_le16(0x1);

+

+

+ DEFINE_PROP_STRING("fdp.ruhs", NvmeNamespace, params.fdp.ruhs),

+#define NVME_FDP_MAX_EVENTS 63

+#define NVME_FDP_MAXPIDS 128

+typedef struct NvmeReclaimUnit {

+ uint64_t ruamw;

+} NvmeReclaimUnit;

+

+typedef struct NvmeRuHandle {

+ uint8_t ruht;

+ uint8_t ruha;

+ uint64_t event_filter;

+ uint8_t lbafi;

+ uint64_t ruamw;

+

+ /* reclaim units indexed by reclaim group */

+ NvmeReclaimUnit *rus;

+} NvmeRuHandle;

+

+typedef struct NvmeFdpEventBuffer {

+ NvmeFdpEvent events[NVME_FDP_MAX_EVENTS];

+ unsigned int nelems;

+ unsigned int start;

+ unsigned int next;

+} NvmeFdpEventBuffer;

+

+typedef struct NvmeEnduranceGroup {

+ uint8_t event_conf;

+

+ struct {

+ NvmeFdpEventBuffer host_events, ctrl_events;

+

+ uint16_t nruh;

+ uint16_t nrg;

+ uint8_t rgif;

+ uint64_t runs;

+

+ uint64_t hbmw;

+ uint64_t mbmw;

+ uint64_t mbe;

+

+ bool enabled;

+

+ NvmeRuHandle *ruhs;

+ } fdp;

+} NvmeEnduranceGroup;

+

+ NvmeCtrl *ctrls[NVME_MAX_CONTROLLERS];

+ NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1];

+ NvmeEnduranceGroup endgrp;

+

+ struct {

+ bool enabled;

+ uint64_t runs;

+ uint16_t nruh;

+ uint32_t nrg;

+ } fdp;

+#define FDP_EVT_MAX 0xff

+#define NVME_FDP_MAX_NS_RUHS 32u

+#define FDPVSS 0

+

+static const uint8_t nvme_fdp_evf_shifts[FDP_EVT_MAX] = {

+ /* Host events */

+ [FDP_EVT_RU_NOT_FULLY_WRITTEN] = 0,

+ [FDP_EVT_RU_ATL_EXCEEDED] = 1,

+ [FDP_EVT_CTRL_RESET_RUH] = 2,

+ [FDP_EVT_INVALID_PID] = 3,

+ /* CTRL events */

+ [FDP_EVT_MEDIA_REALLOC] = 32,

+ [FDP_EVT_RUH_IMPLICIT_RU_CHANGE] = 33,

+};

+

+

+ struct {

+ char *ruhs;

+ } fdp;

+ NvmeSubsystem *subsys;

+ NvmeEnduranceGroup *endgrp;

+

+ struct {

+ uint16_t nphs;

+ /* reclaim unit handle identifiers indexed by placement handle */

+ uint16_t *phs;

+ } fdp;

+static inline void nvme_fdp_stat_inc(uint64_t *a, uint64_t b)

+{

+ uint64_t ret = *a + b;

+ *a = ret < *a ? UINT64_MAX : ret;

+}

+

+ case NVME_ADM_CMD_DIRECTIVE_SEND: return "NVME_ADM_CMD_DIRECTIVE_SEND";

+ case NVME_ADM_CMD_DIRECTIVE_RECV: return "NVME_ADM_CMD_DIRECTIVE_RECV";

+#include "qemu/units.h"

+#define NVME_DEFAULT_RU_SIZE (96 * MiB)

+

+static bool nvme_calc_rgif(uint16_t nruh, uint16_t nrg, uint8_t *rgif)

+{

+ uint16_t val;

+ unsigned int i;

+

+ if (unlikely(nrg == 1)) {

+ /* PIDRG_NORGI scenario, all of pid is used for PHID */

+ *rgif = 0;

+ return true;

+ }

+

+ val = nrg;

+ i = 0;

+ while (val) {

+ val >>= 1;

+ i++;

+ }

+ *rgif = i;

+

+ /* ensure remaining bits suffice to represent number of phids in a RG */

+ if (unlikely((UINT16_MAX >> i) < nruh)) {

+ *rgif = 0;

+ return false;

+ }

+

+ return true;

+}

+

+static bool nvme_subsys_setup_fdp(NvmeSubsystem *subsys, Error **errp)

+{

+ NvmeEnduranceGroup *endgrp = &subsys->endgrp;

+

+ if (!subsys->params.fdp.runs) {

+ error_setg(errp, "fdp.runs must be non-zero");

+ return false;

+ }

+

+ endgrp->fdp.runs = subsys->params.fdp.runs;

+

+ if (!subsys->params.fdp.nrg) {

+ error_setg(errp, "fdp.nrg must be non-zero");

+ return false;

+ }

+

+ endgrp->fdp.nrg = subsys->params.fdp.nrg;

+

+ if (!subsys->params.fdp.nruh) {

+ error_setg(errp, "fdp.nruh must be non-zero");

+ return false;

+ }

+

+ endgrp->fdp.nruh = subsys->params.fdp.nruh;

+

+ if (!nvme_calc_rgif(endgrp->fdp.nruh, endgrp->fdp.nrg, &endgrp->fdp.rgif)) {

+ error_setg(errp,

+ "cannot derive a valid rgif (nruh %"PRIu16" nrg %"PRIu32")",

+ endgrp->fdp.nruh, endgrp->fdp.nrg);

+ return false;

+ }

+

+ endgrp->fdp.ruhs = g_new(NvmeRuHandle, endgrp->fdp.nruh);

+

+ for (uint16_t ruhid = 0; ruhid < endgrp->fdp.nruh; ruhid++) {

+ endgrp->fdp.ruhs[ruhid] = (NvmeRuHandle) {

+ .ruht = NVME_RUHT_INITIALLY_ISOLATED,

+ .ruha = NVME_RUHA_UNUSED,

+ };

+

+ endgrp->fdp.ruhs[ruhid].rus = g_new(NvmeReclaimUnit, endgrp->fdp.nrg);

+ }

+

+ endgrp->fdp.enabled = true;

+

+ return true;

+}

+

+static bool nvme_subsys_setup(NvmeSubsystem *subsys, Error **errp)

+

+ if (subsys->params.fdp.enabled && !nvme_subsys_setup_fdp(subsys, errp)) {

+ return false;

+ }

+

+ return true;

+ nvme_subsys_setup(subsys, errp);

+ DEFINE_PROP_BOOL("fdp", NvmeSubsystem, params.fdp.enabled, false),

+ DEFINE_PROP_SIZE("fdp.runs", NvmeSubsystem, params.fdp.runs,

+ NVME_DEFAULT_RU_SIZE),

+ DEFINE_PROP_UINT32("fdp.nrg", NvmeSubsystem, params.fdp.nrg, 1),

+ DEFINE_PROP_UINT16("fdp.nruh", NvmeSubsystem, params.fdp.nruh, 0),

+pci_nvme_fdp_ruh_change(uint16_t rgid, uint16_t ruhid) "change RU on RUH rgid=%"PRIu16", ruhid=%"PRIu16""

+ qemu_irq mv_pirq[PCI_NUM_PINS];

+ qemu_irq via_pirq[PCI_NUM_PINS];

+static void pegasos2_pci_irq(void *opaque, int n, int level)

+{

+ Pegasos2MachineState *pm = opaque;

+

+ /* PCI interrupt lines are connected to both MV64361 and VT8231 */

+ qemu_set_irq(pm->mv_pirq[n], level);

+ qemu_set_irq(pm->via_pirq[n], level);

+}

+

+ int i, sz;

+ for (i = 0; i < PCI_NUM_PINS; i++) {

+ pm->mv_pirq[i] = qdev_get_gpio_in_named(pm->mv, "gpp", 12 + i);

+ }

+ pci_bus_irqs(pci_bus, pegasos2_pci_irq, pm, PCI_NUM_PINS);

+ for (i = 0; i < PCI_NUM_PINS; i++) {

+ pm->via_pirq[i] = qdev_get_gpio_in_named(DEVICE(via), "pirq", i);

+ }

+ pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |

+ 0x55, 1, 0x90);

+ pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |

+ 0x56, 1, 0x99);

+ pegasos2_pci_config_write(pm, 1, (PCI_DEVFN(12, 0) << 8) |

+ 0x57, 1, 0x90);

+ select ACPI

+riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c'))

+/*

+ * Support for generating ACPI tables and passing them to Guests

+ *

+ * RISC-V virt ACPI generation

+ *

+ * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>

+ * Copyright (C) 2006 Fabrice Bellard

+ * Copyright (C) 2013 Red Hat Inc

+ * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.

+ * Copyright (C) 2021-2023 Ventana Micro Systems Inc

+ *

+ * This program is free software; you can redistribute it and/or modify

+ * it under the terms of the GNU General Public License as published by

+ * the Free Software Foundation; either version 2 of the License, or

+ * (at your option) any later version.

+

+ * This program is distributed in the hope that it will be useful,

+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

+ * GNU General Public License for more details.

+

+ * You should have received a copy of the GNU General Public License along

+ * with this program; if not, see <http://www.gnu.org/licenses/>.

+ */

+

+#include "qemu/osdep.h"

+#include "hw/acpi/acpi-defs.h"

+#include "hw/acpi/acpi.h"

+#include "hw/acpi/aml-build.h"

+#include "hw/acpi/utils.h"

+#include "qapi/error.h"

+#include "sysemu/reset.h"

+#include "migration/vmstate.h"

+#include "hw/riscv/virt.h"

+#include "hw/riscv/numa.h"

+#include "hw/intc/riscv_aclint.h"

+

+#define ACPI_BUILD_TABLE_SIZE 0x20000

+

+typedef struct AcpiBuildState {

+ /* Copy of table in RAM (for patching) */

+ MemoryRegion *table_mr;

+ MemoryRegion *rsdp_mr;

+ MemoryRegion *linker_mr;

+ /* Is table patched? */

+ bool patched;

+} AcpiBuildState;

+

+static void acpi_align_size(GArray *blob, unsigned align)

+{

+ /*

+ * Align size to multiple of given size. This reduces the chance

+ * we need to change size in the future (breaking cross version migration).

+ */

+ g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));

+}

+

+static void riscv_acpi_madt_add_rintc(uint32_t uid,

+ const CPUArchIdList *arch_ids,

+ GArray *entry)

+{

+ uint64_t hart_id = arch_ids->cpus[uid].arch_id;

+

+ build_append_int_noprefix(entry, 0x18, 1); /* Type */

+ build_append_int_noprefix(entry, 20, 1); /* Length */

+ build_append_int_noprefix(entry, 1, 1); /* Version */

+ build_append_int_noprefix(entry, 0, 1); /* Reserved */

+ build_append_int_noprefix(entry, 0x1, 4); /* Flags */

+ build_append_int_noprefix(entry, hart_id, 8); /* Hart ID */

+ build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */

+}

+

+static void acpi_dsdt_add_cpus(Aml *scope, RISCVVirtState *s)

+{

+ MachineClass *mc = MACHINE_GET_CLASS(s);

+ MachineState *ms = MACHINE(s);

+ const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);

+

+ for (int i = 0; i < arch_ids->len; i++) {

+ Aml *dev;

+ GArray *madt_buf = g_array_new(0, 1, 1);

+

+ dev = aml_device("C%.03X", i);

+ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));

+ aml_append(dev, aml_name_decl("_UID",

+ aml_int(arch_ids->cpus[i].arch_id)));

+

+ /* build _MAT object */

+ riscv_acpi_madt_add_rintc(i, arch_ids, madt_buf);

+ aml_append(dev, aml_name_decl("_MAT",

+ aml_buffer(madt_buf->len,

+ (uint8_t *)madt_buf->data)));

+ g_array_free(madt_buf, true);

+

+ aml_append(scope, dev);

+ }

+}

+

+static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)

+{

+ Aml *dev = aml_device("FWCF");

+ aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));

+

+ /* device present, functioning, decoding, not shown in UI */

+ aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));

+ aml_append(dev, aml_name_decl("_CCA", aml_int(1)));

+

+ Aml *crs = aml_resource_template();

+ aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,

+ fw_cfg_memmap->size, AML_READ_WRITE));

+ aml_append(dev, aml_name_decl("_CRS", crs));

+ aml_append(scope, dev);

+}

+

+/* RHCT Node[N] starts at offset 56 */

+#define RHCT_NODE_ARRAY_OFFSET 56

+

+/*

+ * ACPI spec, Revision 6.5+

+ * 5.2.36 RISC-V Hart Capabilities Table (RHCT)

+ * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/16

+ * https://drive.google.com/file/d/1nP3nFiH4jkPMp6COOxP6123DCZKR-tia/view

+ */

+static void build_rhct(GArray *table_data,

+ BIOSLinker *linker,

+ RISCVVirtState *s)

+{

+ MachineClass *mc = MACHINE_GET_CLASS(s);

+ MachineState *ms = MACHINE(s);

+ const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);

+ size_t len, aligned_len;

+ uint32_t isa_offset, num_rhct_nodes;

+ RISCVCPU *cpu;

+ char *isa;

+

+ AcpiTable table = { .sig = "RHCT", .rev = 1, .oem_id = s->oem_id,

+ .oem_table_id = s->oem_table_id };

+

+ acpi_table_begin(&table, table_data);

+

+ build_append_int_noprefix(table_data, 0x0, 4); /* Reserved */

+

+ /* Time Base Frequency */

+ build_append_int_noprefix(table_data,

+ RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, 8);

+

+ /* ISA + N hart info */

+ num_rhct_nodes = 1 + ms->smp.cpus;

+

+ /* Number of RHCT nodes*/

+ build_append_int_noprefix(table_data, num_rhct_nodes, 4);

+

+ /* Offset to the RHCT node array */

+ build_append_int_noprefix(table_data, RHCT_NODE_ARRAY_OFFSET, 4);

+

+ /* ISA String Node */

+ isa_offset = table_data->len - table.table_offset;

+ build_append_int_noprefix(table_data, 0, 2); /* Type 0 */

+

+ cpu = &s->soc[0].harts[0];

+ isa = riscv_isa_string(cpu);

+ len = 8 + strlen(isa) + 1;

+ aligned_len = (len % 2) ? (len + 1) : len;

+

+ build_append_int_noprefix(table_data, aligned_len, 2); /* Length */

+ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */

+

+ /* ISA string length including NUL */

+ build_append_int_noprefix(table_data, strlen(isa) + 1, 2);

+ g_array_append_vals(table_data, isa, strlen(isa) + 1); /* ISA string */

+

+ if (aligned_len != len) {

+ build_append_int_noprefix(table_data, 0x0, 1); /* Optional Padding */

+ }

+

+ /* Hart Info Node */

+ for (int i = 0; i < arch_ids->len; i++) {

+ build_append_int_noprefix(table_data, 0xFFFF, 2); /* Type */

+ build_append_int_noprefix(table_data, 16, 2); /* Length */

+ build_append_int_noprefix(table_data, 0x1, 2); /* Revision */

+ build_append_int_noprefix(table_data, 1, 2); /* Number of offsets */

+ build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */

+ build_append_int_noprefix(table_data, isa_offset, 4); /* Offsets[0] */

+ }

+

+ acpi_table_end(linker, &table);

+}

+

+/* FADT */

+static void build_fadt_rev6(GArray *table_data,

+ BIOSLinker *linker,

+ RISCVVirtState *s,

+ unsigned dsdt_tbl_offset)

+{

+ AcpiFadtData fadt = {

+ .rev = 6,

+ .minor_ver = 5,

+ .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,

+ .xdsdt_tbl_offset = &dsdt_tbl_offset,

+ };

+

+ build_fadt(table_data, linker, &fadt, s->oem_id, s->oem_table_id);

+}

+

+/* DSDT */

+static void build_dsdt(GArray *table_data,

+ BIOSLinker *linker,

+ RISCVVirtState *s)

+{

+ Aml *scope, *dsdt;

+ const MemMapEntry *memmap = s->memmap;

+ AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = s->oem_id,

+ .oem_table_id = s->oem_table_id };

+

+

+ acpi_table_begin(&table, table_data);

+ dsdt = init_aml_allocator();

+

+ /*

+ * When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.

+ * While UEFI can use libfdt to disable the RTC device node in the DTB that

+ * it passes to the OS, it cannot modify AML. Therefore, we won't generate

+ * the RTC ACPI device at all when using UEFI.

+ */

+ scope = aml_scope("\\_SB");

+ acpi_dsdt_add_cpus(scope, s);

+

+ acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);

+

+ aml_append(dsdt, scope);

+

+ /* copy AML table into ACPI tables blob and patch header there */

+ g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);

+

+ acpi_table_end(linker, &table);

+ free_aml_allocator();

+}

+

+/*

+ * ACPI spec, Revision 6.5+

+ * 5.2.12 Multiple APIC Description Table (MADT)

+ * REF: https://github.com/riscv-non-isa/riscv-acpi/issues/15

+ * https://drive.google.com/file/d/1R6k4MshhN3WTT-hwqAquu5nX6xSEqK2l/view

+ */

+static void build_madt(GArray *table_data,

+ BIOSLinker *linker,

+ RISCVVirtState *s)

+{

+ MachineClass *mc = MACHINE_GET_CLASS(s);

+ MachineState *ms = MACHINE(s);

+ const CPUArchIdList *arch_ids = mc->possible_cpu_arch_ids(ms);

+

+ AcpiTable table = { .sig = "APIC", .rev = 6, .oem_id = s->oem_id,

+ .oem_table_id = s->oem_table_id };

+

+ acpi_table_begin(&table, table_data);

+ /* Local Interrupt Controller Address */

+ build_append_int_noprefix(table_data, 0, 4);

+ build_append_int_noprefix(table_data, 0, 4); /* MADT Flags */

+

+ /* RISC-V Local INTC structures per HART */

+ for (int i = 0; i < arch_ids->len; i++) {

+ riscv_acpi_madt_add_rintc(i, arch_ids, table_data);

+ }

+

+ acpi_table_end(linker, &table);

+}

+

+static void virt_acpi_build(RISCVVirtState *s, AcpiBuildTables *tables)

+{

+ GArray *table_offsets;

+ unsigned dsdt, xsdt;

+ GArray *tables_blob = tables->table_data;

+

+ table_offsets = g_array_new(false, true,

+ sizeof(uint32_t));

+

+ bios_linker_loader_alloc(tables->linker,

+ ACPI_BUILD_TABLE_FILE, tables_blob,

+ 64, false);

+

+ /* DSDT is pointed to by FADT */

+ dsdt = tables_blob->len;

+ build_dsdt(tables_blob, tables->linker, s);

+

+ /* FADT and others pointed to by XSDT */

+ acpi_add_table(table_offsets, tables_blob);

+ build_fadt_rev6(tables_blob, tables->linker, s, dsdt);

+

+ acpi_add_table(table_offsets, tables_blob);

+ build_madt(tables_blob, tables->linker, s);

+

+ acpi_add_table(table_offsets, tables_blob);

+ build_rhct(tables_blob, tables->linker, s);

+

+ /* XSDT is pointed to by RSDP */

+ xsdt = tables_blob->len;

+ build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,

+ s->oem_table_id);

+

+ /* RSDP is in FSEG memory, so allocate it separately */

+ {

+ AcpiRsdpData rsdp_data = {

+ .revision = 2,

+ .oem_id = s->oem_id,

+ .xsdt_tbl_offset = &xsdt,

+ .rsdt_tbl_offset = NULL,

+ };

+ build_rsdp(tables->rsdp, tables->linker, &rsdp_data);

+ }

+

+ /*

+ * The align size is 128, warn if 64k is not enough therefore

+ * the align size could be resized.

+ */

+ if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {

+ warn_report("ACPI table size %u exceeds %d bytes,"

+ " migration may not work",

+ tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);

+ error_printf("Try removing some objects.");

+ }

+

+ acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);

+

+ /* Clean up memory that's no longer used */

+ g_array_free(table_offsets, true);

+}

+

+static void acpi_ram_update(MemoryRegion *mr, GArray *data)

+{

+ uint32_t size = acpi_data_len(data);

+

+ /*

+ * Make sure RAM size is correct - in case it got changed

+ * e.g. by migration

+ */

+ memory_region_ram_resize(mr, size, &error_abort);

+

+ memcpy(memory_region_get_ram_ptr(mr), data->data, size);

+ memory_region_set_dirty(mr, 0, size);

+}

+

+static void virt_acpi_build_update(void *build_opaque)

+{

+ AcpiBuildState *build_state = build_opaque;

+ AcpiBuildTables tables;

+

+ /* No state to update or already patched? Nothing to do. */

+ if (!build_state || build_state->patched) {

+ return;

+ }

+

+ build_state->patched = true;

+

+ acpi_build_tables_init(&tables);

+

+ virt_acpi_build(RISCV_VIRT_MACHINE(qdev_get_machine()), &tables);

+

+ acpi_ram_update(build_state->table_mr, tables.table_data);

+ acpi_ram_update(build_state->rsdp_mr, tables.rsdp);

+ acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);

+

+ acpi_build_tables_cleanup(&tables, true);

+}

+

+static void virt_acpi_build_reset(void *build_opaque)

+{

+ AcpiBuildState *build_state = build_opaque;

+ build_state->patched = false;

+}

+

+static const VMStateDescription vmstate_virt_acpi_build = {

+ .name = "virt_acpi_build",

+ .version_id = 1,

+ .minimum_version_id = 1,

+ .fields = (VMStateField[]) {

+ VMSTATE_BOOL(patched, AcpiBuildState),

+ VMSTATE_END_OF_LIST()

+ },

+};

+

+void virt_acpi_setup(RISCVVirtState *s)

+{

+ AcpiBuildTables tables;

+ AcpiBuildState *build_state;

+

+ build_state = g_malloc0(sizeof *build_state);

+

+ acpi_build_tables_init(&tables);

+ virt_acpi_build(s, &tables);

+

+ /* Now expose it all to Guest */

+ build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,

+ build_state, tables.table_data,

+ ACPI_BUILD_TABLE_FILE);

+ assert(build_state->table_mr != NULL);

+

+ build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,

+ build_state,

+ tables.linker->cmd_blob,

+ ACPI_BUILD_LOADER_FILE);

+

+ build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,

+ build_state, tables.rsdp,

+ ACPI_BUILD_RSDP_FILE);

+

+ qemu_register_reset(virt_acpi_build_reset, build_state);

+ virt_acpi_build_reset(build_state);

+ vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);

+

+ /*

+ * Clean up tables but don't free the memory: we track it

+ * in build_state.

+ */

+ acpi_build_tables_cleanup(&tables, false);

+}

+#include "hw/acpi/aml-build.h"

+#include "qapi/qapi-visit-common.h"

+ char *name, *cpu_name, *core_name, *intc_name, *sv_name;

+ uint8_t satp_mode_max;

+

+ satp_mode_max = satp_mode_max_from_map(

+ s->soc[socket].harts[cpu].cfg.satp_mode.map);

+ sv_name = g_strdup_printf("riscv,%s",

+ satp_mode_str(satp_mode_max, is_32_bit));

+ qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", sv_name);

+ g_free(sv_name);

+

+

+

+ if (cpu_ptr->cfg.ext_icbom) {

+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cbom-block-size",

+ cpu_ptr->cfg.cbom_blocksize);

+ }

+

+ if (cpu_ptr->cfg.ext_icboz) {

+ qemu_fdt_setprop_cell(ms->fdt, cpu_name, "riscv,cboz-block-size",

+ cpu_ptr->cfg.cboz_blocksize);

+ }

+

+

+ if (virt_is_acpi_enabled(s)) {

+ virt_acpi_setup(s);

+ }

+ s->memmap = virt_memmap;

+

+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);

+

+ s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);

+ s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);

+ s->acpi = ON_OFF_AUTO_AUTO;

+bool virt_is_acpi_enabled(RISCVVirtState *s)

+{

+ return s->acpi != ON_OFF_AUTO_OFF;

+}

+

+static void virt_get_acpi(Object *obj, Visitor *v, const char *name,

+ void *opaque, Error **errp)

+{

+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);

+ OnOffAuto acpi = s->acpi;

+

+ visit_type_OnOffAuto(v, name, &acpi, errp);

+}

+

+static void virt_set_acpi(Object *obj, Visitor *v, const char *name,

+ void *opaque, Error **errp)

+{

+ RISCVVirtState *s = RISCV_VIRT_MACHINE(obj);

+

+ visit_type_OnOffAuto(v, name, &s->acpi, errp);

+}

+

+ object_class_property_add(oc, "acpi", "OnOffAuto",

+ virt_get_acpi, virt_set_acpi,

+ NULL, NULL);

+ object_class_property_set_description(oc, "acpi",

+ "Enable ACPI");

+/* This is the one state transition the controller can do by itself */

+static bool ohci_resume(OHCIState *s)

+{

+ if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {

+ trace_usb_ohci_remote_wakeup(s->name);

+ s->ctl &= ~OHCI_CTL_HCFS;

+ s->ctl |= OHCI_USB_RESUME;

+ return true;

+ }

+ return false;

+}

+

+ /* CSC is a wakeup event */

+ if (ohci_resume(ohci)) {

+ ohci_set_interrupt(ohci, OHCI_INTR_RD);

+ }

+ if (ohci_resume(s)) {

+#include "hw/pci/pci_bus.h"

+ if ((s->real_device.domain == XEN_PCI_IGD_DOMAIN) &&

+ (s->real_device.bus == XEN_PCI_IGD_BUS) &&

+ (s->real_device.dev == XEN_PCI_IGD_DEV) &&

+ (s->real_device.func == XEN_PCI_IGD_FN)) {

+void xen_igd_reserve_slot(PCIBus *pci_bus)

+{

+ if (!xen_igd_gfx_pt_enabled()) {

+ return;

+ }

+

+ XEN_PT_LOG(0, "Reserving PCI slot 2 for IGD\n");

+ pci_bus->slot_reserved_mask |= XEN_PCI_IGD_SLOT_MASK;

+}

+

+static void xen_igd_clear_slot(DeviceState *qdev, Error **errp)

+{

+ ERRP_GUARD();

+ PCIDevice *pci_dev = (PCIDevice *)qdev;

+ XenPCIPassthroughState *s = XEN_PT_DEVICE(pci_dev);

+ XenPTDeviceClass *xpdc = XEN_PT_DEVICE_GET_CLASS(s);

+ PCIBus *pci_bus = pci_get_bus(pci_dev);

+

+ xen_host_pci_device_get(&s->real_device,

+ s->hostaddr.domain, s->hostaddr.bus,

+ s->hostaddr.slot, s->hostaddr.function,

+ errp);

+ if (*errp) {

+ error_append_hint(errp, "Failed to \"open\" the real pci device");

+ return;

+ }

+

+ if (!(pci_bus->slot_reserved_mask & XEN_PCI_IGD_SLOT_MASK)) {

+ xpdc->pci_qdev_realize(qdev, errp);

+ return;

+ }

+

+ if (is_igd_vga_passthrough(&s->real_device) &&

+ s->real_device.domain == XEN_PCI_IGD_DOMAIN &&

+ s->real_device.bus == XEN_PCI_IGD_BUS &&

+ s->real_device.dev == XEN_PCI_IGD_DEV &&

+ s->real_device.func == XEN_PCI_IGD_FN &&

+ s->real_device.vendor_id == PCI_VENDOR_ID_INTEL) {

+ pci_bus->slot_reserved_mask &= ~XEN_PCI_IGD_SLOT_MASK;

+ XEN_PT_LOG(pci_dev, "Intel IGD found, using slot 2\n");

+ }

+ xpdc->pci_qdev_realize(qdev, errp);

+}

+

+ XenPTDeviceClass *xpdc = XEN_PT_DEVICE_CLASS(klass);

+ xpdc->pci_qdev_realize = dc->realize;

+ dc->realize = xen_igd_clear_slot;

+ .class_size = sizeof(XenPTDeviceClass),

+#define XEN_PT_DEVICE_CLASS(klass) \

+ OBJECT_CLASS_CHECK(XenPTDeviceClass, klass, TYPE_XEN_PT_DEVICE)

+#define XEN_PT_DEVICE_GET_CLASS(obj) \

+ OBJECT_GET_CLASS(XenPTDeviceClass, obj, TYPE_XEN_PT_DEVICE)

+

+typedef void (*XenPTQdevRealize)(DeviceState *qdev, Error **errp);

+

+typedef struct XenPTDeviceClass {

+ PCIDeviceClass parent_class;

+ XenPTQdevRealize pci_qdev_realize;

+} XenPTDeviceClass;

+

+void xen_igd_reserve_slot(PCIBus *pci_bus);

+#define XEN_PCI_IGD_DOMAIN 0

+#define XEN_PCI_IGD_BUS 0

+#define XEN_PCI_IGD_DEV 2

+#define XEN_PCI_IGD_FN 0

+#define XEN_PCI_IGD_SLOT_MASK \

+ (1UL << PCI_SLOT(PCI_DEVFN(XEN_PCI_IGD_DEV, XEN_PCI_IGD_FN)))

+

+ uint32_t val = 0;

+

+void xen_igd_reserve_slot(PCIBus *pci_bus)

+{

+}

+ smp_mb__after_rmw(); \

+#include "hw/registerfields.h"

+

+typedef struct QEMU_PACKED NvmeEndGrpLog {

+ uint8_t critical_warning;

+ uint8_t rsvd[2];

+ uint8_t avail_spare;

+ uint8_t avail_spare_thres;

+ uint8_t percet_used;

+ uint8_t rsvd1[26];

+ uint64_t end_estimate[2];

+ uint64_t data_units_read[2];

+ uint64_t data_units_written[2];

+ uint64_t media_units_written[2];

+ uint64_t host_read_commands[2];

+ uint64_t host_write_commands[2];

+ uint64_t media_integrity_errors[2];

+ uint64_t no_err_info_log_entries[2];

+ uint8_t rsvd2[352];

+} NvmeEndGrpLog;

+

+ NVME_ADM_CMD_DIRECTIVE_SEND = 0x19,

+ NVME_ADM_CMD_DIRECTIVE_RECV = 0x1a,

+ NVME_CMD_IO_MGMT_RECV = 0x12,

+ NVME_CMD_IO_MGMT_SEND = 0x1d,

+ uint8_t dsmgmt;

+ uint8_t rsvd;

+ uint16_t dspec;

+ NVME_FDP_DISABLED = 0x0029,

+ NVME_INVALID_PHID_LIST = 0x002a,

+ NVME_LOG_ERROR_INFO = 0x01,

+ NVME_LOG_SMART_INFO = 0x02,

+ NVME_LOG_FW_SLOT_INFO = 0x03,

+ NVME_LOG_CHANGED_NSLIST = 0x04,

+ NVME_LOG_CMD_EFFECTS = 0x05,

+ NVME_LOG_ENDGRP = 0x09,

+ NVME_LOG_FDP_CONFS = 0x20,

+ NVME_LOG_FDP_RUH_USAGE = 0x21,

+ NVME_LOG_FDP_STATS = 0x22,

+ NVME_LOG_FDP_EVENTS = 0x23,

+ uint8_t rsvd332[6];

+ uint16_t nsetidmax;

+ uint16_t endgidmax;

+ uint8_t rsvd342[170];

+ NVME_CTRATT_ENDGRPS = 1 << 4,

+ NVME_CTRATT_FDPS = 1 << 19,

+ NVME_OACS_SECURITY = 1 << 0,

+ NVME_OACS_FORMAT = 1 << 1,

+ NVME_OACS_FW = 1 << 2,

+ NVME_OACS_NS_MGMT = 1 << 3,

+ NVME_OACS_DIRECTIVES = 1 << 5,

+ NVME_OACS_DBBUF = 1 << 8,

+#define NVME_AEC_ENDGRP_NOTICE(aec) ((aec >> 14) & 0x1)

+ NVME_FDP_MODE = 0x1d,

+ NVME_FDP_EVENTS = 0x1e,

+ uint8_t rsvd81[18];

+ uint8_t nsattr;

+ uint16_t nvmsetid;

+ uint16_t endgid;

+typedef struct NvmeDirectiveIdentify {

+ uint8_t supported;

+ uint8_t unused1[31];

+ uint8_t enabled;

+ uint8_t unused33[31];

+ uint8_t persistent;

+ uint8_t unused65[31];

+ uint8_t rsvd64[4000];

+} NvmeDirectiveIdentify;

+

+enum NvmeDirectiveTypes {

+ NVME_DIRECTIVE_IDENTIFY = 0x0,

+ NVME_DIRECTIVE_DATA_PLACEMENT = 0x2,

+};

+

+enum NvmeDirectiveOperations {

+ NVME_DIRECTIVE_RETURN_PARAMS = 0x1,

+};

+

+typedef struct QEMU_PACKED NvmeFdpConfsHdr {

+ uint16_t num_confs;

+ uint8_t version;

+ uint8_t rsvd3;

+ uint32_t size;

+ uint8_t rsvd8[8];

+} NvmeFdpConfsHdr;

+

+REG8(FDPA, 0x0)

+ FIELD(FDPA, RGIF, 0, 4)

+ FIELD(FDPA, VWC, 4, 1)

+ FIELD(FDPA, VALID, 7, 1);

+

+typedef struct QEMU_PACKED NvmeFdpDescrHdr {

+ uint16_t descr_size;

+ uint8_t fdpa;

+ uint8_t vss;

+ uint32_t nrg;

+ uint16_t nruh;

+ uint16_t maxpids;

+ uint32_t nnss;

+ uint64_t runs;

+ uint32_t erutl;

+ uint8_t rsvd28[36];

+} NvmeFdpDescrHdr;

+

+enum NvmeRuhType {

+ NVME_RUHT_INITIALLY_ISOLATED = 1,

+ NVME_RUHT_PERSISTENTLY_ISOLATED = 2,

+};

+

+typedef struct QEMU_PACKED NvmeRuhDescr {

+ uint8_t ruht;

+ uint8_t rsvd1[3];

+} NvmeRuhDescr;

+

+typedef struct QEMU_PACKED NvmeRuhuLog {

+ uint16_t nruh;

+ uint8_t rsvd2[6];

+} NvmeRuhuLog;

+

+enum NvmeRuhAttributes {

+ NVME_RUHA_UNUSED = 0,

+ NVME_RUHA_HOST = 1,

+ NVME_RUHA_CTRL = 2,

+};

+

+typedef struct QEMU_PACKED NvmeRuhuDescr {

+ uint8_t ruha;

+ uint8_t rsvd1[7];

+} NvmeRuhuDescr;

+

+typedef struct QEMU_PACKED NvmeFdpStatsLog {

+ uint64_t hbmw[2];

+ uint64_t mbmw[2];

+ uint64_t mbe[2];

+ uint8_t rsvd48[16];

+} NvmeFdpStatsLog;

+

+typedef struct QEMU_PACKED NvmeFdpEventsLog {

+ uint32_t num_events;

+ uint8_t rsvd4[60];

+} NvmeFdpEventsLog;

+

+enum NvmeFdpEventType {

+ FDP_EVT_RU_NOT_FULLY_WRITTEN = 0x0,

+ FDP_EVT_RU_ATL_EXCEEDED = 0x1,

+ FDP_EVT_CTRL_RESET_RUH = 0x2,

+ FDP_EVT_INVALID_PID = 0x3,

+ FDP_EVT_MEDIA_REALLOC = 0x80,

+ FDP_EVT_RUH_IMPLICIT_RU_CHANGE = 0x81,

+};

+

+enum NvmeFdpEventFlags {

+ FDPEF_PIV = 1 << 0,

+ FDPEF_NSIDV = 1 << 1,

+ FDPEF_LV = 1 << 2,

+};

+

+typedef struct QEMU_PACKED NvmeFdpEvent {

+ uint8_t type;

+ uint8_t flags;

+ uint16_t pid;

+ uint64_t timestamp;

+ uint32_t nsid;

+ uint64_t type_specific[2];

+ uint16_t rgid;

+ uint8_t ruhid;

+ uint8_t rsvd35[5];

+ uint64_t vendor[3];

+} NvmeFdpEvent;

+

+typedef struct QEMU_PACKED NvmePhidList {

+ uint16_t nnruhd;

+ uint8_t rsvd2[6];

+} NvmePhidList;

+

+typedef struct QEMU_PACKED NvmePhidDescr {

+ uint8_t ruht;

+ uint8_t rsvd1;

+ uint16_t ruhid;

+} NvmePhidDescr;

+

+REG32(FEAT_FDP, 0x0)

+ FIELD(FEAT_FDP, FDPE, 0, 1)

+ FIELD(FEAT_FDP, CONF_NDX, 8, 8);

+

+typedef struct QEMU_PACKED NvmeFdpEventDescr {

+ uint8_t evt;

+ uint8_t evta;

+} NvmeFdpEventDescr;

+

+REG32(NVME_IOMR, 0x0)

+ FIELD(NVME_IOMR, MO, 0, 8)

+ FIELD(NVME_IOMR, MOS, 16, 16);

+

+enum NvmeIomr2Mo {

+ NVME_IOMR_MO_NOP = 0x0,

+ NVME_IOMR_MO_RUH_STATUS = 0x1,

+ NVME_IOMR_MO_VENDOR_SPECIFIC = 0x255,

+};

+

+typedef struct QEMU_PACKED NvmeRuhStatus {

+ uint8_t rsvd0[14];

+ uint16_t nruhsd;

+} NvmeRuhStatus;

+

+typedef struct QEMU_PACKED NvmeRuhStatusDescr {

+ uint16_t pid;

+ uint16_t ruhid;

+ uint32_t earutr;

+ uint64_t ruamw;

+ uint8_t rsvd16[16];

+} NvmeRuhStatusDescr;

+

+REG32(NVME_IOMS, 0x0)

+ FIELD(NVME_IOMS, MO, 0, 8)

+ FIELD(NVME_IOMS, MOS, 16, 16);

+

+enum NvmeIoms2Mo {

+ NVME_IOMS_MO_NOP = 0x0,

+ NVME_IOMS_MO_RUH_UPDATE = 0x1,

+};

+

+ QEMU_BUILD_BUG_ON(sizeof(NvmeEndGrpLog) != 512);

+ QEMU_BUILD_BUG_ON(sizeof(NvmeDirectiveIdentify) != 4096);

+ AW_H3_DEV_TWI1,

+ AW_H3_DEV_TWI2,

+ AW_H3_DEV_R_TWI,

+ AWI2CState i2c1;

+ AWI2CState i2c2;

+ AWI2CState r_twi;

+

+/** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */

+#define TYPE_AW_I2C_SUN6I TYPE_AW_I2C "-sun6i"

+

+

+ bool irq_clear_inverted;

+ uint32_t num_vps;

+ uint32_t num_irq;

+ uint8_t ltim; /* Edge/Level Bank Select (pre-PIIX, chip-wide) */

+#include "hw/pci/pci_device.h"

+#include "audio/audio.h"

+typedef struct {

+ uint8_t stat;

+ uint8_t type;

+ uint32_t base;

+ uint32_t curr;

+ uint32_t addr;

+ uint32_t clen;

+} ViaAC97SGDChannel;

+

+OBJECT_DECLARE_SIMPLE_TYPE(ViaAC97State, VIA_AC97);

+

+struct ViaAC97State {

+ PCIDevice dev;

+ QEMUSoundCard card;

+ MemoryRegion sgd;

+ MemoryRegion fm;

+ MemoryRegion midi;

+ SWVoiceOut *vo;

+ ViaAC97SGDChannel aur;

+ uint16_t codec_regs[128];

+ uint32_t ac97_cmd;

+};

+

+/**

+ * unpack_efi_zboot_image:

+ * @buffer: pointer to a variable holding the address of a buffer containing the

+ * image

+ * @size: pointer to a variable holding the size of the buffer

+ *

+ * Check whether the buffer contains a EFI zboot image, and if it does, extract

+ * the compressed payload and decompress it into a new buffer. If successful,

+ * the old buffer is freed, and the *buffer and size variables pointed to by the

+ * function arguments are updated to refer to the newly populated buffer.

+ *

+ * Returns 0 if the image could not be identified as a EFI zboot image.

+ * Returns -1 if the buffer contents were identified as a EFI zboot image, but

+ * unpacking failed for any reason.

+ * Returns the size of the decompressed payload if decompression was performed

+ * successfully.

+ */

+ssize_t unpack_efi_zboot_image(uint8_t **buffer, int *size);

+

+ uint32_t num_vps;

+ uint32_t num_fifo;

+ uint32_t num_semaphores;

+ uint64_t *saar;

+ MIPSCPU *cpu0;

+ char *oem_id;

+ char *oem_table_id;

+ OnOffAuto acpi;

+ const MemMapEntry *memmap;

+bool virt_is_acpi_enabled(RISCVVirtState *s);

+void virt_acpi_setup(RISCVVirtState *vms);

+/*

+ * SEQ_CST is weaker than the older __sync_* builtins and Linux

+ * kernel read-modify-write atomics. Provide a macro to obtain

+ * the same semantics.

+ */

+#if !defined(QEMU_SANITIZE_THREAD) && \

+ (defined(__i386__) || defined(__x86_64__) || defined(__s390x__))

+# define smp_mb__before_rmw() signal_barrier()

+# define smp_mb__after_rmw() signal_barrier()

+#else

+# define smp_mb__before_rmw() smp_mb()

+# define smp_mb__after_rmw() smp_mb()

+#endif

+

+# define qatomic_mb_set(ptr, i) \

+ ({ (void)qatomic_xchg(ptr, i); smp_mb__after_rmw(); })

+Subproject 6b5188ca14e59ce7bf71afe4e7d3d557c3d31bf

+ g_string_append_printf(buf, "%24s %8s %18s %18s %18s %18s %3s\n",

+ "Block Name", "PSize", "Offset", "Used", "Total",

+ "HVA", "RO");

+

+ " 0x%016" PRIx64 " 0x%016" PRIx64 " %3s\n",

+ block->idstr, psize,

+ (uint64_t)block->max_length,

+ (uint64_t)(uintptr_t)block->host,

+ block->mr->readonly ? "ro" : "rw");

+

+ /* Write map_client_list before reading in_use. */

+ smp_mb();

+ /* Clear in_use before reading map_client_list. */

+ DynamicGDBXMLInfo dyn_m_systemreg_xml;

+ DynamicGDBXMLInfo dyn_m_secextreg_xml;

+/*

+ * Return true if exception levels below EL3 are in secure state,

+ assert(!arm_feature(env, ARM_FEATURE_M));

+ assert(!arm_feature(env, ARM_FEATURE_M));

+ if (arm_feature(env, ARM_FEATURE_M)) {

+ return env->v7m.secure;

+ }

+static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)

+typedef enum {

+ M_SYSREG_MSP,

+ M_SYSREG_PSP,

+ M_SYSREG_PRIMASK,

+ M_SYSREG_CONTROL,

+ M_SYSREG_BASEPRI,

+ M_SYSREG_FAULTMASK,

+ M_SYSREG_MSPLIM,

+ M_SYSREG_PSPLIM,

+} MProfileSysreg;

+

+static const struct {

+ const char *name;

+ int feature;

+} m_sysreg_def[] = {

+ [M_SYSREG_MSP] = { "msp", ARM_FEATURE_M },

+ [M_SYSREG_PSP] = { "psp", ARM_FEATURE_M },

+ [M_SYSREG_PRIMASK] = { "primask", ARM_FEATURE_M },

+ [M_SYSREG_CONTROL] = { "control", ARM_FEATURE_M },

+ [M_SYSREG_BASEPRI] = { "basepri", ARM_FEATURE_M_MAIN },

+ [M_SYSREG_FAULTMASK] = { "faultmask", ARM_FEATURE_M_MAIN },

+ [M_SYSREG_MSPLIM] = { "msplim", ARM_FEATURE_V8 },

+ [M_SYSREG_PSPLIM] = { "psplim", ARM_FEATURE_V8 },

+static uint32_t *m_sysreg_ptr(CPUARMState *env, MProfileSysreg reg, bool sec)

+{

+ uint32_t *ptr;

+

+ switch (reg) {

+ case M_SYSREG_MSP:

+ ptr = arm_v7m_get_sp_ptr(env, sec, false, true);

+ break;

+ case M_SYSREG_PSP:

+ ptr = arm_v7m_get_sp_ptr(env, sec, true, true);

+ break;

+ case M_SYSREG_MSPLIM:

+ ptr = &env->v7m.msplim[sec];

+ break;

+ case M_SYSREG_PSPLIM:

+ ptr = &env->v7m.psplim[sec];

+ break;

+ case M_SYSREG_PRIMASK:

+ ptr = &env->v7m.primask[sec];

+ break;

+ case M_SYSREG_BASEPRI:

+ ptr = &env->v7m.basepri[sec];

+ break;

+ case M_SYSREG_FAULTMASK:

+ ptr = &env->v7m.faultmask[sec];

+ break;

+ case M_SYSREG_CONTROL:

+ ptr = &env->v7m.control[sec];

+ break;

+ default:

+ return NULL;

+ }

+ return arm_feature(env, m_sysreg_def[reg].feature) ? ptr : NULL;

+}

+

+static int m_sysreg_get(CPUARMState *env, GByteArray *buf,

+ MProfileSysreg reg, bool secure)

+{

+ uint32_t *ptr = m_sysreg_ptr(env, reg, secure);

+

+ if (ptr == NULL) {

+ return 0;

+ }

+ return gdb_get_reg32(buf, *ptr);

+}

+

+static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)

+{

+ /*

+ * Here, we emulate MRS instruction, where CONTROL has a mix of

+ * banked and non-banked bits.

+ */

+ if (reg == M_SYSREG_CONTROL) {

+ return gdb_get_reg32(buf, arm_v7m_mrs_control(env, env->v7m.secure));

+ }

+ return m_sysreg_get(env, buf, reg, env->v7m.secure);

+}

+static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)

+{

+ return 0; /* TODO */

+}

+static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)

+ CPUARMState *env = &cpu->env;

+ int base_reg = orig_base_reg;

+ int i;

+

+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.m-system\">\n");

+ for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {

+ if (arm_feature(env, m_sysreg_def[i].feature)) {

+ g_string_append_printf(s,

+ "<reg name=\"%s\" bitsize=\"32\" regnum=\"%d\"/>\n",

+ m_sysreg_def[i].name, base_reg++);

+ g_string_append_printf(s, "</feature>");

+ cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);

+ cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;

+

+ return cpu->dyn_m_systemreg_xml.num;

+}

+

+#ifndef CONFIG_USER_ONLY

+/*

+ * For user-only, we see the non-secure registers via m_systemreg above.

+ * For secext, encode the non-secure view as even and secure view as odd.

+ */

+static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)

+{

+ return m_sysreg_get(env, buf, reg >> 1, reg & 1);

+}

+

+static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)

+{

+ return 0; /* TODO */

+}

+

+static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)

+{

+ ARMCPU *cpu = ARM_CPU(cs);

+ GString *s = g_string_new(NULL);

+ int base_reg = orig_base_reg;

+ int i;

+

+ g_string_printf(s, "<?xml version=\"1.0\"?>");

+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");

+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.arm.secext\">\n");

+ for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {

+ "<reg name=\"%s_ns\" bitsize=\"32\" regnum=\"%d\"/>\n",

+ m_sysreg_def[i].name, base_reg++);

+ "<reg name=\"%s_s\" bitsize=\"32\" regnum=\"%d\"/>\n",

+ m_sysreg_def[i].name, base_reg++);

+

+ cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);

+ cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;

+ return cpu->dyn_m_secextreg_xml.num;

+#endif

+ } else if (strcmp(xmlname, "arm-m-system.xml") == 0) {

+ return cpu->dyn_m_systemreg_xml.desc;

+#ifndef CONFIG_USER_ONLY

+ } else if (strcmp(xmlname, "arm-m-secext.xml") == 0) {

+ return cpu->dyn_m_secextreg_xml.desc;

+#endif

+ int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);

+ gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,

+ aarch64_gdb_set_sve_reg, nreg,

+ gdb_register_coprocessor(cs, aarch64_gdb_get_fpu_reg,

+ aarch64_gdb_set_fpu_reg,

+ if (isar_feature_aa64_pauth(&cpu->isar)) {

+ gdb_register_coprocessor(cs, aarch64_gdb_get_pauth_reg,

+ aarch64_gdb_set_pauth_reg,

+ 4, "aarch64-pauth.xml", 0);

+ }

+ if (arm_feature(env, ARM_FEATURE_M)) {

+ gdb_register_coprocessor(cs,

+ arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,

+ arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),

+ "arm-m-system.xml", 0);

+#ifndef CONFIG_USER_ONLY

+ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {

+ gdb_register_coprocessor(cs,

+ arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,

+ arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),

+ "arm-m-secext.xml", 0);

+ }

+#endif

+ }

+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)

+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)

+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)

+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)

+

+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)

+{

+ switch (reg) {

+ case 0: /* pauth_dmask */

+ case 1: /* pauth_cmask */

+ case 2: /* pauth_dmask_high */

+ case 3: /* pauth_cmask_high */

+ /*

+ * Note that older versions of this feature only contained

+ * pauth_{d,c}mask, for use with Linux user processes, and

+ * thus exclusively in the low half of the address space.

+ *

+ * To support system mode, and to debug kernels, two new regs

+ * were added to cover the high half of the address space.

+ * For the purpose of pauth_ptr_mask, we can use any well-formed

+ * address within the address space half -- here, 0 and -1.

+ */

+ {

+ bool is_data = !(reg & 1);

+ bool is_high = reg & 2;

+ uint64_t mask = pauth_ptr_mask(env, -is_high, is_data);

+ return gdb_get_reg64(buf, mask);

+ }

+ default:

+ return 0;

+ }

+}

+

+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)

+{

+ /* All pseudo registers are read-only. */

+ return 0;

+}

+

+static void output_vector_union_type(GString *s, int reg_width,

+ const char *name)

+{

+ struct TypeSize {

+ const char *gdb_type;

+ short size;

+ char sz, suffix;

+ };

+

+ static const struct TypeSize vec_lanes[] = {

+ /* quads */

+ { "uint128", 128, 'q', 'u' },

+ { "int128", 128, 'q', 's' },

+ /* 64 bit */

+ { "ieee_double", 64, 'd', 'f' },

+ { "uint64", 64, 'd', 'u' },

+ { "int64", 64, 'd', 's' },

+ /* 32 bit */

+ { "ieee_single", 32, 's', 'f' },

+ { "uint32", 32, 's', 'u' },

+ { "int32", 32, 's', 's' },

+ /* 16 bit */

+ { "ieee_half", 16, 'h', 'f' },

+ { "uint16", 16, 'h', 'u' },

+ { "int16", 16, 'h', 's' },

+ /* bytes */

+ { "uint8", 8, 'b', 'u' },

+ { "int8", 8, 'b', 's' },

+ };

+

+ static const char suf[] = { 'b', 'h', 's', 'd', 'q' };

+ int i, j;

+

+ /* First define types and totals in a whole VL */

+ for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {

+ g_string_append_printf(s,

+ "<vector id=\"%s%c%c\" type=\"%s\" count=\"%d\"/>",

+ name, vec_lanes[i].sz, vec_lanes[i].suffix,

+ vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);

+ }

+

+ /*

+ * Now define a union for each size group containing unsigned and

+ * signed and potentially float versions of each size from 128 to

+ * 8 bits.

+ */

+ for (i = 0; i < ARRAY_SIZE(suf); i++) {

+ int bits = 8 << i;

+

+ g_string_append_printf(s, "<union id=\"%sn%c\">", name, suf[i]);

+ for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {

+ if (vec_lanes[j].size == bits) {

+ g_string_append_printf(s, "<field name=\"%c\" type=\"%s%c%c\"/>",

+ vec_lanes[j].suffix, name,

+ vec_lanes[j].sz, vec_lanes[j].suffix);

+ }

+ }

+ g_string_append(s, "</union>");

+ }

+

+ /* And now the final union of unions */

+ g_string_append_printf(s, "<union id=\"%s\">", name);

+ for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {

+ g_string_append_printf(s, "<field name=\"%c\" type=\"%sn%c\"/>",

+ suf[i], name, suf[i]);

+ }

+ g_string_append(s, "</union>");

+}

+

+int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)

+{

+ ARMCPU *cpu = ARM_CPU(cs);

+ GString *s = g_string_new(NULL);

+ DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;

+ int reg_width = cpu->sve_max_vq * 128;

+ int pred_width = cpu->sve_max_vq * 16;

+ int base_reg = orig_base_reg;

+ int i;

+

+ g_string_printf(s, "<?xml version=\"1.0\"?>");

+ g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");

+ g_string_append_printf(s, "<feature name=\"org.gnu.gdb.aarch64.sve\">");

+

+ /* Create the vector union type. */

+ output_vector_union_type(s, reg_width, "svev");

+

+ /* Create the predicate vector type. */

+ g_string_append_printf(s,

+ "<vector id=\"svep\" type=\"uint8\" count=\"%d\"/>",

+ pred_width / 8);

+

+ /* Define the vector registers. */

+ for (i = 0; i < 32; i++) {

+ g_string_append_printf(s,

+ "<reg name=\"z%d\" bitsize=\"%d\""

+ " regnum=\"%d\" type=\"svev\"/>",

+ i, reg_width, base_reg++);

+ }

+

+ /* fpscr & status registers */

+ g_string_append_printf(s, "<reg name=\"fpsr\" bitsize=\"32\""

+ " regnum=\"%d\" group=\"float\""

+ " type=\"int\"/>", base_reg++);

+ g_string_append_printf(s, "<reg name=\"fpcr\" bitsize=\"32\""

+ " regnum=\"%d\" group=\"float\""

+ " type=\"int\"/>", base_reg++);

+

+ /* Define the predicate registers. */

+ for (i = 0; i < 16; i++) {

+ g_string_append_printf(s,

+ "<reg name=\"p%d\" bitsize=\"%d\""

+ " regnum=\"%d\" type=\"svep\"/>",

+ i, pred_width, base_reg++);

+ }

+ g_string_append_printf(s,

+ "<reg name=\"ffr\" bitsize=\"%d\""

+ " regnum=\"%d\" group=\"vector\""

+ " type=\"svep\"/>",

+ pred_width, base_reg++);

+

+ /* Define the vector length pseudo-register. */

+ g_string_append_printf(s,

+ "<reg name=\"vg\" bitsize=\"64\""

+ " regnum=\"%d\" type=\"int\"/>",

+ base_reg++);

+

+ g_string_append_printf(s, "</feature>");

+

+ info->desc = g_string_free(s, false);

+ info->num = base_reg - orig_base_reg;

+ return info->num;

+}

+ if (arm_feature(env, ARM_FEATURE_M)) {

+ return 0;

+ }

+int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);

+int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);

+int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);

+int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);

+int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);

+int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);

+int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);

+/* Read the CONTROL register as the MRS instruction would. */

+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure);

+

+/*

+ * Return a pointer to the location where we currently store the

+ * stack pointer for the requested security state and thread mode.

+ * This pointer will become invalid if the CPU state is updated

+ * such that the stack pointers are switched around (eg changing

+ * the SPSEL control bit).

+ */

+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure,

+ bool threadmode, bool spsel);

+

+/**

+ * pauth_ptr_mask:

+ * @env: cpu context

+ * @ptr: selects between TTBR0 and TTBR1

+ * @data: selects between TBI and TBID

+ *

+ * Return a mask of the bits of @ptr that contain the authentication code.

+ */

+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data);

+

+ * @tcr: VTCR_EL2 or VSTCR_EL2

+ * @ds: Effective value of TCR.DS.

+ * @iasize: Bitsize of IPAs

+ * Decode the starting level of the S2 lookup, returning INT_MIN if

+ * the configuration is invalid.

+static int check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, uint64_t tcr,

+ bool ds, int iasize, int stride)

+ int sl0, sl2, startlevel, granulebits, levels;

+ int s1_min_iasize, s1_max_iasize;

+ sl0 = extract32(tcr, 6, 2);

+ /*

+ * AArch64.S2InvalidTxSZ: While we checked tsz_oob near the top of

+ * get_phys_addr_lpae, that used aa64_va_parameters which apply

+ * to aarch64. If Stage1 is aarch32, the min_txsz is larger.

+ * See AArch64.S2MinTxSZ, where min_tsz is 24, translated to

+ * inputsize is 64 - 24 = 40.

+ */

+ if (iasize < 40 && !arm_el_is_aa64(&cpu->env, 1)) {

+ goto fail;

+ }

+

+ /*

+ * AArch64.S2InvalidSL: Interpretation of SL depends on the page size,

+ * so interleave AArch64.S2StartLevel.

+ */

+ case 9: /* 4KB */

+ /* SL2 is RES0 unless DS=1 & 4KB granule. */

+ sl2 = extract64(tcr, 33, 1);

+ if (ds && sl2) {

+ if (sl0 != 0) {

+ goto fail;

+ }

+ startlevel = -1;

+ } else {

+ startlevel = 2 - sl0;

+ switch (sl0) {

+ case 2:

+ if (arm_pamax(cpu) < 44) {

+ goto fail;

+ }

+ break;

+ case 3:

+ if (!cpu_isar_feature(aa64_st, cpu)) {

+ goto fail;

+ }

+ startlevel = 3;

+ break;

+ }

+ case 11: /* 16KB */

+ switch (sl0) {

+ case 2:

+ if (arm_pamax(cpu) < 42) {

+ goto fail;

+ }

+ break;

+ case 3:

+ if (!ds) {

+ goto fail;

+ }

+ break;

+ startlevel = 3 - sl0;

+ case 13: /* 64KB */

+ switch (sl0) {

+ case 2:

+ if (arm_pamax(cpu) < 44) {

+ goto fail;

+ }

+ break;

+ case 3:

+ goto fail;

+ startlevel = 3 - sl0;

+ /*

+ * Things are simpler for AArch32 EL2, with only 4k pages.

+ * There is no separate S2InvalidSL function, but AArch32.S2Walk

+ * begins with walkparms.sl0 in {'1x'}.

+ */

+ if (sl0 >= 2) {

+ goto fail;

+ startlevel = 2 - sl0;

+

+ /* AArch{64,32}.S2InconsistentSL are functionally equivalent. */

+ levels = 3 - startlevel;

+ granulebits = stride + 3;

+

+ s1_min_iasize = levels * stride + granulebits + 1;

+ s1_max_iasize = s1_min_iasize + (stride - 1) + 4;

+

+ if (iasize >= s1_min_iasize && iasize <= s1_max_iasize) {

+ return startlevel;

+ }

+

+ fail:

+ return INT_MIN;

+ int startlevel = check_s2_mmu_setup(cpu, aarch64, tcr, param.ds,

+ inputsize, stride);

+ if (startlevel == INT_MIN) {

+ level = 0;

+uint32_t arm_v7m_mrs_control(CPUARMState *env, uint32_t secure)

+ return arm_v7m_mrs_control(env, 0);

+ frame_sp_p = arm_v7m_get_sp_ptr(env, M_REG_S, mode,

+ lr & R_V7M_EXCRET_SPSEL_MASK);

+ uint32_t *frame_sp_p = arm_v7m_get_sp_ptr(env, return_to_secure,

+ !return_to_handler, spsel);

+ frame_sp_p = arm_v7m_get_sp_ptr(env, true, threadmode, spsel);

+ return arm_v7m_mrs_control(env, env->v7m.secure);

+

+uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode,

+ bool spsel)

+{

+ /*

+ * Return a pointer to the location where we currently store the

+ * stack pointer for the requested security state and thread mode.

+ * This pointer will become invalid if the CPU state is updated

+ * such that the stack pointers are switched around (eg changing

+ * the SPSEL control bit).

+ * Compare the v8M ARM ARM pseudocode LookUpSP_with_security_mode().

+ * Unlike that pseudocode, we require the caller to pass us in the

+ * SPSEL control bit value; this is because we also use this

+ * function in handling of pushing of the callee-saves registers

+ * part of the v8M stack frame (pseudocode PushCalleeStack()),

+ * and in the tailchain codepath the SPSEL bit comes from the exception

+ * return magic LR value from the previous exception. The pseudocode

+ * opencodes the stack-selection in PushCalleeStack(), but we prefer

+ * to make this utility function generic enough to do the job.

+ */

+ bool want_psp = threadmode && spsel;

+

+ if (secure == env->v7m.secure) {

+ if (want_psp == v7m_using_psp(env)) {

+ return &env->regs[13];

+ } else {

+ return &env->v7m.other_sp;

+ }

+ } else {

+ if (want_psp) {

+ return &env->v7m.other_ss_psp;

+ } else {

+ return &env->v7m.other_ss_msp;

+ }

+ }

+}

+static uint64_t pauth_ptr_mask_internal(ARMVAParameters param)

+ return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit);

+}

+

+static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)

+{

+ uint64_t mask = pauth_ptr_mask_internal(param);

+

+ /* Note that bit 55 is used whether or not the regime has 2 ranges. */

+ if (extract64(ptr, 55, 1)) {

+ return ptr | mask;

+ } else {

+ return ptr & ~mask;

+ }

+}

+

+uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data)

+{

+ ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);

+ ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);

+

+ return pauth_ptr_mask_internal(param);

+ .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt) |

+ (1 << CP0C3_M),

+ .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),

+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),

+ .CP0_Config7 = 1 << CP0C7_WII,

+ .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt) |

+ (1 << CP0C3_M),

+ .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M),

+ .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_NFExists),

+ .CP0_Config7 = 1 << CP0C7_WII,

+ .CP0_Config7 = 1 << CP0C7_WII,

+ * check for interrupts that can be taken. For pre-release 6 CPUs,

+ * check for CP0 Config7 'Wait IE ignore' bit.

+ (env->CP0_Config7 & (1 << CP0C7_WII)) ||

+#define CP0C7_WII 31

+ g_assert_not_reached();

+ cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]],

+ cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());

+ g_assert_not_reached();

+ g_assert_not_reached(); \

+ g_assert_not_reached();

+ g_assert_not_reached(); \

+ g_assert_not_reached(); \

+ g_assert_not_reached();

+ g_assert_not_reached(); \

+ g_assert_not_reached(); \

+ g_assert_not_reached();

+ g_assert_not_reached(); \

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ g_assert_not_reached();

+ {

+ /* Jump to immediate */

+ int jal_mask = ctx->hflags & MIPS_HFLAG_M16 ? 0xF8000000

+ : 0xF0000000;

+ btgt = ((ctx->base.pc_next + insn_bytes) & jal_mask)

+ | (uint32_t)offset;

+ break;

+ }

+#include "qapi/visitor.h"

+ ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom),

+ ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz),

+static void register_cpu_props(Object *obj);

+#ifndef CONFIG_USER_ONLY

+static uint8_t satp_mode_from_str(const char *satp_mode_str)

+{

+ if (!strncmp(satp_mode_str, "mbare", 5)) {

+ return VM_1_10_MBARE;

+ }

+

+ if (!strncmp(satp_mode_str, "sv32", 4)) {

+ return VM_1_10_SV32;

+ }

+

+ if (!strncmp(satp_mode_str, "sv39", 4)) {

+ return VM_1_10_SV39;

+ }

+

+ if (!strncmp(satp_mode_str, "sv48", 4)) {

+ return VM_1_10_SV48;

+ }

+

+ if (!strncmp(satp_mode_str, "sv57", 4)) {

+ return VM_1_10_SV57;

+ }

+

+ if (!strncmp(satp_mode_str, "sv64", 4)) {

+ return VM_1_10_SV64;

+ }

+

+ g_assert_not_reached();

+}

+

+uint8_t satp_mode_max_from_map(uint32_t map)

+{

+ /* map here has at least one bit set, so no problem with clz */

+ return 31 - __builtin_clz(map);

+}

+

+const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)

+{

+ if (is_32_bit) {

+ switch (satp_mode) {

+ case VM_1_10_SV32:

+ return "sv32";

+ case VM_1_10_MBARE:

+ return "none";

+ }

+ } else {

+ switch (satp_mode) {

+ case VM_1_10_SV64:

+ return "sv64";

+ case VM_1_10_SV57:

+ return "sv57";

+ case VM_1_10_SV48:

+ return "sv48";

+ case VM_1_10_SV39:

+ return "sv39";

+ case VM_1_10_MBARE:

+ return "none";

+ }

+ }

+

+ g_assert_not_reached();

+}

+

+static void set_satp_mode_max_supported(RISCVCPU *cpu,

+ uint8_t satp_mode)

+{

+ bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;

+ const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;

+

+ for (int i = 0; i <= satp_mode; ++i) {

+ if (valid_vm[i]) {

+ cpu->cfg.satp_mode.supported |= (1 << i);

+ }

+ }

+}

+

+/* Set the satp mode to the max supported */

+static void set_satp_mode_default_map(RISCVCPU *cpu)

+{

+ cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;

+}

+#endif

+

+

+#ifndef CONFIG_USER_ONLY

+ set_satp_mode_max_supported(RISCV_CPU(obj),

+ riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?

+ VM_1_10_SV32 : VM_1_10_SV57);

+#endif

+