diff options
| -rw-r--r-- | MAINTAINERS | 21 | ||||
| -rw-r--r-- | include/qemu/bitops.h | 80 | ||||
| -rw-r--r-- | qemu-char.c | 7 | ||||
| -rw-r--r-- | target-arm/iwmmxt_helper.c | 2 | ||||
| -rw-r--r-- | tcg/optimize.c | 12 | ||||
| -rw-r--r-- | tcg/tci/tcg-target.c | 1 | ||||
| -rw-r--r-- | tci.c | 14 |
7 files changed, 107 insertions, 30 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 5c3c70c89b..ab8166aa4d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -51,7 +51,6 @@ Descriptions of section entries: General Project Administration ------------------------------ M: Anthony Liguori <anthony@codemonkey.ws> -M: Paul Brook <paul@codesourcery.com> Guest CPU cores (TCG): ---------------------- @@ -62,7 +61,6 @@ F: target-alpha/ F: hw/alpha/ ARM -M: Paul Brook <paul@codesourcery.com> M: Peter Maydell <peter.maydell@linaro.org> S: Maintained F: target-arm/ @@ -83,8 +81,7 @@ F: hw/lm32/ F: hw/char/lm32_* M68K -M: Paul Brook <paul@codesourcery.com> -S: Odd Fixes +S: Orphan F: target-m68k/ F: hw/m68k/ @@ -248,7 +245,6 @@ F: hw/*/imx* F: hw/arm/kzm.c Integrator CP -M: Paul Brook <paul@codesourcery.com> M: Peter Maydell <peter.maydell@linaro.org> S: Maintained F: hw/arm/integratorcp.c @@ -274,7 +270,6 @@ S: Maintained F: hw/arm/palm.c Real View -M: Paul Brook <paul@codesourcery.com> M: Peter Maydell <peter.maydell@linaro.org> S: Maintained F: hw/arm/realview* @@ -285,13 +280,11 @@ S: Maintained F: hw/arm/spitz.c Stellaris -M: Paul Brook <paul@codesourcery.com> M: Peter Maydell <peter.maydell@linaro.org> S: Maintained F: hw/*/stellaris* Versatile PB -M: Paul Brook <paul@codesourcery.com> M: Peter Maydell <peter.maydell@linaro.org> S: Maintained F: hw/*/versatile* @@ -327,18 +320,15 @@ F: hw/lm32/milkymist.c M68K Machines ------------- an5206 -M: Paul Brook <paul@codesourcery.com> -S: Maintained +S: Orphan F: hw/m68k/an5206.c dummy_m68k -M: Paul Brook <paul@codesourcery.com> -S: Maintained +S: Orphan F: hw/m68k/dummy_m68k.c mcf5208 -M: Paul Brook <paul@codesourcery.com> -S: Maintained +S: Orphan F: hw/m68k/mcf5208.c MicroBlaze Machines @@ -567,8 +557,7 @@ F: hw/scsi/* T: git git://github.com/bonzini/qemu.git scsi-next LSI53C895A -M: Paul Brook <paul@codesourcery.com> -S: Odd Fixes +S: Orphan F: hw/scsi/lsi53c895a.c SSI diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 06e2e6f0ee..304c90c2b4 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -184,6 +184,86 @@ static inline unsigned long hweight_long(unsigned long w) } /** + * rol8 - rotate an 8-bit value left + * @word: value to rotate + * @shift: bits to roll + */ +static inline uint8_t rol8(uint8_t word, unsigned int shift) +{ + return (word << shift) | (word >> (8 - shift)); +} + +/** + * ror8 - rotate an 8-bit value right + * @word: value to rotate + * @shift: bits to roll + */ +static inline uint8_t ror8(uint8_t word, unsigned int shift) +{ + return (word >> shift) | (word << (8 - shift)); +} + +/** + * rol16 - rotate a 16-bit value left + * @word: value to rotate + * @shift: bits to roll + */ +static inline uint16_t rol16(uint16_t word, unsigned int shift) +{ + return (word << shift) | (word >> (16 - shift)); +} + +/** + * ror16 - rotate a 16-bit value right + * @word: value to rotate + * @shift: bits to roll + */ +static inline uint16_t ror16(uint16_t word, unsigned int shift) +{ + return (word >> shift) | (word << (16 - shift)); +} + +/** + * rol32 - rotate a 32-bit value left + * @word: value to rotate + * @shift: bits to roll + */ +static inline uint32_t rol32(uint32_t word, unsigned int shift) +{ + return (word << shift) | (word >> (32 - shift)); +} + +/** + * ror32 - rotate a 32-bit value right + * @word: value to rotate + * @shift: bits to roll + */ +static inline uint32_t ror32(uint32_t word, unsigned int shift) +{ + return (word >> shift) | (word << (32 - shift)); +} + +/** + * rol64 - rotate a 64-bit value left + * @word: value to rotate + * @shift: bits to roll + */ +static inline uint64_t rol64(uint64_t word, unsigned int shift) +{ + return (word << shift) | (word >> (64 - shift)); +} + +/** + * ror64 - rotate a 64-bit value right + * @word: value to rotate + * @shift: bits to roll + */ +static inline uint64_t ror64(uint64_t word, unsigned int shift) +{ + return (word >> shift) | (word << (64 - shift)); +} + +/** * extract32: * @value: the value to extract the bit field from * @start: the lowest bit in the bit field (numbered from 0) diff --git a/qemu-char.c b/qemu-char.c index f7f5464b67..2ca34cd710 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -3271,7 +3271,12 @@ CharDriverState *qemu_chr_new_from_opts(QemuOpts *opts, backend->kind = CHARDEV_BACKEND_KIND_MUX; backend->mux->chardev = g_strdup(bid); ret = qmp_chardev_add(id, backend, errp); - assert(!error_is_set(errp)); + if (error_is_set(errp)) { + chr = qemu_chr_find(bid); + qemu_chr_delete(chr); + chr = NULL; + goto qapi_out; + } } chr = qemu_chr_find(id); diff --git a/target-arm/iwmmxt_helper.c b/target-arm/iwmmxt_helper.c index 7953b53f7e..e6cfa62da8 100644 --- a/target-arm/iwmmxt_helper.c +++ b/target-arm/iwmmxt_helper.c @@ -577,7 +577,7 @@ uint64_t HELPER(iwmmxt_rorl)(CPUARMState *env, uint64_t x, uint32_t n) uint64_t HELPER(iwmmxt_rorq)(CPUARMState *env, uint64_t x, uint32_t n) { - x = (x >> n) | (x << (64 - n)); + x = ror64(x, n); env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x); return x; } diff --git a/tcg/optimize.c b/tcg/optimize.c index b29bf25b67..89e2d6a3b3 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -238,20 +238,16 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) return (int64_t)x >> (int64_t)y; case INDEX_op_rotr_i32: - x = ((uint32_t)x << (32 - y)) | ((uint32_t)x >> y); - return x; + return ror32(x, y); case INDEX_op_rotr_i64: - x = ((uint64_t)x << (64 - y)) | ((uint64_t)x >> y); - return x; + return ror64(x, y); case INDEX_op_rotl_i32: - x = ((uint32_t)x << y) | ((uint32_t)x >> (32 - y)); - return x; + return rol32(x, y); case INDEX_op_rotl_i64: - x = ((uint64_t)x << y) | ((uint64_t)x >> (64 - y)); - return x; + return rol64(x, y); CASE_OP_32_64(not): return ~x; diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c index 233ab3bf35..4976becbe7 100644 --- a/tcg/tci/tcg-target.c +++ b/tcg/tci/tcg-target.c @@ -670,7 +670,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - /* TODO: Implementation of rotl_i64, rotr_i64 missing in tci.c. */ case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ tcg_out_r(s, args[0]); @@ -688,13 +688,13 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t0 = *tb_ptr++; t1 = tci_read_ri32(&tb_ptr); t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (t1 << t2) | (t1 >> (32 - t2))); + tci_write_reg32(t0, rol32(t1, t2)); break; case INDEX_op_rotr_i32: t0 = *tb_ptr++; t1 = tci_read_ri32(&tb_ptr); t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2))); + tci_write_reg32(t0, ror32(t1, t2)); break; #endif #if TCG_TARGET_HAS_deposit_i32 @@ -952,8 +952,16 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: + t0 = *tb_ptr++; + t1 = tci_read_ri64(&tb_ptr); + t2 = tci_read_ri64(&tb_ptr); + tci_write_reg64(t0, rol64(t1, t2)); + break; case INDEX_op_rotr_i64: - TODO(); + t0 = *tb_ptr++; + t1 = tci_read_ri64(&tb_ptr); + t2 = tci_read_ri64(&tb_ptr); + tci_write_reg64(t0, ror64(t1, t2)); break; #endif #if TCG_TARGET_HAS_deposit_i64 |