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-rw-r--r--cpu-exec.c2
-rw-r--r--target-mips/helper.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/cpu-exec.c b/cpu-exec.c
index 8a585c1066..b6df3bef18 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -561,6 +561,8 @@ int cpu_exec(CPUState *env1)
#elif defined(TARGET_SH4)
/* XXXXX */
#endif
+ /* Don't use the cached interupt_request value,
+ do_interrupt may have updated the EXITTB flag. */
if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
/* ensure that no TB jump will be modified as
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 752ee72750..d3c64bb7e5 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -219,7 +219,6 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
exception = EXCP_TLBS;
else
exception = EXCP_TLBL;
- error_code = 0;
break;
case -4:
/* TLB match but 'D' bit is cleared */
@@ -350,7 +349,6 @@ void do_interrupt (CPUState *env)
cause = 4;
goto set_EPC;
case EXCP_TLBL:
- case EXCP_TLBF:
cause = 2;
if (env->error_code == 1 && !(env->hflags & MIPS_HFLAG_EXL))
offset = 0x000;