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-rw-r--r--darwin-user/main.c4
-rw-r--r--hw/ppc.c4
-rw-r--r--hw/ppc.h4
-rw-r--r--hw/ppc405_uc.c46
-rw-r--r--hw/ppc4xx_devs.c14
-rw-r--r--linux-user/main.c4
-rw-r--r--target-ppc/cpu.h4
-rw-r--r--target-ppc/helper.h4
-rw-r--r--target-ppc/op_helper.c10
9 files changed, 47 insertions, 47 deletions
diff --git a/darwin-user/main.c b/darwin-user/main.c
index d83e1c172e..ade7d4864b 100644
--- a/darwin-user/main.c
+++ b/darwin-user/main.c
@@ -113,12 +113,12 @@ uint32_t cpu_ppc601_load_rtcl (CPUState *env)
}
/* XXX: to be fixed */
-int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
+int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
{
return -1;
}
-int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
+int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
{
return -1;
}
diff --git a/hw/ppc.c b/hw/ppc.c
index c917ae6698..5baeeafb3d 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -1009,7 +1009,7 @@ struct ppc_dcr_t {
int (*write_error)(int dcrn);
};
-int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
+int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
{
ppc_dcrn_t *dcr;
@@ -1029,7 +1029,7 @@ int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
return -1;
}
-int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
+int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
{
ppc_dcrn_t *dcr;
diff --git a/hw/ppc.h b/hw/ppc.h
index 4b481afbc9..bbf3a986b6 100644
--- a/hw/ppc.h
+++ b/hw/ppc.h
@@ -13,8 +13,8 @@ static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
/* Embedded PowerPC DCR management */
-typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
-typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
+typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
+typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
int (*dcr_write_error)(int dcrn));
int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 052f9022f2..bfcb79144b 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -107,10 +107,10 @@ struct ppc4xx_plb_t {
uint32_t besr;
};
-static target_ulong dcr_read_plb (void *opaque, int dcrn)
+static uint32_t dcr_read_plb (void *opaque, int dcrn)
{
ppc4xx_plb_t *plb;
- target_ulong ret;
+ uint32_t ret;
plb = opaque;
switch (dcrn) {
@@ -132,7 +132,7 @@ static target_ulong dcr_read_plb (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_plb_t *plb;
@@ -189,10 +189,10 @@ struct ppc4xx_pob_t {
uint32_t besr[2];
};
-static target_ulong dcr_read_pob (void *opaque, int dcrn)
+static uint32_t dcr_read_pob (void *opaque, int dcrn)
{
ppc4xx_pob_t *pob;
- target_ulong ret;
+ uint32_t ret;
pob = opaque;
switch (dcrn) {
@@ -212,7 +212,7 @@ static target_ulong dcr_read_pob (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_pob_t *pob;
@@ -410,10 +410,10 @@ enum {
EBC0_CFGDATA = 0x013,
};
-static target_ulong dcr_read_ebc (void *opaque, int dcrn)
+static uint32_t dcr_read_ebc (void *opaque, int dcrn)
{
ppc4xx_ebc_t *ebc;
- target_ulong ret;
+ uint32_t ret;
ebc = opaque;
switch (dcrn) {
@@ -494,7 +494,7 @@ static target_ulong dcr_read_ebc (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_ebc_t *ebc;
@@ -627,7 +627,7 @@ struct ppc405_dma_t {
uint32_t pol;
};
-static target_ulong dcr_read_dma (void *opaque, int dcrn)
+static uint32_t dcr_read_dma (void *opaque, int dcrn)
{
ppc405_dma_t *dma;
@@ -636,7 +636,7 @@ static target_ulong dcr_read_dma (void *opaque, int dcrn)
return 0;
}
-static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
{
ppc405_dma_t *dma;
@@ -914,10 +914,10 @@ static void ocm_update_mappings (ppc405_ocm_t *ocm,
}
}
-static target_ulong dcr_read_ocm (void *opaque, int dcrn)
+static uint32_t dcr_read_ocm (void *opaque, int dcrn)
{
ppc405_ocm_t *ocm;
- target_ulong ret;
+ uint32_t ret;
ocm = opaque;
switch (dcrn) {
@@ -941,7 +941,7 @@ static target_ulong dcr_read_ocm (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
{
ppc405_ocm_t *ocm;
uint32_t isarc, dsarc, isacntl, dsacntl;
@@ -1578,10 +1578,10 @@ struct ppc40x_mal_t {
static void ppc40x_mal_reset (void *opaque);
-static target_ulong dcr_read_mal (void *opaque, int dcrn)
+static uint32_t dcr_read_mal (void *opaque, int dcrn)
{
ppc40x_mal_t *mal;
- target_ulong ret;
+ uint32_t ret;
mal = opaque;
switch (dcrn) {
@@ -1650,7 +1650,7 @@ static target_ulong dcr_read_mal (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
{
ppc40x_mal_t *mal;
int idx;
@@ -1951,10 +1951,10 @@ static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
}
-static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
+static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
{
ppc405cr_cpc_t *cpc;
- target_ulong ret;
+ uint32_t ret;
cpc = opaque;
switch (dcrn) {
@@ -1991,7 +1991,7 @@ static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
{
ppc405cr_cpc_t *cpc;
@@ -2353,10 +2353,10 @@ static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
}
-static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
+static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
{
ppc405ep_cpc_t *cpc;
- target_ulong ret;
+ uint32_t ret;
cpc = opaque;
switch (dcrn) {
@@ -2393,7 +2393,7 @@ static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
{
ppc405ep_cpc_t *cpc;
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 7921ebfb4a..37a3948293 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -183,10 +183,10 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level)
ppcuic_trigger_irq(uic);
}
-static target_ulong dcr_read_uic (void *opaque, int dcrn)
+static uint32_t dcr_read_uic (void *opaque, int dcrn)
{
ppcuic_t *uic;
- target_ulong ret;
+ uint32_t ret;
uic = opaque;
dcrn -= uic->dcr_base;
@@ -229,13 +229,13 @@ static target_ulong dcr_read_uic (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
{
ppcuic_t *uic;
uic = opaque;
dcrn -= uic->dcr_base;
- LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
+ LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
@@ -448,10 +448,10 @@ static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
}
}
-static target_ulong dcr_read_sdram (void *opaque, int dcrn)
+static uint32_t dcr_read_sdram (void *opaque, int dcrn)
{
ppc4xx_sdram_t *sdram;
- target_ulong ret;
+ uint32_t ret;
sdram = opaque;
switch (dcrn) {
@@ -516,7 +516,7 @@ static target_ulong dcr_read_sdram (void *opaque, int dcrn)
return ret;
}
-static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_sdram_t *sdram;
diff --git a/linux-user/main.c b/linux-user/main.c
index 445bfc76b6..d8bb8307ef 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1097,12 +1097,12 @@ uint32_t cpu_ppc601_load_rtcl (CPUState *env)
}
/* XXX: to be fixed */
-int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp)
+int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp)
{
return -1;
}
-int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val)
+int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val)
{
return -1;
}
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ac93df115c..d15bba18d4 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -795,8 +795,8 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
}
/* Device control registers */
-int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, target_ulong *valp);
-int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, target_ulong val);
+int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
+int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define cpu_init cpu_ppc_init
#define cpu_exec cpu_ppc_exec
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5cf6cd4501..40d4cedeac 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -359,8 +359,8 @@ DEF_HELPER_2(divo, tl, tl, tl)
DEF_HELPER_2(divs, tl, tl, tl)
DEF_HELPER_2(divso, tl, tl, tl)
-DEF_HELPER_1(load_dcr, tl, tl);
-DEF_HELPER_2(store_dcr, void, tl, tl)
+DEF_HELPER_1(load_dcr, i32, i32);
+DEF_HELPER_2(store_dcr, void, i32, i32)
DEF_HELPER_1(load_dump_spr, void, i32)
DEF_HELPER_1(store_dump_spr, void, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index cb191933ae..cea27f2b4d 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -1828,30 +1828,30 @@ target_ulong helper_602_mfrom (target_ulong arg)
/* Embedded PowerPC specific helpers */
/* XXX: to be improved to check access rights when in user-mode */
-target_ulong helper_load_dcr (target_ulong dcrn)
+uint32_t helper_load_dcr (uint32_t dcrn)
{
- target_ulong val = 0;
+ uint32_t val = 0;
if (unlikely(env->dcr_env == NULL)) {
qemu_log("No DCR environment\n");
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
} else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
- qemu_log("DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
+ qemu_log("DCR read error %d %03x\n", dcrn, dcrn);
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
}
return val;
}
-void helper_store_dcr (target_ulong dcrn, target_ulong val)
+void helper_store_dcr (uint32_t dcrn, uint32_t val)
{
if (unlikely(env->dcr_env == NULL)) {
qemu_log("No DCR environment\n");
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
} else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
- qemu_log("DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
+ qemu_log("DCR write error %d %03x\n", dcrn, dcrn);
helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
}
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-25 18:36:58 +0000