diff options
| -rw-r--r-- | target-mips/translate.c | 8 | ||||
| -rw-r--r-- | target-mips/translate_init.c | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index ff0e590d28..dfea6f6e34 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -9845,6 +9845,14 @@ void cpu_reset (CPUMIPSState *env) env->hflags = MIPS_HFLAG_UM; /* Enable access to the SYNCI_Step register. */ env->CP0_HWREna |= (1 << 1); + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + env->hflags |= MIPS_HFLAG_FPU; + } +#ifdef TARGET_MIPS64 + if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { + env->hflags |= MIPS_HFLAG_F64; + } +#endif #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 6f50555e2d..11bc47c0a3 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -533,14 +533,6 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def) env->fpus[i].fcr0 = def->CP1_fcr0; memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); -#if defined(CONFIG_USER_ONLY) - if (env->CP0_Config1 & (1 << CP0C1_FP)) - env->hflags |= MIPS_HFLAG_FPU; -#ifdef TARGET_MIPS64 - if (env->active_fpu.fcr0 & (1 << FCR0_F64)) - env->hflags |= MIPS_HFLAG_F64; -#endif -#endif } static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |