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-rw-r--r--target-arm/cpu.h10
-rw-r--r--target-arm/helper.c54
-rw-r--r--target-arm/helper.h3
-rw-r--r--target-arm/translate.c41
4 files changed, 1 insertions, 107 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 6c7d3e72e0..a61cb07d4c 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -228,12 +228,6 @@ typedef struct CPUARMState {
/* Internal CPU feature flags. */
uint32_t features;
- /* Coprocessor IO used by peripherals */
- struct {
- ARMReadCPFunc *cp_read;
- ARMWriteCPFunc *cp_write;
- void *opaque;
- } cp[15];
void *nvic;
const struct arm_boot_info *boot_info;
} CPUARMState;
@@ -406,10 +400,6 @@ void armv7m_nvic_set_pending(void *opaque, int irq);
int armv7m_nvic_acknowledge_irq(void *opaque);
void armv7m_nvic_complete_irq(void *opaque, int irq);
-void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
- ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
- void *opaque);
-
/* Interface for defining coprocessor registers.
* Registers are defined in tables of arm_cp_reginfo structs
* which are passed to define_arm_cp_regs().
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 70324234ec..57bb78b7bd 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -386,21 +386,6 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
return 1;
}
-/* These should probably raise undefined insn exceptions. */
-void HELPER(set_cp)(CPUARMState *env, uint32_t insn, uint32_t val)
-{
- int op1 = (insn >> 8) & 0xf;
- cpu_abort(env, "cp%i insn %08x\n", op1, insn);
- return;
-}
-
-uint32_t HELPER(get_cp)(CPUARMState *env, uint32_t insn)
-{
- int op1 = (insn >> 8) & 0xf;
- cpu_abort(env, "cp%i insn %08x\n", op1, insn);
- return 0;
-}
-
void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
{
cpu_abort(env, "cp15 insn %08x\n", insn);
@@ -1137,31 +1122,6 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
return phys_addr;
}
-void HELPER(set_cp)(CPUARMState *env, uint32_t insn, uint32_t val)
-{
- int cp_num = (insn >> 8) & 0xf;
- int cp_info = (insn >> 5) & 7;
- int src = (insn >> 16) & 0xf;
- int operand = insn & 0xf;
-
- if (env->cp[cp_num].cp_write)
- env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
- cp_info, src, operand, val);
-}
-
-uint32_t HELPER(get_cp)(CPUARMState *env, uint32_t insn)
-{
- int cp_num = (insn >> 8) & 0xf;
- int cp_info = (insn >> 5) & 7;
- int dest = (insn >> 16) & 0xf;
- int operand = insn & 0xf;
-
- if (env->cp[cp_num].cp_read)
- return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
- cp_info, dest, operand);
- return 0;
-}
-
/* Return basic MPU access permission bits. */
static uint32_t simple_mpu_ap_bits(uint32_t val)
{
@@ -2125,20 +2085,6 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
}
}
-void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
- ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
- void *opaque)
-{
- if (cpnum < 0 || cpnum > 14) {
- cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
- return;
- }
-
- env->cp[cpnum].cp_read = cp_read;
- env->cp[cpnum].cp_write = cp_write;
- env->cp[cpnum].opaque = opaque;
-}
-
#endif
/* Note that signed overflow is undefined in C. The following routines are
diff --git a/target-arm/helper.h b/target-arm/helper.h
index b6cefed206..bb6b85da72 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -62,9 +62,6 @@ DEF_HELPER_2(v7m_mrs, i32, env, i32)
DEF_HELPER_3(set_cp15, void, env, i32, i32)
DEF_HELPER_2(get_cp15, i32, env, i32)
-DEF_HELPER_3(set_cp, void, env, i32, i32)
-DEF_HELPER_2(get_cp, i32, env, i32)
-
DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
DEF_HELPER_2(get_cp_reg, i32, env, ptr)
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index d7edda758e..75e464d1b1 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2439,39 +2439,6 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
return 1;
}
-/* Disassemble system coprocessor instruction. Return nonzero if
- instruction is not defined. */
-static int disas_cp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
-{
- TCGv tmp, tmp2;
- uint32_t rd = (insn >> 12) & 0xf;
- uint32_t cp = (insn >> 8) & 0xf;
- if (IS_USER(s)) {
- return 1;
- }
-
- if (insn & ARM_CP_RW_BIT) {
- if (!env->cp[cp].cp_read)
- return 1;
- gen_set_pc_im(s->pc);
- tmp = tcg_temp_new_i32();
- tmp2 = tcg_const_i32(insn);
- gen_helper_get_cp(tmp, cpu_env, tmp2);
- tcg_temp_free(tmp2);
- store_reg(s, rd, tmp);
- } else {
- if (!env->cp[cp].cp_write)
- return 1;
- gen_set_pc_im(s->pc);
- tmp = load_reg(s, rd);
- tmp2 = tcg_const_i32(insn);
- gen_helper_set_cp(cpu_env, tmp2, tmp);
- tcg_temp_free(tmp2);
- tcg_temp_free_i32(tmp);
- }
- return 0;
-}
-
static int cp15_user_ok(CPUARMState *env, uint32_t insn)
{
int cpn = (insn >> 16) & 0xf;
@@ -6653,10 +6620,6 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
*/
switch (cpnum) {
case 14:
- /* Coprocessors 7-15 are architecturally reserved by ARM.
- Unfortunately Intel decided to ignore this. */
- if (arm_feature(env, ARM_FEATURE_XSCALE))
- goto board;
if (insn & (1 << 20))
return disas_cp14_read(env, s, insn);
else
@@ -6664,9 +6627,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
case 15:
return disas_cp15_insn (env, s, insn);
default:
- board:
- /* Unknown coprocessor. See if the board has hooked it. */
- return disas_cp_insn (env, s, insn);
+ return 1;
}
}
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-26 12:54:01 +0000