diff options
| -rw-r--r-- | target/mips/cpu.h | 5 | ||||
| -rw-r--r-- | target/mips/mips-defs.h | 4 |
2 files changed, 8 insertions, 1 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 0c2d397e4a..9c45744c5c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1305,6 +1305,11 @@ static inline bool ase_mt_available(CPUMIPSState *env) return env->CP0_Config3 & (1 << CP0C3_MT); } +static inline bool cpu_type_is_64bit(const char *cpu_type) +{ + return cpu_type_supports_isa(cpu_type, CPU_MIPS64); +} + void cpu_set_exception_base(int vp_index, target_ulong address); /* addr.c */ diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index 1630ae20d5..89a9a4dda3 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -13,7 +13,7 @@ */ #define ISA_MIPS1 0x0000000000000001ULL #define ISA_MIPS2 0x0000000000000002ULL -#define ISA_MIPS3 0x0000000000000004ULL +#define ISA_MIPS3 0x0000000000000004ULL /* 64-bit */ #define ISA_MIPS4 0x0000000000000008ULL #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS32 0x0000000000000020ULL @@ -71,6 +71,8 @@ #define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) #define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F | ASE_LMMI) +#define CPU_MIPS64 (ISA_MIPS3) + /* MIPS Technologies "Release 1" */ #define CPU_MIPS32R1 (CPU_MIPS2 | ISA_MIPS32) #define CPU_MIPS64R1 (CPU_MIPS5 | CPU_MIPS32R1 | ISA_MIPS64) |