diff options
28 files changed, 345 insertions, 161 deletions
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index a0a69b98a7..715fca61ae 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -472,12 +472,8 @@ static uint8_t pnv_xive_get_block_id(XiveRouter *xrtr) static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu) { int pir = ppc_cpu_pir(cpu); - PnvChip *chip; - PnvXive *xive; - - chip = pnv_get_chip(PNV9_PIR2CHIP(pir)); - assert(chip); - xive = &PNV9_CHIP(chip)->xive; + XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr; + PnvXive *xive = PNV_XIVE(xptr); if (!pnv_xive_is_cpu_enabled(xive, cpu)) { xive_error(xive, "IC: CPU %x is not enabled", pir); @@ -1816,10 +1812,17 @@ static void pnv_xive_init(Object *obj) static void pnv_xive_realize(DeviceState *dev, Error **errp) { PnvXive *xive = PNV_XIVE(dev); + PnvXiveClass *pxc = PNV_XIVE_GET_CLASS(dev); XiveSource *xsrc = &xive->ipi_source; XiveENDSource *end_xsrc = &xive->end_source; Error *local_err = NULL; + pxc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + assert(xive->chip); /* @@ -1947,10 +1950,12 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); + PnvXiveClass *pxc = PNV_XIVE_CLASS(klass); xdc->dt_xscom = pnv_xive_dt_xscom; dc->desc = "PowerNV XIVE Interrupt Controller"; + device_class_set_parent_realize(dc, pnv_xive_realize, &pxc->parent_realize); dc->realize = pnv_xive_realize; dc->props = pnv_xive_properties; @@ -1971,6 +1976,7 @@ static const TypeInfo pnv_xive_info = { .instance_init = pnv_xive_init, .instance_size = sizeof(PnvXive), .class_init = pnv_xive_class_init, + .class_size = sizeof(PnvXiveClass), .interfaces = (InterfaceInfo[]) { { TYPE_PNV_XSCOM_INTERFACE }, { } diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index 57305c56d7..7663123878 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -286,10 +286,17 @@ static void spapr_xive_instance_init(Object *obj) static void spapr_xive_realize(DeviceState *dev, Error **errp) { SpaprXive *xive = SPAPR_XIVE(dev); + SpaprXiveClass *sxc = SPAPR_XIVE_GET_CLASS(xive); XiveSource *xsrc = &xive->source; XiveENDSource *end_xsrc = &xive->end_source; Error *local_err = NULL; + sxc->parent_realize(dev, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + if (!xive->nr_irqs) { error_setg(errp, "Number of interrupt needs to be greater 0"); return; @@ -594,7 +601,7 @@ static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, Object *obj; SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); - obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(xive), errp); + obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(xive), errp); if (!obj) { return -1; } @@ -760,10 +767,12 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data) XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); SpaprInterruptControllerClass *sicc = SPAPR_INTC_CLASS(klass); XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass); + SpaprXiveClass *sxc = SPAPR_XIVE_CLASS(klass); dc->desc = "sPAPR XIVE Interrupt Controller"; dc->props = spapr_xive_properties; - dc->realize = spapr_xive_realize; + device_class_set_parent_realize(dc, spapr_xive_realize, + &sxc->parent_realize); dc->vmsd = &vmstate_spapr_xive; xrc->get_eas = spapr_xive_get_eas; @@ -794,6 +803,7 @@ static const TypeInfo spapr_xive_info = { .instance_init = spapr_xive_instance_init, .instance_size = sizeof(SpaprXive), .class_init = spapr_xive_class_init, + .class_size = sizeof(SpaprXiveClass), .interfaces = (InterfaceInfo[]) { { TYPE_SPAPR_INTC }, { } diff --git a/hw/intc/spapr_xive_kvm.c b/hw/intc/spapr_xive_kvm.c index 32b2809210..edb7ee0e74 100644 --- a/hw/intc/spapr_xive_kvm.c +++ b/hw/intc/spapr_xive_kvm.c @@ -75,7 +75,7 @@ static void kvm_cpu_disable_all(void) void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp) { - SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive; + SpaprXive *xive = SPAPR_XIVE(tctx->xptr); uint64_t state[2]; int ret; @@ -97,7 +97,7 @@ void kvmppc_xive_cpu_set_state(XiveTCTX *tctx, Error **errp) void kvmppc_xive_cpu_get_state(XiveTCTX *tctx, Error **errp) { - SpaprXive *xive = SPAPR_MACHINE(qdev_get_machine())->xive; + SpaprXive *xive = SPAPR_XIVE(tctx->xptr); uint64_t state[2] = { 0 }; int ret; @@ -152,8 +152,7 @@ void kvmppc_xive_cpu_synchronize_state(XiveTCTX *tctx, Error **errp) void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp) { - MachineState *ms = MACHINE(qdev_get_machine()); - SpaprXive *xive = SPAPR_MACHINE(ms)->xive; + SpaprXive *xive = SPAPR_XIVE(tctx->xptr); unsigned long vcpu_id; int ret; @@ -179,7 +178,7 @@ void kvmppc_xive_cpu_connect(XiveTCTX *tctx, Error **errp) vcpu_id, strerror(errno)); if (errno == ENOSPC) { error_append_hint(&local_err, "Try -smp maxcpus=N with N < %u\n", - ms->smp.max_cpus); + MACHINE(qdev_get_machine())->smp.max_cpus); } error_propagate(errp, local_err); return; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index d4c6e21703..bc8019c4c9 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -654,6 +654,7 @@ static void xive_tctx_realize(DeviceState *dev, Error **errp) Error *local_err = NULL; assert(tctx->cs); + assert(tctx->xptr); cpu = POWERPC_CPU(tctx->cs); env = &cpu->env; @@ -727,6 +728,8 @@ static const VMStateDescription vmstate_xive_tctx = { static Property xive_tctx_properties[] = { DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), + DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, + XivePresenter *), DEFINE_PROP_END_OF_LIST(), }; @@ -752,7 +755,7 @@ static const TypeInfo xive_tctx_info = { .class_init = xive_tctx_class_init, }; -Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) +Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp) { Error *local_err = NULL; Object *obj; @@ -761,6 +764,7 @@ Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp) object_property_add_child(cpu, TYPE_XIVE_TCTX, obj, &error_abort); object_unref(obj); object_property_set_link(obj, cpu, "cpu", &error_abort); + object_property_set_link(obj, OBJECT(xptr), "presenter", &error_abort); object_property_set_bool(obj, true, "realized", &local_err); if (local_err) { goto error; @@ -1378,6 +1382,13 @@ static int xive_router_get_block_id(XiveRouter *xrtr) return xrc->get_block_id(xrtr); } +static void xive_router_realize(DeviceState *dev, Error **errp) +{ + XiveRouter *xrtr = XIVE_ROUTER(dev); + + assert(xrtr->xfb); +} + /* * Encode the HW CAM line in the block group mode format : * @@ -1470,12 +1481,11 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, * * The parameters represent what is sent on the PowerBus */ -static bool xive_presenter_notify(uint8_t format, +static bool xive_presenter_notify(XiveFabric *xfb, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv) { - XiveFabric *xfb = XIVE_FABRIC(qdev_get_machine()); XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xfb); XiveTCTXMatch match = { .tctx = NULL, .ring = 0 }; int count; @@ -1607,7 +1617,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, return; } - found = xive_presenter_notify(format, nvt_blk, nvt_idx, + found = xive_presenter_notify(xrtr->xfb, format, nvt_blk, nvt_idx, xive_get_field32(END_W7_F0_IGNORE, end.w7), priority, xive_get_field32(END_W7_F1_LOG_SERVER_ID, end.w7)); @@ -1714,12 +1724,21 @@ void xive_router_notify(XiveNotifier *xn, uint32_t lisn) xive_get_field64(EAS_END_DATA, eas.w)); } +static Property xive_router_properties[] = { + DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, + TYPE_XIVE_FABRIC, XiveFabric *), + DEFINE_PROP_END_OF_LIST(), +}; + static void xive_router_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); dc->desc = "XIVE Router Engine"; + dc->props = xive_router_properties; + /* Parent is SysBusDeviceClass. No need to call its realize hook */ + dc->realize = xive_router_realize; xnc->notify = xive_router_notify; } @@ -1727,6 +1746,7 @@ static const TypeInfo xive_router_info = { .name = TYPE_XIVE_ROUTER, .parent = TYPE_SYS_BUS_DEVICE, .abstract = true, + .instance_size = sizeof(XiveRouter), .class_size = sizeof(XiveRouterClass), .class_init = xive_router_class_init, .interfaces = (InterfaceInfo[]) { diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index cecf0be59e..10b85bf751 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -244,6 +244,9 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) val = s->b; break; case VIA_REG_A: + qemu_log_mask(LOG_UNIMP, "Read access to register A with handshake"); + /* fall through */ + case VIA_REG_ANH: val = s->a; break; case VIA_REG_DIRB: @@ -297,9 +300,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) val = s->ier | 0x80; break; default: - case VIA_REG_ANH: - val = s->anh; - break; + g_assert_not_reached(); } if (addr != VIA_REG_IFR || val != 0) { @@ -322,6 +323,9 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) mdc->portB_write(s); break; case VIA_REG_A: + qemu_log_mask(LOG_UNIMP, "Write access to register A with handshake"); + /* fall through */ + case VIA_REG_ANH: s->a = (s->a & ~s->dira) | (val & s->dira); mdc->portA_write(s); break; @@ -395,9 +399,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); break; default: - case VIA_REG_ANH: - s->anh = val; - break; + g_assert_not_reached(); } } @@ -439,7 +441,6 @@ const VMStateDescription vmstate_mos6522 = { VMSTATE_UINT8(pcr, MOS6522State), VMSTATE_UINT8(ifr, MOS6522State), VMSTATE_UINT8(ier, MOS6522State), - VMSTATE_UINT8(anh, MOS6522State), VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0, vmstate_mos6522_timer, MOS6522Timer), VMSTATE_END_OF_LIST() @@ -460,7 +461,6 @@ static void mos6522_reset(DeviceState *dev) s->ifr = 0; s->ier = 0; /* s->ier = T1_INT | SR_INT; */ - s->anh = 0; s->timers[0].frequency = s->frequency; s->timers[0].latch = 0xffff; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index f77e7ca84e..e2735bb8dd 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -561,7 +561,7 @@ static void *pnv_dt_create(MachineState *machine) static void pnv_powerdown_notify(Notifier *n, void *opaque) { - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); if (pnv->bmc) { pnv_bmc_powerdown(pnv->bmc); @@ -768,6 +768,18 @@ static void pnv_init(MachineState *machine) exit(1); } + pnv->num_chips = + machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); + /* + * TODO: should we decide on how many chips we can create based + * on #cores and Venice vs. Murano vs. Naples chip type etc..., + */ + if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { + error_report("invalid number of chips: '%d'", pnv->num_chips); + error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); + exit(1); + } + pnv->chips = g_new0(PnvChip *, pnv->num_chips); for (i = 0; i < pnv->num_chips; i++) { char chip_name[32]; @@ -790,12 +802,25 @@ static void pnv_init(MachineState *machine) &error_fatal); object_property_set_int(chip, machine->smp.cores, "nr-cores", &error_fatal); + object_property_set_int(chip, machine->smp.threads, + "nr-threads", &error_fatal); + /* + * The POWER8 machine use the XICS interrupt interface. + * Propagate the XICS fabric to the chip and its controllers. + */ + if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { + object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); + } + if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { + object_property_set_link(chip, OBJECT(pnv), "xive-fabric", + &error_abort); + } object_property_set_bool(chip, true, "realized", &error_fatal); } g_free(chip_typename); /* Create the machine BMC simulator */ - pnv->bmc = pnv_bmc_create(); + pnv->bmc = pnv_bmc_create(pnv->pnor); /* Instantiate ISA bus on chip 0 */ pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); @@ -831,12 +856,12 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, Error **errp) { + Pnv8Chip *chip8 = PNV8_CHIP(chip); Error *local_err = NULL; Object *obj; PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); - obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), - &local_err); + obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -900,7 +925,8 @@ static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, * controller object is initialized afterwards. Hopefully, it's * only used at runtime. */ - obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); + obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), + &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -990,10 +1016,14 @@ static void pnv_chip_power8_instance_init(Object *obj) { Pnv8Chip *chip8 = PNV8_CHIP(obj); + object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, + (Object **)&chip8->xics, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG, + &error_abort); + object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), TYPE_PNV8_PSI, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip8->psi), "xics", - OBJECT(qdev_get_machine()), &error_abort); object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), TYPE_PNV8_LPC, &error_abort, NULL); @@ -1011,7 +1041,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); int i, j; char *name; - XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); name = g_strdup_printf("icp-%x", chip->chip_id); memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); @@ -1027,7 +1056,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { uint32_t pir = pcc->core_pir(chip, core_hwid) + j; - PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); + PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); memory_region_add_subregion(&chip8->icp_mmio, pir << 12, &icp->mmio); @@ -1043,6 +1072,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) Pnv8Psi *psi8 = &chip8->psi; Error *local_err = NULL; + assert(chip8->xics); + /* XSCOM bridge is first */ pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); if (local_err) { @@ -1060,6 +1091,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) /* Processor Service Interface (PSI) Host Bridge */ object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), "bar", &error_fatal); + object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), + ICS_PROP_XICS, &error_abort); object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); @@ -1201,6 +1234,8 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), TYPE_PNV_XIVE, &error_abort, NULL); + object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), + "xive-fabric", &error_abort); object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), TYPE_PNV9_PSI, &error_abort, NULL); @@ -1494,7 +1529,6 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) static void pnv_chip_core_realize(PnvChip *chip, Error **errp) { - MachineState *ms = MACHINE(qdev_get_machine()); Error *error = NULL; PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); const char *typename = pnv_chip_core_typename(chip); @@ -1530,8 +1564,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), &error_abort); chip->cores[i] = pnv_core; - object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", - &error_fatal); + object_property_set_int(OBJECT(pnv_core), chip->nr_threads, + "nr-threads", &error_fatal); object_property_set_int(OBJECT(pnv_core), core_hwid, CPU_CORE_PROP_CORE_ID, &error_fatal); object_property_set_int(OBJECT(pnv_core), @@ -1570,6 +1604,7 @@ static Property pnv_chip_properties[] = { DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), + DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -1682,67 +1717,6 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, return total_count; } -PnvChip *pnv_get_chip(uint32_t chip_id) -{ - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - int i; - - for (i = 0; i < pnv->num_chips; i++) { - PnvChip *chip = pnv->chips[i]; - if (chip->chip_id == chip_id) { - return chip; - } - } - return NULL; -} - -static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); -} - -static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - PnvMachineState *pnv = PNV_MACHINE(obj); - uint32_t num_chips; - Error *local_err = NULL; - - visit_type_uint32(v, name, &num_chips, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - /* - * TODO: should we decide on how many chips we can create based - * on #cores and Venice vs. Murano vs. Naples chip type etc..., - */ - if (!is_power_of_2(num_chips) || num_chips > 4) { - error_setg(errp, "invalid number of chips: '%d'", num_chips); - return; - } - - pnv->num_chips = num_chips; -} - -static void pnv_machine_instance_init(Object *obj) -{ - PnvMachineState *pnv = PNV_MACHINE(obj); - pnv->num_chips = 1; -} - -static void pnv_machine_class_props_init(ObjectClass *oc) -{ - object_class_property_add(oc, "num-chips", "uint32", - pnv_get_num_chips, pnv_set_num_chips, - NULL, NULL, NULL); - object_class_property_set_description(oc, "num-chips", - "Specifies the number of processor chips", - NULL); -} - static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1812,8 +1786,6 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) */ mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; ispc->print_info = pnv_pic_print_info; - - pnv_machine_class_props_init(oc); } #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ @@ -1866,7 +1838,6 @@ static const TypeInfo types[] = { .parent = TYPE_MACHINE, .abstract = true, .instance_size = sizeof(PnvMachineState), - .instance_init = pnv_machine_instance_init, .class_init = pnv_machine_class_init, .class_size = sizeof(PnvMachineClass), .interfaces = (InterfaceInfo[]) { diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c index 07fa1e1c7e..8863354c1c 100644 --- a/hw/ppc/pnv_bmc.c +++ b/hw/ppc/pnv_bmc.c @@ -143,8 +143,8 @@ static uint16_t bytes_to_blocks(uint32_t bytes) static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len, RspBuffer *rsp) { - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - PnvPnor *pnor = pnv->pnor; + PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor", + &error_abort)); uint32_t pnor_size = pnor->size; uint32_t pnor_addr = PNOR_SPI_OFFSET; bool readonly = false; @@ -217,11 +217,13 @@ static const IPMINetfn hiomap_netfn = { * Instantiate the machine BMC. PowerNV uses the QEMU internal * simulator but it could also be external. */ -IPMIBmc *pnv_bmc_create(void) +IPMIBmc *pnv_bmc_create(PnvPnor *pnor) { Object *obj; obj = object_new(TYPE_IPMI_BMC_SIMULATOR); + object_ref(OBJECT(pnor)); + object_property_add_const_link(obj, "pnor", OBJECT(pnor), &error_abort); object_property_set_bool(obj, true, "realized", &error_fatal); /* Install the HIOMAP protocol handlers to access the PNOR */ diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c index bfb1e92b03..b061106d1c 100644 --- a/hw/ppc/pnv_pnor.c +++ b/hw/ppc/pnv_pnor.c @@ -33,6 +33,7 @@ static uint64_t pnv_pnor_read(void *opaque, hwaddr addr, unsigned size) static void pnv_pnor_update(PnvPnor *s, int offset, int size) { int offset_end; + int ret; if (s->blk) { return; @@ -42,8 +43,11 @@ static void pnv_pnor_update(PnvPnor *s, int offset, int size) offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); - blk_pwrite(s->blk, offset, s->storage + offset, - offset_end - offset, 0); + ret = blk_pwrite(s->blk, offset, s->storage + offset, + offset_end - offset, 0); + if (ret < 0) { + error_report("Could not update PNOR: %s", strerror(-ret)); + } } static void pnv_pnor_write(void *opaque, hwaddr addr, uint64_t data, @@ -107,7 +111,7 @@ static void pnv_pnor_realize(DeviceState *dev, Error **errp) } static Property pnv_pnor_properties[] = { - DEFINE_PROP_UINT32("size", PnvPnor, size, 128 << 20), + DEFINE_PROP_INT64("size", PnvPnor, size, 128 << 20), DEFINE_PROP_DRIVE("drive", PnvPnor, blk), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 75e20d9da0..1d8da31738 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -455,7 +455,7 @@ static const MemoryRegionOps pnv_psi_xscom_ops = { } }; -static void pnv_psi_reset(void *dev) +static void pnv_psi_reset(DeviceState *dev) { PnvPsi *psi = PNV_PSI(dev); @@ -464,12 +464,29 @@ static void pnv_psi_reset(void *dev) psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; } +static void pnv_psi_reset_handler(void *dev) +{ + device_reset(DEVICE(dev)); +} + +static void pnv_psi_realize(DeviceState *dev, Error **errp) +{ + PnvPsi *psi = PNV_PSI(dev); + + /* Default BAR for MMIO region */ + pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); + + qemu_register_reset(pnv_psi_reset_handler, dev); +} + static void pnv_psi_power8_instance_init(Object *obj) { Pnv8Psi *psi8 = PNV8_PSI(obj); object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics), TYPE_ICS, &error_abort, NULL); + object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics), + ICS_PROP_XICS, &error_abort); } static const uint8_t irq_to_xivr[] = { @@ -485,19 +502,10 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) { PnvPsi *psi = PNV_PSI(dev); ICSState *ics = &PNV8_PSI(psi)->ics; - Object *obj; Error *err = NULL; unsigned int i; - obj = object_property_get_link(OBJECT(dev), "xics", &err); - if (!obj) { - error_setg(errp, "%s: required link 'xics' not found: %s", - __func__, error_get_pretty(err)); - return; - } - /* Create PSI interrupt control source */ - object_property_set_link(OBJECT(ics), obj, ICS_PROP_XICS, &error_abort); object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err); if (err) { error_propagate(errp, err); @@ -523,9 +531,6 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, "psihb", PNV_PSIHB_SIZE); - /* Default BAR for MMIO region */ - pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); - /* Default sources in XIVR */ for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { uint8_t xivr = irq_to_xivr[i]; @@ -533,7 +538,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) ((uint64_t) i << PSIHB_XIVR_SRC_SH); } - qemu_register_reset(pnv_psi_reset, dev); + pnv_psi_realize(dev, errp); } static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) @@ -816,7 +821,7 @@ static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state) qemu_set_irq(psi->qirqs[irq], state); } -static void pnv_psi_power9_reset(void *dev) +static void pnv_psi_power9_reset(DeviceState *dev) { Pnv9Psi *psi = PNV9_PSI(dev); @@ -868,9 +873,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, "psihb", PNV9_PSIHB_SIZE); - pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); - - qemu_register_reset(pnv_psi_power9_reset, dev); + pnv_psi_realize(dev, errp); } static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) @@ -882,6 +885,7 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller POWER9"; dc->realize = pnv_psi_power9_realize; + dc->reset = pnv_psi_power9_reset; ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; @@ -934,6 +938,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller"; dc->props = pnv_psi_properties; + dc->reset = pnv_psi_reset; } static const TypeInfo pnv_psi_info = { diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 4d95c0f8a8..b782641b23 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -71,12 +71,12 @@ static int bamboo_load_device_tree(hwaddr addr, filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); if (!filename) { - goto out; + return -1; } fdt = load_device_tree(filename, &fdt_size); g_free(filename); if (fdt == NULL) { - goto out; + return -1; } /* Manipulate device tree in memory. */ @@ -117,10 +117,6 @@ static int bamboo_load_device_tree(hwaddr addr, rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); g_free(fdt); return 0; - -out: - - return ret; } /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f11422fc41..30a5fbd3be 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -878,7 +878,7 @@ static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, g_assert(smc->dr_lmb_enabled); ret = spapr_populate_drconf_memory(spapr, fdt); if (ret) { - goto out; + return ret; } } @@ -889,11 +889,8 @@ static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, return offset; } } - ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, - "ibm,architecture-vec-5"); - -out: - return ret; + return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, + "ibm,architecture-vec-5"); } static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) @@ -1597,6 +1594,7 @@ static void spapr_machine_reset(MachineState *machine) void *fdt; int rc; + kvmppc_svm_off(&error_fatal); spapr_caps_apply(spapr); first_ppc_cpu = POWERPC_CPU(first_cpu); @@ -4197,19 +4195,19 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj, kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); } +/* + * This is a XIVE only operation + */ static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match) { SpaprMachineState *spapr = SPAPR_MACHINE(xfb); - XivePresenter *xptr = XIVE_PRESENTER(spapr->xive); + XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); int count; - /* This is a XIVE only operation */ - assert(spapr->active_intc == SPAPR_INTC(spapr->xive)); - count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, priority, logic_serv, match); if (count < 0) { diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 373505d28b..1f630f296b 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -332,6 +332,8 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) * priority */ qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); + object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric", + &error_abort); qdev_init_nofail(dev); spapr->xive = SPAPR_XIVE(dev); diff --git a/include/hw/misc/mos6522.h b/include/hw/misc/mos6522.h index 493c907537..97384c6e02 100644 --- a/include/hw/misc/mos6522.h +++ b/include/hw/misc/mos6522.h @@ -115,7 +115,6 @@ typedef struct MOS6522State { uint8_t pcr; uint8_t ifr; uint8_t ier; - uint8_t anh; MOS6522Timer timers[2]; uint64_t frequency; diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index f78fd0dd96..d65dd32036 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -48,6 +48,7 @@ typedef struct PnvChip { uint64_t ram_size; uint32_t nr_cores; + uint32_t nr_threads; uint64_t cores_mask; PnvCore **cores; @@ -72,6 +73,8 @@ typedef struct Pnv8Chip { Pnv8Psi psi; PnvOCC occ; PnvHomer homer; + + XICSFabric *xics; } Pnv8Chip; #define TYPE_PNV9_CHIP "pnv9-chip" @@ -216,8 +219,6 @@ struct PnvMachineState { PnvPnor *pnor; }; -PnvChip *pnv_get_chip(uint32_t chip_id); - #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL @@ -226,7 +227,7 @@ PnvChip *pnv_get_chip(uint32_t chip_id); */ void pnv_dt_bmc_sensors(IPMIBmc *bmc, void *fdt); void pnv_bmc_powerdown(IPMIBmc *bmc); -IPMIBmc *pnv_bmc_create(void); +IPMIBmc *pnv_bmc_create(PnvPnor *pnor); /* * POWER8 MMIO base addresses diff --git a/include/hw/ppc/pnv_pnor.h b/include/hw/ppc/pnv_pnor.h index c3dd28643c..4f96abdfb4 100644 --- a/include/hw/ppc/pnv_pnor.h +++ b/include/hw/ppc/pnv_pnor.h @@ -23,7 +23,7 @@ typedef struct PnvPnor { BlockBackend *blk; uint8_t *storage; - uint32_t size; + int64_t size; MemoryRegion mmio; } PnvPnor; diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h index f4c7caad40..76cf16f644 100644 --- a/include/hw/ppc/pnv_xive.h +++ b/include/hw/ppc/pnv_xive.h @@ -16,6 +16,10 @@ struct PnvChip; #define TYPE_PNV_XIVE "pnv-xive" #define PNV_XIVE(obj) OBJECT_CHECK(PnvXive, (obj), TYPE_PNV_XIVE) +#define PNV_XIVE_CLASS(klass) \ + OBJECT_CLASS_CHECK(PnvXiveClass, (klass), TYPE_PNV_XIVE) +#define PNV_XIVE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PnvXiveClass, (obj), TYPE_PNV_XIVE) #define XIVE_BLOCK_MAX 16 @@ -85,6 +89,12 @@ typedef struct PnvXive { uint64_t edt[XIVE_TABLE_EDT_MAX]; } PnvXive; +typedef struct PnvXiveClass { + XiveRouterClass parent_class; + + DeviceRealize parent_realize; +} PnvXiveClass; + void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon); #endif /* PPC_PNV_XIVE_H */ diff --git a/include/hw/ppc/spapr_xive.h b/include/hw/ppc/spapr_xive.h index 3a103c224d..93d09d68de 100644 --- a/include/hw/ppc/spapr_xive.h +++ b/include/hw/ppc/spapr_xive.h @@ -15,6 +15,10 @@ #define TYPE_SPAPR_XIVE "spapr-xive" #define SPAPR_XIVE(obj) OBJECT_CHECK(SpaprXive, (obj), TYPE_SPAPR_XIVE) +#define SPAPR_XIVE_CLASS(klass) \ + OBJECT_CLASS_CHECK(SpaprXiveClass, (klass), TYPE_SPAPR_XIVE) +#define SPAPR_XIVE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(SpaprXiveClass, (obj), TYPE_SPAPR_XIVE) typedef struct SpaprXive { XiveRouter parent; @@ -47,6 +51,12 @@ typedef struct SpaprXive { VMChangeStateEntry *change; } SpaprXive; +typedef struct SpaprXiveClass { + XiveRouterClass parent; + + DeviceRealize parent_realize; +} SpaprXiveClass; + /* * The sPAPR machine has a unique XIVE IC device. Assign a fixed value * to the controller block id value. It can nevertheless be changed diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 1b7b89098f..705cf48176 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -311,6 +311,8 @@ void xive_source_set_irq(void *opaque, int srcno, int val); #define XIVE_TM_RING_COUNT 4 #define XIVE_TM_RING_SIZE 0x10 +typedef struct XivePresenter XivePresenter; + typedef struct XiveTCTX { DeviceState parent_obj; @@ -319,14 +321,19 @@ typedef struct XiveTCTX { qemu_irq os_output; uint8_t regs[XIVE_TM_RING_COUNT * XIVE_TM_RING_SIZE]; + + XivePresenter *xptr; } XiveTCTX; /* * XIVE Router */ +typedef struct XiveFabric XiveFabric; typedef struct XiveRouter { SysBusDevice parent; + + XiveFabric *xfb; } XiveRouter; #define TYPE_XIVE_ROUTER "xive-router" @@ -375,8 +382,6 @@ typedef struct XiveTCTXMatch { uint8_t ring; } XiveTCTXMatch; -typedef struct XivePresenter XivePresenter; - #define TYPE_XIVE_PRESENTER "xive-presenter" #define XIVE_PRESENTER(obj) \ INTERFACE_CHECK(XivePresenter, (obj), TYPE_XIVE_PRESENTER) @@ -402,8 +407,6 @@ int xive_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, * XIVE Fabric (Interface between Interrupt Controller and Machine) */ -typedef struct XiveFabric XiveFabric; - #define TYPE_XIVE_FABRIC "xive-fabric" #define XIVE_FABRIC(obj) \ INTERFACE_CHECK(XiveFabric, (obj), TYPE_XIVE_FABRIC) @@ -466,7 +469,7 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, unsigned size); void xive_tctx_pic_print_info(XiveTCTX *tctx, Monitor *mon); -Object *xive_tctx_create(Object *cpu, XiveRouter *xrtr, Error **errp); +Object *xive_tctx_create(Object *cpu, XivePresenter *xptr, Error **errp); void xive_tctx_reset(XiveTCTX *tctx); void xive_tctx_destroy(XiveTCTX *tctx); void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb); diff --git a/include/standard-headers/asm-x86/bootparam.h b/include/standard-headers/asm-x86/bootparam.h index a6f7cf535e..072e2ed546 100644 --- a/include/standard-headers/asm-x86/bootparam.h +++ b/include/standard-headers/asm-x86/bootparam.h @@ -2,7 +2,7 @@ #ifndef _ASM_X86_BOOTPARAM_H #define _ASM_X86_BOOTPARAM_H -/* setup_data types */ +/* setup_data/setup_indirect types */ #define SETUP_NONE 0 #define SETUP_E820_EXT 1 #define SETUP_DTB 2 @@ -11,6 +11,11 @@ #define SETUP_APPLE_PROPERTIES 5 #define SETUP_JAILHOUSE 6 +#define SETUP_INDIRECT (1<<31) + +/* SETUP_INDIRECT | max(SETUP_*) */ +#define SETUP_TYPE_MAX (SETUP_INDIRECT | SETUP_JAILHOUSE) + /* ram_size flags */ #define RAMDISK_IMAGE_START_MASK 0x07FF #define RAMDISK_PROMPT_FLAG 0x8000 diff --git a/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h b/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h index d019872608..a5a1c8234e 100644 --- a/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h +++ b/include/standard-headers/drivers/infiniband/hw/vmw_pvrdma/pvrdma_dev_api.h @@ -58,7 +58,8 @@ #define PVRDMA_ROCEV1_VERSION 17 #define PVRDMA_ROCEV2_VERSION 18 #define PVRDMA_PPN64_VERSION 19 -#define PVRDMA_VERSION PVRDMA_PPN64_VERSION +#define PVRDMA_QPHANDLE_VERSION 20 +#define PVRDMA_VERSION PVRDMA_QPHANDLE_VERSION #define PVRDMA_BOARD_ID 1 #define PVRDMA_REV_ID 1 @@ -581,6 +582,17 @@ struct pvrdma_cmd_create_qp_resp { uint32_t max_inline_data; }; +struct pvrdma_cmd_create_qp_resp_v2 { + struct pvrdma_cmd_resp_hdr hdr; + uint32_t qpn; + uint32_t qp_handle; + uint32_t max_send_wr; + uint32_t max_recv_wr; + uint32_t max_send_sge; + uint32_t max_recv_sge; + uint32_t max_inline_data; +}; + struct pvrdma_cmd_modify_qp { struct pvrdma_cmd_hdr hdr; uint32_t qp_handle; @@ -663,6 +675,7 @@ union pvrdma_cmd_resp { struct pvrdma_cmd_create_cq_resp create_cq_resp; struct pvrdma_cmd_resize_cq_resp resize_cq_resp; struct pvrdma_cmd_create_qp_resp create_qp_resp; + struct pvrdma_cmd_create_qp_resp_v2 create_qp_resp_v2; struct pvrdma_cmd_query_qp_resp query_qp_resp; struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp; struct pvrdma_cmd_create_srq_resp create_srq_resp; diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h index a308c91b4f..46d279f515 100644 --- a/include/standard-headers/drm/drm_fourcc.h +++ b/include/standard-headers/drm/drm_fourcc.h @@ -68,7 +68,7 @@ extern "C" { #define fourcc_code(a, b, c, d) ((uint32_t)(a) | ((uint32_t)(b) << 8) | \ ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24)) -#define DRM_FORMAT_BIG_ENDIAN (1<<31) /* format is big endian instead of little endian */ +#define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */ /* Reserve 0 for the invalid format specifier */ #define DRM_FORMAT_INVALID 0 @@ -647,7 +647,21 @@ extern "C" { * Further information on the use of AFBC modifiers can be found in * Documentation/gpu/afbc.rst */ -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, __afbc_mode) + +/* + * The top 4 bits (out of the 56 bits alloted for specifying vendor specific + * modifiers) denote the category for modifiers. Currently we have only two + * categories of modifiers ie AFBC and MISC. We can have a maximum of sixteen + * different categories. + */ +#define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \ + fourcc_mod_code(ARM, ((uint64_t)(__type) << 52) | ((__val) & 0x000fffffffffffffULL)) + +#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00 +#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01 + +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) /* * AFBC superblock size @@ -742,6 +756,16 @@ extern "C" { #define AFBC_FORMAT_MOD_BCH (1ULL << 11) /* + * Arm 16x16 Block U-Interleaved modifier + * + * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image + * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels + * in the block are reordered. + */ +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \ + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL) + +/* * Allwinner tiled modifier * * This tiling mode is implemented by the VPU found on all Allwinner platforms, diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h index eb08cb8598..b484c25289 100644 --- a/include/standard-headers/linux/input-event-codes.h +++ b/include/standard-headers/linux/input-event-codes.h @@ -649,6 +649,83 @@ */ #define KEY_DATA 0x277 #define KEY_ONSCREEN_KEYBOARD 0x278 +/* Electronic privacy screen control */ +#define KEY_PRIVACY_SCREEN_TOGGLE 0x279 + +/* + * Some keyboards have keys which do not have a defined meaning, these keys + * are intended to be programmed / bound to macros by the user. For most + * keyboards with these macro-keys the key-sequence to inject, or action to + * take, is all handled by software on the host side. So from the kernel's + * point of view these are just normal keys. + * + * The KEY_MACRO# codes below are intended for such keys, which may be labeled + * e.g. G1-G18, or S1 - S30. The KEY_MACRO# codes MUST NOT be used for keys + * where the marking on the key does indicate a defined meaning / purpose. + * + * The KEY_MACRO# codes MUST also NOT be used as fallback for when no existing + * KEY_FOO define matches the marking / purpose. In this case a new KEY_FOO + * define MUST be added. + */ +#define KEY_MACRO1 0x290 +#define KEY_MACRO2 0x291 +#define KEY_MACRO3 0x292 +#define KEY_MACRO4 0x293 +#define KEY_MACRO5 0x294 +#define KEY_MACRO6 0x295 +#define KEY_MACRO7 0x296 +#define KEY_MACRO8 0x297 +#define KEY_MACRO9 0x298 +#define KEY_MACRO10 0x299 +#define KEY_MACRO11 0x29a +#define KEY_MACRO12 0x29b +#define KEY_MACRO13 0x29c +#define KEY_MACRO14 0x29d +#define KEY_MACRO15 0x29e +#define KEY_MACRO16 0x29f +#define KEY_MACRO17 0x2a0 +#define KEY_MACRO18 0x2a1 +#define KEY_MACRO19 0x2a2 +#define KEY_MACRO20 0x2a3 +#define KEY_MACRO21 0x2a4 +#define KEY_MACRO22 0x2a5 +#define KEY_MACRO23 0x2a6 +#define KEY_MACRO24 0x2a7 +#define KEY_MACRO25 0x2a8 +#define KEY_MACRO26 0x2a9 +#define KEY_MACRO27 0x2aa +#define KEY_MACRO28 0x2ab +#define KEY_MACRO29 0x2ac +#define KEY_MACRO30 0x2ad + +/* + * Some keyboards with the macro-keys described above have some extra keys + * for controlling the host-side software responsible for the macro handling: + * -A macro recording start/stop key. Note that not all keyboards which emit + * KEY_MACRO_RECORD_START will also emit KEY_MACRO_RECORD_STOP if + * KEY_MACRO_RECORD_STOP is not advertised, then KEY_MACRO_RECORD_START + * should be interpreted as a recording start/stop toggle; + * -Keys for switching between different macro (pre)sets, either a key for + * cycling through the configured presets or keys to directly select a preset. + */ +#define KEY_MACRO_RECORD_START 0x2b0 +#define KEY_MACRO_RECORD_STOP 0x2b1 +#define KEY_MACRO_PRESET_CYCLE 0x2b2 +#define KEY_MACRO_PRESET1 0x2b3 +#define KEY_MACRO_PRESET2 0x2b4 +#define KEY_MACRO_PRESET3 0x2b5 + +/* + * Some keyboards have a buildin LCD panel where the contents are controlled + * by the host. Often these have a number of keys directly below the LCD + * intended for controlling a menu shown on the LCD. These keys often don't + * have any labeling so we just name them KEY_KBD_LCD_MENU# + */ +#define KEY_KBD_LCD_MENU1 0x2b8 +#define KEY_KBD_LCD_MENU2 0x2b9 +#define KEY_KBD_LCD_MENU3 0x2ba +#define KEY_KBD_LCD_MENU4 0x2bb +#define KEY_KBD_LCD_MENU5 0x2bc #define BTN_TRIGGER_HAPPY 0x2c0 #define BTN_TRIGGER_HAPPY1 0x2c0 diff --git a/include/standard-headers/linux/pci_regs.h b/include/standard-headers/linux/pci_regs.h index 29d6e93fd1..acb7d2bdb4 100644 --- a/include/standard-headers/linux/pci_regs.h +++ b/include/standard-headers/linux/pci_regs.h @@ -34,6 +34,7 @@ * of which the first 64 bytes are standardized as follows: */ #define PCI_STD_HEADER_SIZEOF 64 +#define PCI_STD_NUM_BARS 6 /* Number of standard BARs */ #define PCI_VENDOR_ID 0x00 /* 16 bits */ #define PCI_DEVICE_ID 0x02 /* 16 bits */ #define PCI_COMMAND 0x04 /* 16 bits */ @@ -673,6 +674,8 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ +#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */ diff --git a/include/standard-headers/rdma/vmw_pvrdma-abi.h b/include/standard-headers/rdma/vmw_pvrdma-abi.h index 336a8d596f..0989426a3f 100644 --- a/include/standard-headers/rdma/vmw_pvrdma-abi.h +++ b/include/standard-headers/rdma/vmw_pvrdma-abi.h @@ -179,6 +179,11 @@ struct pvrdma_create_qp { uint64_t __attribute__((aligned(8))) qp_addr; }; +struct pvrdma_create_qp_resp { + uint32_t qpn; + uint32_t qp_handle; +}; + /* PVRDMA masked atomic compare and swap */ struct pvrdma_ex_cmp_swap { uint64_t __attribute__((aligned(8))) swap_val; diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 3b27a1ae85..9d647fad76 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1348,6 +1348,7 @@ struct kvm_s390_ucas_mapping { #define KVM_PPC_GET_CPU_CHAR _IOR(KVMIO, 0xb1, struct kvm_ppc_cpu_char) /* Available with KVM_CAP_PMU_EVENT_FILTER */ #define KVM_SET_PMU_EVENT_FILTER _IOW(KVMIO, 0xb2, struct kvm_pmu_event_filter) +#define KVM_PPC_SVM_OFF _IO(KVMIO, 0xb3) /* ioctl for vm fd */ #define KVM_CREATE_DEVICE _IOWR(KVMIO, 0xe0, struct kvm_create_device) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 50b004d00d..5752ed4a4d 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -112,6 +112,8 @@ static uint64_t ppc_excp_vector_offset(CPUState *cs, int ail) uint64_t offset = 0; switch (ail) { + case AIL_NONE: + break; case AIL_0001_8000: offset = 0x18000; break; diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index d1c334f0e3..b5799e62b4 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1325,12 +1325,6 @@ int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) return 0; } -#if defined(TARGET_PPC64) -#define PPC_INPUT_INT PPC970_INPUT_INT -#else -#define PPC_INPUT_INT PPC6xx_INPUT_INT -#endif - void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) { return; @@ -2900,3 +2894,21 @@ void kvmppc_set_reg_tb_offset(PowerPCCPU *cpu, int64_t tb_offset) kvm_set_one_reg(cs, KVM_REG_PPC_TB_OFFSET, &tb_offset); } } + +/* + * Don't set error if KVM_PPC_SVM_OFF ioctl is invoked on kernels + * that don't support this ioctl. + */ +void kvmppc_svm_off(Error **errp) +{ + int rc; + + if (!kvm_enabled()) { + return; + } + + rc = kvm_vm_ioctl(KVM_STATE(current_machine->accelerator), KVM_PPC_SVM_OFF); + if (rc && rc != -ENOTTY) { + error_setg_errno(errp, -rc, "KVM_PPC_SVM_OFF ioctl failed"); + } +} diff --git a/target/ppc/kvm_ppc.h b/target/ppc/kvm_ppc.h index f22daabf51..b713097bfb 100644 --- a/target/ppc/kvm_ppc.h +++ b/target/ppc/kvm_ppc.h @@ -37,6 +37,7 @@ int kvmppc_booke_watchdog_enable(PowerPCCPU *cpu); target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, bool radix, bool gtse, uint64_t proc_tbl); +void kvmppc_svm_off(Error **errp); #ifndef CONFIG_USER_ONLY bool kvmppc_spapr_use_multitce(void); int kvmppc_spapr_enable_inkernel_multitce(void); @@ -201,6 +202,11 @@ static inline target_ulong kvmppc_configure_v3_mmu(PowerPCCPU *cpu, return 0; } +static inline void kvmppc_svm_off(Error **errp) +{ + return; +} + static inline void kvmppc_set_reg_ppc_online(PowerPCCPU *cpu, unsigned int online) { |