diff options
| -rw-r--r-- | Makefile.target | 5 | ||||
| -rwxr-xr-x | configure | 8 | ||||
| -rw-r--r-- | cpu-exec.c | 17 | ||||
| -rw-r--r-- | dyngen-exec.h | 11 | ||||
| -rw-r--r-- | dyngen.c | 57 | ||||
| -rw-r--r-- | dyngen.h | 8 | ||||
| -rw-r--r-- | exec.h | 12 | ||||
| -rw-r--r-- | m68k.ld | 177 |
8 files changed, 293 insertions, 2 deletions
diff --git a/Makefile.target b/Makefile.target index db72eeb080..27c79e8ca7 100644 --- a/Makefile.target +++ b/Makefile.target @@ -79,6 +79,11 @@ OP_CFLAGS=$(CFLAGS) -mno-sched-prolog LDFLAGS+=-Wl,-T,$(SRC_PATH)/arm.ld endif +ifeq ($(ARCH),m68k) +OP_CFLAGS=$(CFLAGS) -fomit-frame-pointer +LDFLAGS+=-Wl,-T,m68k.ld +endif + ifeq ($(HAVE_GCC3_OPTIONS),yes) # very important to generate a return at the end of every operation OP_CFLAGS+=-fno-reorder-blocks -fno-optimize-sibling-calls @@ -56,6 +56,9 @@ case "$cpu" in ia64) cpu="ia64" ;; + m68k) + cpu="m68k" + ;; *) cpu="unknown" ;; @@ -163,7 +166,7 @@ fi else # if cross compiling, cannot launch a program, so make a static guess -if test "$cpu" = "powerpc" -o "$cpu" = "mips" -o "$cpu" = "s390" -o "$cpu" = "sparc" -o "$cpu" = "sparc64"; then +if test "$cpu" = "powerpc" -o "$cpu" = "mips" -o "$cpu" = "s390" -o "$cpu" = "sparc" -o "$cpu" = "sparc64" -o "$cpu" = "m68k"; then bigendian="yes" fi @@ -265,6 +268,9 @@ elif test "$cpu" = "sparc64" ; then elif test "$cpu" = "ia64" ; then echo "ARCH=ia64" >> $config_mak echo "#define HOST_IA64 1" >> $config_h +elif test "$cpu" = "m68k" ; then + echo "ARCH=m68k" >> config.mak + echo "#define HOST_M68K 1" >> $TMPH else echo "Unsupported CPU" exit 1 diff --git a/cpu-exec.c b/cpu-exec.c index ecab6ff11d..fe165dffdd 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -642,6 +642,23 @@ int cpu_signal_handler(int host_signum, struct siginfo *info, &uc->uc_sigmask); } +#elif defined(__mc68000) + +int cpu_signal_handler(int host_signum, struct siginfo *info, + void *puc) +{ + struct ucontext *uc = puc; + unsigned long pc; + int is_write; + + pc = uc->uc_mcontext.gregs[16]; + /* XXX: compute is_write */ + is_write = 0; + return handle_cpu_signal(pc, (unsigned long)info->si_addr, + is_write, + &uc->uc_sigmask); +} + #else #error host CPU specific signal handler needed diff --git a/dyngen-exec.h b/dyngen-exec.h index 46f4042f68..980e70ca99 100644 --- a/dyngen-exec.h +++ b/dyngen-exec.h @@ -109,6 +109,13 @@ extern int printf(const char *, ...); #define AREG5 "$13" #define AREG6 "$14" #endif +#ifdef __mc68000 +#define AREG0 "%a5" +#define AREG1 "%a4" +#define AREG2 "%d7" +#define AREG3 "%d6" +#define AREG4 "%d5" +#endif #ifdef __ia64__ #define AREG0 "r27" #define AREG1 "r24" @@ -178,4 +185,6 @@ extern int __op_jmp0, __op_jmp1; #ifdef __arm__ #define EXIT_TB() asm volatile ("b exec_loop") #endif - +#ifdef __mc68000 +#define EXIT_TB() asm volatile ("rts") +#endif @@ -86,6 +86,13 @@ #define elf_check_arch(x) ((x) == EM_ARM) #define ELF_USES_RELOC +#elif defined(HOST_M68K) + +#define ELF_CLASS ELFCLASS32 +#define ELF_ARCH EM_68K +#define elf_check_arch(x) ((x) == EM_68K) +#define ELF_USES_RELOCA + #else #error unsupported CPU - please update the code #endif @@ -575,6 +582,21 @@ void gen_code(const char *name, host_ulong offset, host_ulong size, relocs, nb_relocs); break; #endif + case EM_68K: + { + uint8_t *p; + p = (void *)(p_end - 2); + if (p == p_start) + error("empty code for %s", name); + // remove NOP's, probably added for alignment + while ((get16((uint16_t *)p) == 0x4e71) && + (p>p_start)) + p -= 2; + if (get16((uint16_t *)p) != 0x4e75) + error("rts expected at the end of %s", name); + copy_size = p - p_start; + } + break; default: error("unknown ELF architecture"); } @@ -1062,6 +1084,41 @@ void gen_code(const char *name, host_ulong offset, host_ulong size, } } } +#elif defined(HOST_M68K) + { + char name[256]; + int type; + int addend; + Elf32_Sym *sym; + for(i = 0, rel = relocs;i < nb_relocs; i++, rel++) { + if (rel->r_offset >= start_offset && + rel->r_offset < start_offset + copy_size) { + sym = &(symtab[ELFW(R_SYM)(rel->r_info)]); + sym_name = strtab + symtab[ELFW(R_SYM)(rel->r_info)].st_name; + if (strstart(sym_name, "__op_param", &p)) { + snprintf(name, sizeof(name), "param%s", p); + } else { + snprintf(name, sizeof(name), "(long)(&%s)", sym_name); + } + type = ELF32_R_TYPE(rel->r_info); + addend = get32((uint32_t *)(text + rel->r_offset)) + rel->r_addend; + switch(type) { + case R_68K_32: + fprintf(outfile, " /* R_68K_32 RELOC, offset %x */\n", rel->r_offset) ; + fprintf(outfile, " *(uint32_t *)(gen_code_ptr + %d) = %s + %#x;\n", + rel->r_offset - start_offset, name, addend ); + break; + case R_68K_PC32: + fprintf(outfile, " /* R_68K_PC32 RELOC, offset %x */\n", rel->r_offset); + fprintf(outfile, " *(uint32_t *)(gen_code_ptr + %d) = %s - (long)(gen_code_ptr + %#x) + %#x;\n", + rel->r_offset - start_offset, name, rel->r_offset - start_offset, /*sym->st_value+*/ addend); + break; + default: + error("unsupported m68k relocation (%d)", type); + } + } + } + } #else #error unsupported CPU #endif @@ -94,6 +94,14 @@ static inline void flush_icache_range(unsigned long start, unsigned long stop) } #endif +#ifdef __mc68000 +#include <asm/cachectl.h> +static inline void flush_icache_range(unsigned long start, unsigned long stop) +{ + cacheflush(start,FLUSH_SCOPE_LINE,FLUSH_CACHE_BOTH,stop-start+16); +} +#endif + #ifdef __alpha__ register int gp asm("$29"); @@ -348,6 +348,18 @@ static inline int testandset (int *spinlock) } #endif +#ifdef __mc68000 +static inline int testandset (int *p) +{ + char ret; + __asm__ __volatile__("tas %1; sne %0" + : "=r" (ret) + : "m" (p) + : "cc","memory"); + return ret == 0; +} +#endif + typedef int spinlock_t; #define SPIN_LOCK_UNLOCKED 0 diff --git a/m68k.ld b/m68k.ld new file mode 100644 index 0000000000..28da902fd5 --- /dev/null +++ b/m68k.ld @@ -0,0 +1,177 @@ +/* Script for -z combreloc: combine and sort reloc sections */ +OUTPUT_FORMAT("elf32-m68k", "elf32-m68k", + "elf32-m68k") +OUTPUT_ARCH(m68k) +ENTRY(_start) +SEARCH_DIR("/usr/local/m68k-linux/lib"); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = 0x60000000 + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.dyn : + { + *(.rel.init) + *(.rel.text .rel.text.* .rel.gnu.linkonce.t.*) + *(.rel.fini) + *(.rel.rodata .rel.rodata.* .rel.gnu.linkonce.r.*) + *(.rel.data .rel.data.* .rel.gnu.linkonce.d.*) + *(.rel.tdata .rel.tdata.* .rel.gnu.linkonce.td.*) + *(.rel.tbss .rel.tbss.* .rel.gnu.linkonce.tb.*) + *(.rel.ctors) + *(.rel.dtors) + *(.rel.got) + *(.rel.bss .rel.bss.* .rel.gnu.linkonce.b.*) + } + .rela.dyn : + { + *(.rela.init) + *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) + *(.rela.fini) + *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) + *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) + *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) + *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) + *(.rela.ctors) + *(.rela.dtors) + *(.rela.got) + *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*) + } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : + { + KEEP (*(.init)) + } =0x4e754e75 + .plt : { *(.plt) } + .text : + { + *(.text .stub .text.* .gnu.linkonce.t.*) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } =0x4e754e75 + .fini : + { + KEEP (*(.fini)) + } =0x4e754e75 + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + .rodata : { *(.rodata .rodata.* .gnu.linkonce.r.*) } + .rodata1 : { *(.rodata1) } + .eh_frame_hdr : { *(.eh_frame_hdr) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(0x2000) + (. & (0x2000 - 1)); + /* Ensure the __preinit_array_start label is properly aligned. We + could instead move the label definition inside the section, but + the linker would then create the section even if it turns out to + be empty, which isn't pretty. */ + . = ALIGN(32 / 8); + PROVIDE (__preinit_array_start = .); + .preinit_array : { *(.preinit_array) } + PROVIDE (__preinit_array_end = .); + PROVIDE (__init_array_start = .); + .init_array : { *(.init_array) } + PROVIDE (__init_array_end = .); + PROVIDE (__fini_array_start = .); + .fini_array : { *(.fini_array) } + PROVIDE (__fini_array_end = .); + .data : + { + *(.data .data.* .gnu.linkonce.d.*) + SORT(CONSTRUCTORS) + } + .data1 : { *(.data1) } + .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } + .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } + .eh_frame : { KEEP (*(.eh_frame)) } + .gcc_except_table : { *(.gcc_except_table) } + .dynamic : { *(.dynamic) } + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + /* We don't want to include the .ctor section from + from the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } + .jcr : { KEEP (*(.jcr)) } + .got : { *(.got.plt) *(.got) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .bss : + { + *(.dynbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ + . = ALIGN(32 / 8); + } + . = ALIGN(32 / 8); + _end = .; + PROVIDE (end = .); + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} |