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-rw-r--r--target-mips/mips-defs.h37
-rw-r--r--target-mips/translate.c3
-rw-r--r--target-mips/translate_init.c61
3 files changed, 61 insertions, 40 deletions
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index b0fc983969..b59af0fd7b 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -15,43 +15,6 @@
#define MIPS_USES_R4K_TLB
#define MIPS_TLB_NB 16
#define MIPS_TLB_MAX 128
-/* Define a implementation number of 1.
- * Define a major version 1, minor version 0.
- */
-#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
- /* Have config1, is MIPS32R1, uses TLB, no virtual icache,
- uncached coherency */
-#define MIPS_CONFIG0_1 \
- ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
- (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
- (0x2 << CP0C0_K0))
-#ifdef TARGET_WORDS_BIGENDIAN
-#define MIPS_CONFIG0 (MIPS_CONFIG0_1 | (1 << CP0C0_BE))
-#else
-#define MIPS_CONFIG0 MIPS_CONFIG0_1
-#endif
-/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
- 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
- no coprocessor2 attached, no MDMX support attached,
- no performance counters, watch registers present,
- no code compression, EJTAG present, no FPU */
-#define MIPS_CONFIG1 \
-((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \
- (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
- (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
- (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
- (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
- (0 << CP0C1_FP))
-/* Have config3, no tertiary/secondary caches implemented */
-#define MIPS_CONFIG2 \
-((1 << CP0C2_M))
-/* No config4, no DSP ASE, no large physaddr,
- no external interrupt controller, no vectored interupts,
- no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
-#define MIPS_CONFIG3 \
-((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
- (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
- (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
#ifdef MIPS_HAS_MIPS64
#define TARGET_LONG_BITS 64
diff --git a/target-mips/translate.c b/target-mips/translate.c
index b39ec5f98a..89061db9aa 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5292,8 +5292,6 @@ void cpu_reset (CPUMIPSState *env)
env->CP0_Wired = 0;
/* SMP not implemented */
env->CP0_EBase = 0x80000000;
- env->CP0_Config2 = MIPS_CONFIG2;
- env->CP0_Config3 = MIPS_CONFIG3;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
env->CP0_WatchLo = 0;
env->hflags = MIPS_HFLAG_ERL;
@@ -5305,7 +5303,6 @@ void cpu_reset (CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_UM;
env->user_mode_only = 1;
#endif
- env->fcr0 = MIPS_FCR0;
/* XXX some guesswork here, values are CPU specific */
env->SYNCI_Step = 16;
env->CCRes = 2;
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index b7baff1871..b87d8f3b58 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -19,11 +19,53 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+/* CPU / CPU family specific config register values. */
+
+/* Have config1, is MIPS32R1, uses TLB, no virtual icache,
+ uncached coherency */
+#define MIPS_CONFIG0 \
+ ((1 << CP0C0_M) | (0x0 << CP0C0_K23) | (0x0 << CP0C0_KU) | \
+ (0x0 << CP0C0_AT) | (0x0 << CP0C0_AR) | (0x1 << CP0C0_MT) | \
+ (0x2 << CP0C0_K0))
+
+/* Have config2, 16 TLB entries, 64 sets Icache, 16 bytes Icache line,
+ 2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
+ no coprocessor2 attached, no MDMX support attached,
+ no performance counters, watch registers present,
+ no code compression, EJTAG present, no FPU */
+#define MIPS_CONFIG1 \
+((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) | \
+ (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) | \
+ (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) | \
+ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
+ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
+ (0 << CP0C1_FP))
+
+/* Have config3, no tertiary/secondary caches implemented */
+#define MIPS_CONFIG2 \
+((1 << CP0C2_M))
+
+/* No config4, no DSP ASE, no large physaddr,
+ no external interrupt controller, no vectored interupts,
+ no 1kb pages, no MT ASE, no SmartMIPS ASE, no trace logic */
+#define MIPS_CONFIG3 \
+((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
+ (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
+ (0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL))
+
+/* Define a implementation number of 1.
+ Define a major version 1, minor version 0. */
+#define MIPS_FCR0 ((0 << 16) | (1 << 8) | (1 << 4) | 0)
+
+
struct mips_def_t {
const unsigned char *name;
int32_t CP0_PRid;
int32_t CP0_Config0;
int32_t CP0_Config1;
+ int32_t CP0_Config2;
+ int32_t CP0_Config3;
+ int32_t CP1_fcr0;
};
/*****************************************************************************/
@@ -36,18 +78,27 @@ static mips_def_t mips_defs[] =
.CP0_PRid = 0x00018000,
.CP0_Config0 = MIPS_CONFIG0,
.CP0_Config1 = MIPS_CONFIG1,
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP1_fcr0 = MIPS_FCR0,
},
{
.name = "4KEc",
.CP0_PRid = 0x00018400,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
.CP0_Config1 = MIPS_CONFIG1,
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP1_fcr0 = MIPS_FCR0,
},
{
.name = "24Kf",
.CP0_PRid = 0x00019300,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP1_fcr0 = MIPS_FCR0,
},
#else
{
@@ -55,6 +106,9 @@ static mips_def_t mips_defs[] =
.CP0_PRid = 0x00000400,
.CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
+ .CP0_Config2 = MIPS_CONFIG2,
+ .CP0_Config3 = MIPS_CONFIG3,
+ .CP1_fcr0 = MIPS_FCR0,
},
#endif
};
@@ -91,7 +145,14 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
if (!def)
cpu_abort(env, "Unable to find MIPS CPU definition\n");
env->CP0_PRid = def->CP0_PRid;
+#ifdef TARGET_WORDS_BIGENDIAN
+ env->CP0_Config0 = def->CP0_Config0 | (1 << CP0C0_BE);
+#else
env->CP0_Config0 = def->CP0_Config0;
+#endif
env->CP0_Config1 = def->CP0_Config1;
+ env->CP0_Config2 = def->CP0_Config2;
+ env->CP0_Config3 = def->CP0_Config3;
+ env->fcr0 = def->CP1_fcr0;
return 0;
}
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-16 05:38:41 +0000