diff options
| -rw-r--r-- | target-mips/exec.h | 35 | ||||
| -rw-r--r-- | target-mips/helper.h | 118 | ||||
| -rw-r--r-- | target-mips/op.c | 954 | ||||
| -rw-r--r-- | target-mips/op_helper.c | 792 | ||||
| -rw-r--r-- | target-mips/translate.c | 516 |
5 files changed, 1179 insertions, 1236 deletions
diff --git a/target-mips/exec.h b/target-mips/exec.h index f10a35df03..c927005729 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -48,28 +48,6 @@ register target_ulong T1 asm(AREG2); #include "softmmu_exec.h" #endif /* !defined(CONFIG_USER_ONLY) */ -#if defined(TARGET_MIPS64) -#if TARGET_LONG_BITS > HOST_LONG_BITS -void do_dsll (void); -void do_dsll32 (void); -void do_dsra (void); -void do_dsra32 (void); -void do_dsrl (void); -void do_dsrl32 (void); -void do_drotr (void); -void do_drotr32 (void); -void do_dsllv (void); -void do_dsrav (void); -void do_dsrlv (void); -void do_drotrv (void); -void do_dclo (void); -void do_dclz (void); -#endif -#endif - -#if HOST_LONG_BITS < 64 -void do_div (void); -#endif #if TARGET_LONG_BITS > HOST_LONG_BITS void do_mult (void); void do_multu (void); @@ -92,15 +70,7 @@ void do_mulhiu (void); void do_mulshi (void); void do_mulshiu (void); #endif -#if defined(TARGET_MIPS64) -void do_ddiv (void); -#if TARGET_LONG_BITS > HOST_LONG_BITS -void do_ddivu (void); -#endif -#endif -void do_mfc0_random(void); -void do_mfc0_count(void); -void do_mtc0_entryhi(uint32_t in); + void do_mtc0_status_debug(uint32_t old, uint32_t val); void do_mtc0_status_irqraise_debug(void); void dump_fpu(CPUState *env); @@ -133,9 +103,6 @@ void cpu_mips_update_irq (CPUState *env); void cpu_mips_clock_init (CPUState *env); void cpu_mips_tlb_flush (CPUState *env, int flush_global); -void do_cfc1 (int reg); -void do_ctc1 (int reg); - #define FOP_PROTO(op) \ void do_float_ ## op ## _s(void); \ void do_float_ ## op ## _d(void); diff --git a/target-mips/helper.h b/target-mips/helper.h index cee92fc823..ddc82f1df5 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -12,3 +12,121 @@ DEF_HELPER(void, do_clz, (void)) DEF_HELPER(void, do_dclo, (void)) DEF_HELPER(void, do_dclz, (void)) #endif + +/* CP0 helpers */ +#ifndef CONFIG_USER_ONLY +DEF_HELPER(void, do_mfc0_mvpcontrol, (void)) +DEF_HELPER(void, do_mfc0_mvpconf0, (void)) +DEF_HELPER(void, do_mfc0_mvpconf1, (void)) +DEF_HELPER(void, do_mfc0_random, (void)) +DEF_HELPER(void, do_mfc0_tcstatus, (void)) +DEF_HELPER(void, do_mftc0_tcstatus, (void)) +DEF_HELPER(void, do_mfc0_tcbind, (void)) +DEF_HELPER(void, do_mftc0_tcbind, (void)) +DEF_HELPER(void, do_mfc0_tcrestart, (void)) +DEF_HELPER(void, do_mftc0_tcrestart, (void)) +DEF_HELPER(void, do_mfc0_tchalt, (void)) +DEF_HELPER(void, do_mftc0_tchalt, (void)) +DEF_HELPER(void, do_mfc0_tccontext, (void)) +DEF_HELPER(void, do_mftc0_tccontext, (void)) +DEF_HELPER(void, do_mfc0_tcschedule, (void)) +DEF_HELPER(void, do_mftc0_tcschedule, (void)) +DEF_HELPER(void, do_mfc0_tcschefback, (void)) +DEF_HELPER(void, do_mftc0_tcschefback, (void)) +DEF_HELPER(void, do_mfc0_count, (void)) +DEF_HELPER(void, do_mftc0_entryhi, (void)) +DEF_HELPER(void, do_mftc0_status, (void)) +DEF_HELPER(void, do_mfc0_lladdr, (void)) +DEF_HELPER(void, do_mfc0_watchlo, (uint32_t sel)) +DEF_HELPER(void, do_mfc0_watchhi, (uint32_t sel)) +DEF_HELPER(void, do_mfc0_debug, (void)) +DEF_HELPER(void, do_mftc0_debug, (void)) +#ifdef TARGET_MIPS64 +DEF_HELPER(void, do_dmfc0_tcrestart, (void)) +DEF_HELPER(void, do_dmfc0_tchalt, (void)) +DEF_HELPER(void, do_dmfc0_tccontext, (void)) +DEF_HELPER(void, do_dmfc0_tcschedule, (void)) +DEF_HELPER(void, do_dmfc0_tcschefback, (void)) +DEF_HELPER(void, do_dmfc0_lladdr, (void)) +DEF_HELPER(void, do_dmfc0_watchlo, (uint32_t sel)) +#endif /* TARGET_MIPS64 */ + +DEF_HELPER(void, do_mtc0_index, (void)) +DEF_HELPER(void, do_mtc0_mvpcontrol, (void)) +DEF_HELPER(void, do_mtc0_vpecontrol, (void)) +DEF_HELPER(void, do_mtc0_vpeconf0, (void)) +DEF_HELPER(void, do_mtc0_vpeconf1, (void)) +DEF_HELPER(void, do_mtc0_yqmask, (void)) +DEF_HELPER(void, do_mtc0_vpeopt, (void)) +DEF_HELPER(void, do_mtc0_entrylo0, (void)) +DEF_HELPER(void, do_mtc0_tcstatus, (void)) +DEF_HELPER(void, do_mttc0_tcstatus, (void)) +DEF_HELPER(void, do_mtc0_tcbind, (void)) +DEF_HELPER(void, do_mttc0_tcbind, (void)) +DEF_HELPER(void, do_mtc0_tcrestart, (void)) +DEF_HELPER(void, do_mttc0_tcrestart, (void)) +DEF_HELPER(void, do_mtc0_tchalt, (void)) +DEF_HELPER(void, do_mttc0_tchalt, (void)) +DEF_HELPER(void, do_mtc0_tccontext, (void)) +DEF_HELPER(void, do_mttc0_tccontext, (void)) +DEF_HELPER(void, do_mtc0_tcschedule, (void)) +DEF_HELPER(void, do_mttc0_tcschedule, (void)) +DEF_HELPER(void, do_mtc0_tcschefback, (void)) +DEF_HELPER(void, do_mttc0_tcschefback, (void)) +DEF_HELPER(void, do_mtc0_entrylo1, (void)) +DEF_HELPER(void, do_mtc0_context, (void)) +DEF_HELPER(void, do_mtc0_pagemask, (void)) +DEF_HELPER(void, do_mtc0_pagegrain, (void)) +DEF_HELPER(void, do_mtc0_wired, (void)) +DEF_HELPER(void, do_mtc0_srsconf0, (void)) +DEF_HELPER(void, do_mtc0_srsconf1, (void)) +DEF_HELPER(void, do_mtc0_srsconf2, (void)) +DEF_HELPER(void, do_mtc0_srsconf3, (void)) +DEF_HELPER(void, do_mtc0_srsconf4, (void)) +DEF_HELPER(void, do_mtc0_hwrena, (void)) +DEF_HELPER(void, do_mtc0_count, (void)) +DEF_HELPER(void, do_mtc0_entryhi, (void)) +DEF_HELPER(void, do_mttc0_entryhi, (void)) +DEF_HELPER(void, do_mtc0_compare, (void)) +DEF_HELPER(void, do_mtc0_status, (void)) +DEF_HELPER(void, do_mttc0_status, (void)) +DEF_HELPER(void, do_mtc0_intctl, (void)) +DEF_HELPER(void, do_mtc0_srsctl, (void)) +DEF_HELPER(void, do_mtc0_cause, (void)) +DEF_HELPER(void, do_mtc0_ebase, (void)) +DEF_HELPER(void, do_mtc0_config0, (void)) +DEF_HELPER(void, do_mtc0_config2, (void)) +DEF_HELPER(void, do_mtc0_watchlo, (uint32_t sel)) +DEF_HELPER(void, do_mtc0_watchhi, (uint32_t sel)) +DEF_HELPER(void, do_mtc0_xcontext, (void)) +DEF_HELPER(void, do_mtc0_framemask, (void)) +DEF_HELPER(void, do_mtc0_debug, (void)) +DEF_HELPER(void, do_mttc0_debug, (void)) +DEF_HELPER(void, do_mtc0_performance0, (void)) +DEF_HELPER(void, do_mtc0_taglo, (void)) +DEF_HELPER(void, do_mtc0_datalo, (void)) +DEF_HELPER(void, do_mtc0_taghi, (void)) +DEF_HELPER(void, do_mtc0_datahi, (void)) +#endif /* !CONFIG_USER_ONLY */ + +/* MIPS MT functions */ +DEF_HELPER(void, do_mftgpr, (uint32_t sel)) +DEF_HELPER(void, do_mftlo, (uint32_t sel)) +DEF_HELPER(void, do_mfthi, (uint32_t sel)) +DEF_HELPER(void, do_mftacx, (uint32_t sel)) +DEF_HELPER(void, do_mftdsp, (void)) +DEF_HELPER(void, do_mttgpr, (uint32_t sel)) +DEF_HELPER(void, do_mttlo, (uint32_t sel)) +DEF_HELPER(void, do_mtthi, (uint32_t sel)) +DEF_HELPER(void, do_mttacx, (uint32_t sel)) +DEF_HELPER(void, do_mttdsp, (void)) +DEF_HELPER(void, do_dmt, (void)) +DEF_HELPER(void, do_emt, (void)) +DEF_HELPER(void, do_dvpe, (void)) +DEF_HELPER(void, do_evpe, (void)) +DEF_HELPER(void, do_fork, (void)) +DEF_HELPER(void, do_yield, (void)) + +/* CP1 functions */ +DEF_HELPER(void, do_cfc1, (uint32_t reg)) +DEF_HELPER(void, do_ctc1, (uint32_t reg)) diff --git a/target-mips/op.c b/target-mips/op.c index f09c2a4510..ff5aed9681 100644 --- a/target-mips/op.c +++ b/target-mips/op.c @@ -460,946 +460,6 @@ void op_dmultu (void) } #endif -/* CP0 functions */ -void op_mfc0_mvpcontrol (void) -{ - T0 = env->mvp->CP0_MVPControl; - FORCE_RET(); -} - -void op_mfc0_mvpconf0 (void) -{ - T0 = env->mvp->CP0_MVPConf0; - FORCE_RET(); -} - -void op_mfc0_mvpconf1 (void) -{ - T0 = env->mvp->CP0_MVPConf1; - FORCE_RET(); -} - -void op_mfc0_random (void) -{ - CALL_FROM_TB0(do_mfc0_random); - FORCE_RET(); -} - -void op_mfc0_tcstatus (void) -{ - T0 = env->CP0_TCStatus[env->current_tc]; - FORCE_RET(); -} - -void op_mftc0_tcstatus(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->CP0_TCStatus[other_tc]; - FORCE_RET(); -} - -void op_mfc0_tcbind (void) -{ - T0 = env->CP0_TCBind[env->current_tc]; - FORCE_RET(); -} - -void op_mftc0_tcbind(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->CP0_TCBind[other_tc]; - FORCE_RET(); -} - -void op_mfc0_tcrestart (void) -{ - T0 = env->PC[env->current_tc]; - FORCE_RET(); -} - -void op_mftc0_tcrestart(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->PC[other_tc]; - FORCE_RET(); -} - -void op_mfc0_tchalt (void) -{ - T0 = env->CP0_TCHalt[env->current_tc]; - FORCE_RET(); -} - -void op_mftc0_tchalt(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->CP0_TCHalt[other_tc]; - FORCE_RET(); -} - -void op_mfc0_tccontext (void) -{ - T0 = env->CP0_TCContext[env->current_tc]; - FORCE_RET(); -} - -void op_mftc0_tccontext(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->CP0_TCContext[other_tc]; - FORCE_RET(); -} - -void op_mfc0_tcschedule (void) -{ - T0 = env->CP0_TCSchedule[env->current_tc]; - FORCE_RET(); -} - -void op_mftc0_tcschedule(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->CP0_TCSchedule[other_tc]; - FORCE_RET(); -} - -void op_mfc0_tcschefback (void) -{ - T0 = env->CP0_TCScheFBack[env->current_tc]; - FORCE_RET(); -} - -void op_mftc0_tcschefback(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->CP0_TCScheFBack[other_tc]; - FORCE_RET(); -} - -void op_mfc0_count (void) -{ - CALL_FROM_TB0(do_mfc0_count); - FORCE_RET(); -} - -void op_mftc0_entryhi(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); - FORCE_RET(); -} - -void op_mftc0_status(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - uint32_t tcstatus = env->CP0_TCStatus[other_tc]; - - T0 = env->CP0_Status & ~0xf1000018; - T0 |= tcstatus & (0xf << CP0TCSt_TCU0); - T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); - T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); - FORCE_RET(); -} - -void op_mfc0_lladdr (void) -{ - T0 = (int32_t)env->CP0_LLAddr >> 4; - FORCE_RET(); -} - -void op_mfc0_watchlo (void) -{ - T0 = (int32_t)env->CP0_WatchLo[PARAM1]; - FORCE_RET(); -} - -void op_mfc0_watchhi (void) -{ - T0 = env->CP0_WatchHi[PARAM1]; - FORCE_RET(); -} - -void op_mfc0_debug (void) -{ - T0 = env->CP0_Debug; - if (env->hflags & MIPS_HFLAG_DM) - T0 |= 1 << CP0DB_DM; - FORCE_RET(); -} - -void op_mftc0_debug(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - /* XXX: Might be wrong, check with EJTAG spec. */ - T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | - (env->CP0_Debug_tcstatus[other_tc] & - ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); - FORCE_RET(); -} - -void op_mtc0_index (void) -{ - int num = 1; - unsigned int tmp = env->tlb->nb_tlb; - - do { - tmp >>= 1; - num <<= 1; - } while (tmp); - env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1)); - FORCE_RET(); -} - -void op_mtc0_mvpcontrol (void) -{ - uint32_t mask = 0; - uint32_t newval; - - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) - mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | - (1 << CP0MVPCo_EVP); - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) - mask |= (1 << CP0MVPCo_STLB); - newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask); - - // TODO: Enable/disable shared TLB, enable/disable VPEs. - - env->mvp->CP0_MVPControl = newval; - FORCE_RET(); -} - -void op_mtc0_vpecontrol (void) -{ - uint32_t mask; - uint32_t newval; - - mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | - (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); - newval = (env->CP0_VPEControl & ~mask) | (T0 & mask); - - /* Yield scheduler intercept not implemented. */ - /* Gating storage scheduler intercept not implemented. */ - - // TODO: Enable/disable TCs. - - env->CP0_VPEControl = newval; - FORCE_RET(); -} - -void op_mtc0_vpeconf0 (void) -{ - uint32_t mask = 0; - uint32_t newval; - - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) - mask |= (0xff << CP0VPEC0_XTC); - mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); - } - newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask); - - // TODO: TC exclusive handling due to ERL/EXL. - - env->CP0_VPEConf0 = newval; - FORCE_RET(); -} - -void op_mtc0_vpeconf1 (void) -{ - uint32_t mask = 0; - uint32_t newval; - - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) - mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | - (0xff << CP0VPEC1_NCP1); - newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask); - - /* UDI not implemented. */ - /* CP2 not implemented. */ - - // TODO: Handle FPU (CP1) binding. - - env->CP0_VPEConf1 = newval; - FORCE_RET(); -} - -void op_mtc0_yqmask (void) -{ - /* Yield qualifier inputs not implemented. */ - env->CP0_YQMask = 0x00000000; - FORCE_RET(); -} - -void op_mtc0_vpeschedule (void) -{ - env->CP0_VPESchedule = T0; - FORCE_RET(); -} - -void op_mtc0_vpeschefback (void) -{ - env->CP0_VPEScheFBack = T0; - FORCE_RET(); -} - -void op_mtc0_vpeopt (void) -{ - env->CP0_VPEOpt = T0 & 0x0000ffff; - FORCE_RET(); -} - -void op_mtc0_entrylo0 (void) -{ - /* Large physaddr (PABITS) not implemented */ - /* 1k pages not implemented */ - env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; - FORCE_RET(); -} - -void op_mtc0_tcstatus (void) -{ - uint32_t mask = env->CP0_TCStatus_rw_bitmask; - uint32_t newval; - - newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask); - - // TODO: Sync with CP0_Status. - - env->CP0_TCStatus[env->current_tc] = newval; - FORCE_RET(); -} - -void op_mttc0_tcstatus (void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - // TODO: Sync with CP0_Status. - - env->CP0_TCStatus[other_tc] = T0; - FORCE_RET(); -} - -void op_mtc0_tcbind (void) -{ - uint32_t mask = (1 << CP0TCBd_TBE); - uint32_t newval; - - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) - mask |= (1 << CP0TCBd_CurVPE); - newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask); - env->CP0_TCBind[env->current_tc] = newval; - FORCE_RET(); -} - -void op_mttc0_tcbind (void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - uint32_t mask = (1 << CP0TCBd_TBE); - uint32_t newval; - - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) - mask |= (1 << CP0TCBd_CurVPE); - newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask); - env->CP0_TCBind[other_tc] = newval; - FORCE_RET(); -} - -void op_mtc0_tcrestart (void) -{ - env->PC[env->current_tc] = T0; - env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS); - env->CP0_LLAddr = 0ULL; - /* MIPS16 not implemented. */ - FORCE_RET(); -} - -void op_mttc0_tcrestart (void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - env->PC[other_tc] = T0; - env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS); - env->CP0_LLAddr = 0ULL; - /* MIPS16 not implemented. */ - FORCE_RET(); -} - -void op_mtc0_tchalt (void) -{ - env->CP0_TCHalt[env->current_tc] = T0 & 0x1; - - // TODO: Halt TC / Restart (if allocated+active) TC. - - FORCE_RET(); -} - -void op_mttc0_tchalt (void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - // TODO: Halt TC / Restart (if allocated+active) TC. - - env->CP0_TCHalt[other_tc] = T0; - FORCE_RET(); -} - -void op_mtc0_tccontext (void) -{ - env->CP0_TCContext[env->current_tc] = T0; - FORCE_RET(); -} - -void op_mttc0_tccontext (void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - env->CP0_TCContext[other_tc] = T0; - FORCE_RET(); -} - -void op_mtc0_tcschedule (void) -{ - env->CP0_TCSchedule[env->current_tc] = T0; - FORCE_RET(); -} - -void op_mttc0_tcschedule (void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - env->CP0_TCSchedule[other_tc] = T0; - FORCE_RET(); -} - -void op_mtc0_tcschefback (void) -{ - env->CP0_TCScheFBack[env->current_tc] = T0; - FORCE_RET(); -} - -void op_mttc0_tcschefback (void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - env->CP0_TCScheFBack[other_tc] = T0; - FORCE_RET(); -} - -void op_mtc0_entrylo1 (void) -{ - /* Large physaddr (PABITS) not implemented */ - /* 1k pages not implemented */ - env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; - FORCE_RET(); -} - -void op_mtc0_context (void) -{ - env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); - FORCE_RET(); -} - -void op_mtc0_pagemask (void) -{ - /* 1k pages not implemented */ - env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); - FORCE_RET(); -} - -void op_mtc0_pagegrain (void) -{ - /* SmartMIPS not implemented */ - /* Large physaddr (PABITS) not implemented */ - /* 1k pages not implemented */ - env->CP0_PageGrain = 0; - FORCE_RET(); -} - -void op_mtc0_wired (void) -{ - env->CP0_Wired = T0 % env->tlb->nb_tlb; - FORCE_RET(); -} - -void op_mtc0_srsconf0 (void) -{ - env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask; - FORCE_RET(); -} - -void op_mtc0_srsconf1 (void) -{ - env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask; - FORCE_RET(); -} - -void op_mtc0_srsconf2 (void) -{ - env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask; - FORCE_RET(); -} - -void op_mtc0_srsconf3 (void) -{ - env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask; - FORCE_RET(); -} - -void op_mtc0_srsconf4 (void) -{ - env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask; - FORCE_RET(); -} - -void op_mtc0_hwrena (void) -{ - env->CP0_HWREna = T0 & 0x0000000F; - FORCE_RET(); -} - -void op_mtc0_count (void) -{ - CALL_FROM_TB2(cpu_mips_store_count, env, T0); - FORCE_RET(); -} - -void op_mtc0_entryhi (void) -{ - target_ulong old, val; - - /* 1k pages not implemented */ - val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); -#if defined(TARGET_MIPS64) - val &= env->SEGMask; -#endif - old = env->CP0_EntryHi; - env->CP0_EntryHi = val; - if (env->CP0_Config3 & (1 << CP0C3_MT)) { - uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff; - env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff); - } - /* If the ASID changes, flush qemu's TLB. */ - if ((old & 0xFF) != (val & 0xFF)) - CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1); - FORCE_RET(); -} - -void op_mttc0_entryhi(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff); - env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff); - FORCE_RET(); -} - -void op_mtc0_compare (void) -{ - CALL_FROM_TB2(cpu_mips_store_compare, env, T0); - FORCE_RET(); -} - -void op_mtc0_status (void) -{ - uint32_t val, old; - uint32_t mask = env->CP0_Status_rw_bitmask; - - val = T0 & mask; - old = env->CP0_Status; - env->CP0_Status = (env->CP0_Status & ~mask) | val; - CALL_FROM_TB1(compute_hflags, env); - if (loglevel & CPU_LOG_EXEC) - CALL_FROM_TB2(do_mtc0_status_debug, old, val); - CALL_FROM_TB1(cpu_mips_update_irq, env); - FORCE_RET(); -} - -void op_mttc0_status(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - uint32_t tcstatus = env->CP0_TCStatus[other_tc]; - - env->CP0_Status = T0 & ~0xf1000018; - tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0)); - tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); - tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); - env->CP0_TCStatus[other_tc] = tcstatus; - FORCE_RET(); -} - -void op_mtc0_intctl (void) -{ - /* vectored interrupts not implemented, no performance counters. */ - env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0); - FORCE_RET(); -} - -void op_mtc0_srsctl (void) -{ - uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); - env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask); - FORCE_RET(); -} - -void op_mtc0_srsmap (void) -{ - env->CP0_SRSMap = T0; - FORCE_RET(); -} - -void op_mtc0_cause (void) -{ - uint32_t mask = 0x00C00300; - uint32_t old = env->CP0_Cause; - - if (env->insn_flags & ISA_MIPS32R2) - mask |= 1 << CP0Ca_DC; - - env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) - CALL_FROM_TB1(cpu_mips_stop_count, env); - else - CALL_FROM_TB1(cpu_mips_start_count, env); - } - - /* Handle the software interrupt as an hardware one, as they - are very similar */ - if (T0 & CP0Ca_IP_mask) { - CALL_FROM_TB1(cpu_mips_update_irq, env); - } - FORCE_RET(); -} - -void op_mtc0_epc (void) -{ - env->CP0_EPC = T0; - FORCE_RET(); -} - -void op_mtc0_ebase (void) -{ - /* vectored interrupts not implemented */ - /* Multi-CPU not implemented */ - env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); - FORCE_RET(); -} - -void op_mtc0_config0 (void) -{ - env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007); - FORCE_RET(); -} - -void op_mtc0_config2 (void) -{ - /* tertiary/secondary caches not implemented */ - env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); - FORCE_RET(); -} - -void op_mtc0_watchlo (void) -{ - /* Watch exceptions for instructions, data loads, data stores - not implemented. */ - env->CP0_WatchLo[PARAM1] = (T0 & ~0x7); - FORCE_RET(); -} - -void op_mtc0_watchhi (void) -{ - env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8); - env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7); - FORCE_RET(); -} - -void op_mtc0_xcontext (void) -{ - target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; - env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask); - FORCE_RET(); -} - -void op_mtc0_framemask (void) -{ - env->CP0_Framemask = T0; /* XXX */ - FORCE_RET(); -} - -void op_mtc0_debug (void) -{ - env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); - if (T0 & (1 << CP0DB_DM)) - env->hflags |= MIPS_HFLAG_DM; - else - env->hflags &= ~MIPS_HFLAG_DM; - FORCE_RET(); -} - -void op_mttc0_debug(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - /* XXX: Might be wrong, check with EJTAG spec. */ - env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); - env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | - (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); - FORCE_RET(); -} - -void op_mtc0_depc (void) -{ - env->CP0_DEPC = T0; - FORCE_RET(); -} - -void op_mtc0_performance0 (void) -{ - env->CP0_Performance0 = T0 & 0x000007ff; - FORCE_RET(); -} - -void op_mtc0_taglo (void) -{ - env->CP0_TagLo = T0 & 0xFFFFFCF6; - FORCE_RET(); -} - -void op_mtc0_datalo (void) -{ - env->CP0_DataLo = T0; /* XXX */ - FORCE_RET(); -} - -void op_mtc0_taghi (void) -{ - env->CP0_TagHi = T0; /* XXX */ - FORCE_RET(); -} - -void op_mtc0_datahi (void) -{ - env->CP0_DataHi = T0; /* XXX */ - FORCE_RET(); -} - -void op_mtc0_errorepc (void) -{ - env->CP0_ErrorEPC = T0; - FORCE_RET(); -} - -void op_mtc0_desave (void) -{ - env->CP0_DESAVE = T0; - FORCE_RET(); -} - -#if defined(TARGET_MIPS64) -void op_dmfc0_tcrestart (void) -{ - T0 = env->PC[env->current_tc]; - FORCE_RET(); -} - -void op_dmfc0_tchalt (void) -{ - T0 = env->CP0_TCHalt[env->current_tc]; - FORCE_RET(); -} - -void op_dmfc0_tccontext (void) -{ - T0 = env->CP0_TCContext[env->current_tc]; - FORCE_RET(); -} - -void op_dmfc0_tcschedule (void) -{ - T0 = env->CP0_TCSchedule[env->current_tc]; - FORCE_RET(); -} - -void op_dmfc0_tcschefback (void) -{ - T0 = env->CP0_TCScheFBack[env->current_tc]; - FORCE_RET(); -} - -void op_dmfc0_lladdr (void) -{ - T0 = env->CP0_LLAddr >> 4; - FORCE_RET(); -} - -void op_dmfc0_watchlo (void) -{ - T0 = env->CP0_WatchLo[PARAM1]; - FORCE_RET(); -} -#endif /* TARGET_MIPS64 */ - -/* MIPS MT functions */ -void op_mftgpr(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->gpr[other_tc][PARAM1]; - FORCE_RET(); -} - -void op_mftlo(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->LO[other_tc][PARAM1]; - FORCE_RET(); -} - -void op_mfthi(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->HI[other_tc][PARAM1]; - FORCE_RET(); -} - -void op_mftacx(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->ACX[other_tc][PARAM1]; - FORCE_RET(); -} - -void op_mftdsp(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->DSPControl[other_tc]; - FORCE_RET(); -} - -void op_mttgpr(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->gpr[other_tc][PARAM1]; - FORCE_RET(); -} - -void op_mttlo(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->LO[other_tc][PARAM1]; - FORCE_RET(); -} - -void op_mtthi(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->HI[other_tc][PARAM1]; - FORCE_RET(); -} - -void op_mttacx(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->ACX[other_tc][PARAM1]; - FORCE_RET(); -} - -void op_mttdsp(void) -{ - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - - T0 = env->DSPControl[other_tc]; - FORCE_RET(); -} - - -void op_dmt(void) -{ - // TODO - T0 = 0; - // rt = T0 - FORCE_RET(); -} - -void op_emt(void) -{ - // TODO - T0 = 0; - // rt = T0 - FORCE_RET(); -} - -void op_dvpe(void) -{ - // TODO - T0 = 0; - // rt = T0 - FORCE_RET(); -} - -void op_evpe(void) -{ - // TODO - T0 = 0; - // rt = T0 - FORCE_RET(); -} - -void op_fork(void) -{ - // T0 = rt, T1 = rs - T0 = 0; - // TODO: store to TC register - FORCE_RET(); -} - -void op_yield(void) -{ - if (T0 < 0) { - /* No scheduling policy implemented. */ - if (T0 != -2) { - if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && - env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) { - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); - } - } - } else if (T0 == 0) { - if (0 /* TODO: TC underflow */) { - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); - } else { - // TODO: Deallocate TC - } - } else if (T0 > 0) { - /* Yield qualifier inputs not implemented. */ - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); - } - T0 = env->CP0_YQMask; - FORCE_RET(); -} - /* CP1 functions */ #if 0 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env) @@ -1407,20 +467,6 @@ void op_yield(void) # define DEBUG_FPU_STATE() do { } while(0) #endif -void op_cfc1 (void) -{ - CALL_FROM_TB1(do_cfc1, PARAM1); - DEBUG_FPU_STATE(); - FORCE_RET(); -} - -void op_ctc1 (void) -{ - CALL_FROM_TB1(do_ctc1, PARAM1); - DEBUG_FPU_STATE(); - FORCE_RET(); -} - void op_mfc1 (void) { T0 = (int32_t)WT0; diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 2020e9efe3..ae91acdb07 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -306,7 +306,7 @@ void do_mulshiu (void) } #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ -#if defined(CONFIG_USER_ONLY) +#ifdef CONFIG_USER_ONLY void do_mfc0_random (void) { cpu_abort(env, "mfc0 random\n"); @@ -360,16 +360,662 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global) #else /* CP0 helpers */ +void do_mfc0_mvpcontrol (void) +{ + T0 = env->mvp->CP0_MVPControl; +} + +void do_mfc0_mvpconf0 (void) +{ + T0 = env->mvp->CP0_MVPConf0; +} + +void do_mfc0_mvpconf1 (void) +{ + T0 = env->mvp->CP0_MVPConf1; +} + void do_mfc0_random (void) { T0 = (int32_t)cpu_mips_get_random(env); } +void do_mfc0_tcstatus (void) +{ + T0 = env->CP0_TCStatus[env->current_tc]; +} + +void do_mftc0_tcstatus(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->CP0_TCStatus[other_tc]; +} + +void do_mfc0_tcbind (void) +{ + T0 = env->CP0_TCBind[env->current_tc]; +} + +void do_mftc0_tcbind(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->CP0_TCBind[other_tc]; +} + +void do_mfc0_tcrestart (void) +{ + T0 = env->PC[env->current_tc]; +} + +void do_mftc0_tcrestart(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->PC[other_tc]; +} + +void do_mfc0_tchalt (void) +{ + T0 = env->CP0_TCHalt[env->current_tc]; +} + +void do_mftc0_tchalt(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->CP0_TCHalt[other_tc]; +} + +void do_mfc0_tccontext (void) +{ + T0 = env->CP0_TCContext[env->current_tc]; +} + +void do_mftc0_tccontext(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->CP0_TCContext[other_tc]; +} + +void do_mfc0_tcschedule (void) +{ + T0 = env->CP0_TCSchedule[env->current_tc]; +} + +void do_mftc0_tcschedule(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->CP0_TCSchedule[other_tc]; +} + +void do_mfc0_tcschefback (void) +{ + T0 = env->CP0_TCScheFBack[env->current_tc]; +} + +void do_mftc0_tcschefback(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->CP0_TCScheFBack[other_tc]; +} + void do_mfc0_count (void) { T0 = (int32_t)cpu_mips_get_count(env); } +void do_mftc0_entryhi(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); +} + +void do_mftc0_status(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t tcstatus = env->CP0_TCStatus[other_tc]; + + T0 = env->CP0_Status & ~0xf1000018; + T0 |= tcstatus & (0xf << CP0TCSt_TCU0); + T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX); + T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU); +} + +void do_mfc0_lladdr (void) +{ + T0 = (int32_t)env->CP0_LLAddr >> 4; +} + +void do_mfc0_watchlo (uint32_t sel) +{ + T0 = (int32_t)env->CP0_WatchLo[sel]; +} + +void do_mfc0_watchhi (uint32_t sel) +{ + T0 = env->CP0_WatchHi[sel]; +} + +void do_mfc0_debug (void) +{ + T0 = env->CP0_Debug; + if (env->hflags & MIPS_HFLAG_DM) + T0 |= 1 << CP0DB_DM; +} + +void do_mftc0_debug(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + /* XXX: Might be wrong, check with EJTAG spec. */ + T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | + (env->CP0_Debug_tcstatus[other_tc] & + ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); +} + +#if defined(TARGET_MIPS64) +void do_dmfc0_tcrestart (void) +{ + T0 = env->PC[env->current_tc]; +} + +void do_dmfc0_tchalt (void) +{ + T0 = env->CP0_TCHalt[env->current_tc]; +} + +void do_dmfc0_tccontext (void) +{ + T0 = env->CP0_TCContext[env->current_tc]; +} + +void do_dmfc0_tcschedule (void) +{ + T0 = env->CP0_TCSchedule[env->current_tc]; +} + +void do_dmfc0_tcschefback (void) +{ + T0 = env->CP0_TCScheFBack[env->current_tc]; +} + +void do_dmfc0_lladdr (void) +{ + T0 = env->CP0_LLAddr >> 4; +} + +void do_dmfc0_watchlo (uint32_t sel) +{ + T0 = env->CP0_WatchLo[sel]; +} +#endif /* TARGET_MIPS64 */ + +void do_mtc0_index (void) +{ + int num = 1; + unsigned int tmp = env->tlb->nb_tlb; + + do { + tmp >>= 1; + num <<= 1; + } while (tmp); + env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1)); +} + +void do_mtc0_mvpcontrol (void) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) + mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | + (1 << CP0MVPCo_EVP); + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0MVPCo_STLB); + newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask); + + // TODO: Enable/disable shared TLB, enable/disable VPEs. + + env->mvp->CP0_MVPControl = newval; +} + +void do_mtc0_vpecontrol (void) +{ + uint32_t mask; + uint32_t newval; + + mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | + (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); + newval = (env->CP0_VPEControl & ~mask) | (T0 & mask); + + /* Yield scheduler intercept not implemented. */ + /* Gating storage scheduler intercept not implemented. */ + + // TODO: Enable/disable TCs. + + env->CP0_VPEControl = newval; +} + +void do_mtc0_vpeconf0 (void) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) + mask |= (0xff << CP0VPEC0_XTC); + mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); + } + newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask); + + // TODO: TC exclusive handling due to ERL/EXL. + + env->CP0_VPEConf0 = newval; +} + +void do_mtc0_vpeconf1 (void) +{ + uint32_t mask = 0; + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | + (0xff << CP0VPEC1_NCP1); + newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask); + + /* UDI not implemented. */ + /* CP2 not implemented. */ + + // TODO: Handle FPU (CP1) binding. + + env->CP0_VPEConf1 = newval; +} + +void do_mtc0_yqmask (void) +{ + /* Yield qualifier inputs not implemented. */ + env->CP0_YQMask = 0x00000000; +} + +void do_mtc0_vpeopt (void) +{ + env->CP0_VPEOpt = T0 & 0x0000ffff; +} + +void do_mtc0_entrylo0 (void) +{ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_EntryLo0 = T0 & 0x3FFFFFFF; +} + +void do_mtc0_tcstatus (void) +{ + uint32_t mask = env->CP0_TCStatus_rw_bitmask; + uint32_t newval; + + newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask); + + // TODO: Sync with CP0_Status. + + env->CP0_TCStatus[env->current_tc] = newval; +} + +void do_mttc0_tcstatus (void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + // TODO: Sync with CP0_Status. + + env->CP0_TCStatus[other_tc] = T0; +} + +void do_mtc0_tcbind (void) +{ + uint32_t mask = (1 << CP0TCBd_TBE); + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0TCBd_CurVPE); + newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask); + env->CP0_TCBind[env->current_tc] = newval; +} + +void do_mttc0_tcbind (void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask = (1 << CP0TCBd_TBE); + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |= (1 << CP0TCBd_CurVPE); + newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask); + env->CP0_TCBind[other_tc] = newval; +} + +void do_mtc0_tcrestart (void) +{ + env->PC[env->current_tc] = T0; + env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS); + env->CP0_LLAddr = 0ULL; + /* MIPS16 not implemented. */ +} + +void do_mttc0_tcrestart (void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + env->PC[other_tc] = T0; + env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS); + env->CP0_LLAddr = 0ULL; + /* MIPS16 not implemented. */ +} + +void do_mtc0_tchalt (void) +{ + env->CP0_TCHalt[env->current_tc] = T0 & 0x1; + + // TODO: Halt TC / Restart (if allocated+active) TC. +} + +void do_mttc0_tchalt (void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + // TODO: Halt TC / Restart (if allocated+active) TC. + + env->CP0_TCHalt[other_tc] = T0; +} + +void do_mtc0_tccontext (void) +{ + env->CP0_TCContext[env->current_tc] = T0; +} + +void do_mttc0_tccontext (void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + env->CP0_TCContext[other_tc] = T0; +} + +void do_mtc0_tcschedule (void) +{ + env->CP0_TCSchedule[env->current_tc] = T0; +} + +void do_mttc0_tcschedule (void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + env->CP0_TCSchedule[other_tc] = T0; +} + +void do_mtc0_tcschefback (void) +{ + env->CP0_TCScheFBack[env->current_tc] = T0; +} + +void do_mttc0_tcschefback (void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + env->CP0_TCScheFBack[other_tc] = T0; +} + +void do_mtc0_entrylo1 (void) +{ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_EntryLo1 = T0 & 0x3FFFFFFF; +} + +void do_mtc0_context (void) +{ + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); +} + +void do_mtc0_pagemask (void) +{ + /* 1k pages not implemented */ + env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); +} + +void do_mtc0_pagegrain (void) +{ + /* SmartMIPS not implemented */ + /* Large physaddr (PABITS) not implemented */ + /* 1k pages not implemented */ + env->CP0_PageGrain = 0; +} + +void do_mtc0_wired (void) +{ + env->CP0_Wired = T0 % env->tlb->nb_tlb; +} + +void do_mtc0_srsconf0 (void) +{ + env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask; +} + +void do_mtc0_srsconf1 (void) +{ + env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask; +} + +void do_mtc0_srsconf2 (void) +{ + env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask; +} + +void do_mtc0_srsconf3 (void) +{ + env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask; +} + +void do_mtc0_srsconf4 (void) +{ + env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask; +} + +void do_mtc0_hwrena (void) +{ + env->CP0_HWREna = T0 & 0x0000000F; +} + +void do_mtc0_count (void) +{ + cpu_mips_store_count(env, T0); +} + +void do_mtc0_entryhi (void) +{ + target_ulong old, val; + + /* 1k pages not implemented */ + val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); +#if defined(TARGET_MIPS64) + val &= env->SEGMask; +#endif + old = env->CP0_EntryHi; + env->CP0_EntryHi = val; + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff; + env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff); + } + /* If the ASID changes, flush qemu's TLB. */ + if ((old & 0xFF) != (val & 0xFF)) + cpu_mips_tlb_flush(env, 1); +} + +void do_mttc0_entryhi(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff); + env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff); +} + +void do_mtc0_compare (void) +{ + cpu_mips_store_compare(env, T0); +} + +void do_mtc0_status (void) +{ + uint32_t val, old; + uint32_t mask = env->CP0_Status_rw_bitmask; + + val = T0 & mask; + old = env->CP0_Status; + env->CP0_Status = (env->CP0_Status & ~mask) | val; + compute_hflags(env); + if (loglevel & CPU_LOG_EXEC) + do_mtc0_status_debug(old, val); + cpu_mips_update_irq(env); +} + +void do_mttc0_status(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t tcstatus = env->CP0_TCStatus[other_tc]; + + env->CP0_Status = T0 & ~0xf1000018; + tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0)); + tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); + tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); + env->CP0_TCStatus[other_tc] = tcstatus; +} + +void do_mtc0_intctl (void) +{ + /* vectored interrupts not implemented, no performance counters. */ + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0); +} + +void do_mtc0_srsctl (void) +{ + uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); + env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask); +} + +void do_mtc0_cause (void) +{ + uint32_t mask = 0x00C00300; + uint32_t old = env->CP0_Cause; + + if (env->insn_flags & ISA_MIPS32R2) + mask |= 1 << CP0Ca_DC; + + env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) + cpu_mips_stop_count(env); + else + cpu_mips_start_count(env); + } + + /* Handle the software interrupt as an hardware one, as they + are very similar */ + if (T0 & CP0Ca_IP_mask) { + cpu_mips_update_irq(env); + } +} + +void do_mtc0_ebase (void) +{ + /* vectored interrupts not implemented */ + /* Multi-CPU not implemented */ + env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); +} + +void do_mtc0_config0 (void) +{ + env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007); +} + +void do_mtc0_config2 (void) +{ + /* tertiary/secondary caches not implemented */ + env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF); +} + +void do_mtc0_watchlo (uint32_t sel) +{ + /* Watch exceptions for instructions, data loads, data stores + not implemented. */ + env->CP0_WatchLo[sel] = (T0 & ~0x7); +} + +void do_mtc0_watchhi (uint32_t sel) +{ + env->CP0_WatchHi[sel] = (T0 & 0x40FF0FF8); + env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & T0 & 0x7); +} + +void do_mtc0_xcontext (void) +{ + target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; + env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask); +} + +void do_mtc0_framemask (void) +{ + env->CP0_Framemask = T0; /* XXX */ +} + +void do_mtc0_debug (void) +{ + env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); + if (T0 & (1 << CP0DB_DM)) + env->hflags |= MIPS_HFLAG_DM; + else + env->hflags &= ~MIPS_HFLAG_DM; +} + +void do_mttc0_debug(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + /* XXX: Might be wrong, check with EJTAG spec. */ + env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); + env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | + (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); +} + +void do_mtc0_performance0 (void) +{ + env->CP0_Performance0 = T0 & 0x000007ff; +} + +void do_mtc0_taglo (void) +{ + env->CP0_TagLo = T0 & 0xFFFFFCF6; +} + +void do_mtc0_datalo (void) +{ + env->CP0_DataLo = T0; /* XXX */ +} + +void do_mtc0_taghi (void) +{ + env->CP0_TagHi = T0; /* XXX */ +} + +void do_mtc0_datahi (void) +{ + env->CP0_DataHi = T0; /* XXX */ +} + void do_mtc0_status_debug(uint32_t old, uint32_t val) { fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x", @@ -388,7 +1034,144 @@ void do_mtc0_status_irqraise_debug(void) { fprintf(logfile, "Raise pending IRQs\n"); } +#endif /* !CONFIG_USER_ONLY */ + +/* MIPS MT functions */ +void do_mftgpr(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->gpr[other_tc][sel]; +} + +void do_mftlo(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->LO[other_tc][sel]; +} + +void do_mfthi(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->HI[other_tc][sel]; +} + +void do_mftacx(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->ACX[other_tc][sel]; +} + +void do_mftdsp(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->DSPControl[other_tc]; +} +void do_mttgpr(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->gpr[other_tc][sel]; +} + +void do_mttlo(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->LO[other_tc][sel]; +} + +void do_mtthi(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->HI[other_tc][sel]; +} + +void do_mttacx(uint32_t sel) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->ACX[other_tc][sel]; +} + +void do_mttdsp(void) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + T0 = env->DSPControl[other_tc]; +} + +/* MIPS MT functions */ +void do_dmt(void) +{ + // TODO + T0 = 0; + // rt = T0 +} + +void do_emt(void) +{ + // TODO + T0 = 0; + // rt = T0 +} + +void do_dvpe(void) +{ + // TODO + T0 = 0; + // rt = T0 +} + +void do_evpe(void) +{ + // TODO + T0 = 0; + // rt = T0 +} + +void do_fork(void) +{ + // T0 = rt, T1 = rs + T0 = 0; + // TODO: store to TC register +} + +void do_yield(void) +{ + if (T0 < 0) { + /* No scheduling policy implemented. */ + if (T0 != -2) { + if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && + env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) { + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; + do_raise_exception(EXCP_THREAD); + } + } + } else if (T0 == 0) { + if (0 /* TODO: TC underflow */) { + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + do_raise_exception(EXCP_THREAD); + } else { + // TODO: Deallocate TC + } + } else if (T0 > 0) { + /* Yield qualifier inputs not implemented. */ + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; + do_raise_exception(EXCP_THREAD); + } + T0 = env->CP0_YQMask; +} + +/* CP1 functions */ void fpu_handle_exception(void) { #ifdef CONFIG_SOFTFLOAT @@ -426,6 +1209,7 @@ void fpu_handle_exception(void) #endif } +#ifndef CONFIG_USER_ONLY /* TLB management */ void cpu_mips_tlb_flush (CPUState *env, int flush_global) { @@ -679,7 +1463,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, else do_raise_exception(EXCP_DBE); } -#endif +#endif /* !CONFIG_USER_ONLY */ /* Complex FPU operations which may need stack space. */ @@ -703,7 +1487,7 @@ unsigned int ieee_rm[] = { #define RESTORE_ROUNDING_MODE \ set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status) -void do_cfc1 (int reg) +void do_cfc1 (uint32_t reg) { switch (reg) { case 0: @@ -724,7 +1508,7 @@ void do_cfc1 (int reg) } } -void do_ctc1 (int reg) +void do_ctc1 (uint32_t reg) { switch(reg) { case 25: diff --git a/target-mips/translate.c b/target-mips/translate.c index e6b3f547c5..c744c9afb5 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -2583,6 +2583,7 @@ fail: } /* CP0 (MMU and control) */ +#ifndef CONFIG_USER_ONLY static inline void gen_mfc0_load32 (TCGv t, target_ulong off) { TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); @@ -2601,6 +2602,24 @@ static inline void gen_mfc0_load64 (TCGv t, target_ulong off) tcg_temp_free(r_tmp); } +static inline void gen_mtc0_store32 (TCGv t, target_ulong off) +{ + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); + + tcg_gen_trunc_tl_i32(r_tmp, t); + tcg_gen_st_i32(r_tmp, cpu_env, off); + tcg_temp_free(r_tmp); +} + +static inline void gen_mtc0_store64 (TCGv t, target_ulong off) +{ + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I64); + + tcg_gen_ext_tl_i64(r_tmp, t); + tcg_gen_st_i64(r_tmp, cpu_env, off); + tcg_temp_free(r_tmp); +} + static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) { const char *rn = "invalid"; @@ -2617,17 +2636,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_mvpcontrol(); + tcg_gen_helper_0_0(do_mfc0_mvpcontrol); rn = "MVPControl"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_mvpconf0(); + tcg_gen_helper_0_0(do_mfc0_mvpconf0); rn = "MVPConf0"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_mvpconf1(); + tcg_gen_helper_0_0(do_mfc0_mvpconf1); rn = "MVPConf1"; break; default: @@ -2637,7 +2656,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 1: switch (sel) { case 0: - gen_op_mfc0_random(); + tcg_gen_helper_0_0(do_mfc0_random); rn = "Random"; break; case 1: @@ -2688,37 +2707,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tcstatus(); + tcg_gen_helper_0_0(do_mfc0_tcstatus); rn = "TCStatus"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tcbind(); + tcg_gen_helper_0_0(do_mfc0_tcbind); rn = "TCBind"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tcrestart(); + tcg_gen_helper_0_0(do_mfc0_tcrestart); rn = "TCRestart"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tchalt(); + tcg_gen_helper_0_0(do_mfc0_tchalt); rn = "TCHalt"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tccontext(); + tcg_gen_helper_0_0(do_mfc0_tccontext); rn = "TCContext"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tcschedule(); + tcg_gen_helper_0_0(do_mfc0_tcschedule); rn = "TCSchedule"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tcschefback(); + tcg_gen_helper_0_0(do_mfc0_tcschefback); rn = "TCScheFBack"; break; default: @@ -2744,7 +2763,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) rn = "Context"; break; case 1: -// gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */ +// tcg_gen_helper_0_0(do_mfc0_contextconfig); /* SmartMIPS ASE */ rn = "ContextConfig"; // break; default: @@ -2826,7 +2845,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 9: switch (sel) { case 0: - gen_op_mfc0_count(); + tcg_gen_helper_0_0(do_mfc0_count); rn = "Count"; break; /* 6,7 are implementation dependent */ @@ -2952,7 +2971,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 17: switch (sel) { case 0: - gen_op_mfc0_lladdr(); + tcg_gen_helper_0_0(do_mfc0_lladdr); rn = "LLAddr"; break; default: @@ -2962,7 +2981,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 18: switch (sel) { case 0 ... 7: - gen_op_mfc0_watchlo(sel); + tcg_gen_helper_0_1i(do_mfc0_watchlo, sel); rn = "WatchLo"; break; default: @@ -2972,7 +2991,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 19: switch (sel) { case 0 ...7: - gen_op_mfc0_watchhi(sel); + tcg_gen_helper_0_1i(do_mfc0_watchhi, sel); rn = "WatchHi"; break; default: @@ -3011,23 +3030,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 23: switch (sel) { case 0: - gen_op_mfc0_debug(); /* EJTAG support */ + tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */ rn = "Debug"; break; case 1: -// gen_op_mfc0_tracecontrol(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mfc0_tracecontrol); /* PDtrace support */ rn = "TraceControl"; // break; case 2: -// gen_op_mfc0_tracecontrol2(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mfc0_tracecontrol2); /* PDtrace support */ rn = "TraceControl2"; // break; case 3: -// gen_op_mfc0_usertracedata(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mfc0_usertracedata); /* PDtrace support */ rn = "UserTraceData"; // break; case 4: -// gen_op_mfc0_debug(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mfc0_debug); /* PDtrace support */ rn = "TraceBPC"; // break; default: @@ -3053,31 +3072,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) rn = "Performance0"; break; case 1: -// gen_op_mfc0_performance1(); +// tcg_gen_helper_0_0(do_mfc0_performance1); rn = "Performance1"; // break; case 2: -// gen_op_mfc0_performance2(); +// tcg_gen_helper_0_0(do_mfc0_performance2); rn = "Performance2"; // break; case 3: -// gen_op_mfc0_performance3(); +// tcg_gen_helper_0_0(do_mfc0_performance3); rn = "Performance3"; // break; case 4: -// gen_op_mfc0_performance4(); +// tcg_gen_helper_0_0(do_mfc0_performance4); rn = "Performance4"; // break; case 5: -// gen_op_mfc0_performance5(); +// tcg_gen_helper_0_0(do_mfc0_performance5); rn = "Performance5"; // break; case 6: -// gen_op_mfc0_performance6(); +// tcg_gen_helper_0_0(do_mfc0_performance6); rn = "Performance6"; // break; case 7: -// gen_op_mfc0_performance7(); +// tcg_gen_helper_0_0(do_mfc0_performance7); rn = "Performance7"; // break; default: @@ -3191,12 +3210,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 0: switch (sel) { case 0: - gen_op_mtc0_index(); + tcg_gen_helper_0_0(do_mtc0_index); rn = "Index"; break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_mvpcontrol(); + tcg_gen_helper_0_0(do_mtc0_mvpcontrol); rn = "MVPControl"; break; case 2: @@ -3221,37 +3240,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpecontrol(); + tcg_gen_helper_0_0(do_mtc0_vpecontrol); rn = "VPEControl"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeconf0(); + tcg_gen_helper_0_0(do_mtc0_vpeconf0); rn = "VPEConf0"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeconf1(); + tcg_gen_helper_0_0(do_mtc0_vpeconf1); rn = "VPEConf1"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_yqmask(); + tcg_gen_helper_0_0(do_mtc0_yqmask); rn = "YQMask"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeschedule(); + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeschefback(); + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeopt(); + tcg_gen_helper_0_0(do_mtc0_vpeopt); rn = "VPEOpt"; break; default: @@ -3261,42 +3280,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 2: switch (sel) { case 0: - gen_op_mtc0_entrylo0(); + tcg_gen_helper_0_0(do_mtc0_entrylo0); rn = "EntryLo0"; break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcstatus(); + tcg_gen_helper_0_0(do_mtc0_tcstatus); rn = "TCStatus"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcbind(); + tcg_gen_helper_0_0(do_mtc0_tcbind); rn = "TCBind"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcrestart(); + tcg_gen_helper_0_0(do_mtc0_tcrestart); rn = "TCRestart"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tchalt(); + tcg_gen_helper_0_0(do_mtc0_tchalt); rn = "TCHalt"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tccontext(); + tcg_gen_helper_0_0(do_mtc0_tccontext); rn = "TCContext"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcschedule(); + tcg_gen_helper_0_0(do_mtc0_tcschedule); rn = "TCSchedule"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcschefback(); + tcg_gen_helper_0_0(do_mtc0_tcschefback); rn = "TCScheFBack"; break; default: @@ -3306,7 +3325,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 3: switch (sel) { case 0: - gen_op_mtc0_entrylo1(); + tcg_gen_helper_0_0(do_mtc0_entrylo1); rn = "EntryLo1"; break; default: @@ -3316,11 +3335,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 4: switch (sel) { case 0: - gen_op_mtc0_context(); + tcg_gen_helper_0_0(do_mtc0_context); rn = "Context"; break; case 1: -// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */ +// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */ rn = "ContextConfig"; // break; default: @@ -3330,12 +3349,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 5: switch (sel) { case 0: - gen_op_mtc0_pagemask(); + tcg_gen_helper_0_0(do_mtc0_pagemask); rn = "PageMask"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_pagegrain(); + tcg_gen_helper_0_0(do_mtc0_pagegrain); rn = "PageGrain"; break; default: @@ -3345,32 +3364,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 6: switch (sel) { case 0: - gen_op_mtc0_wired(); + tcg_gen_helper_0_0(do_mtc0_wired); rn = "Wired"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf0(); + tcg_gen_helper_0_0(do_mtc0_srsconf0); rn = "SRSConf0"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf1(); + tcg_gen_helper_0_0(do_mtc0_srsconf1); rn = "SRSConf1"; break; case 3: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf2(); + tcg_gen_helper_0_0(do_mtc0_srsconf2); rn = "SRSConf2"; break; case 4: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf3(); + tcg_gen_helper_0_0(do_mtc0_srsconf3); rn = "SRSConf3"; break; case 5: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf4(); + tcg_gen_helper_0_0(do_mtc0_srsconf4); rn = "SRSConf4"; break; default: @@ -3381,7 +3400,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) switch (sel) { case 0: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_hwrena(); + tcg_gen_helper_0_0(do_mtc0_hwrena); rn = "HWREna"; break; default: @@ -3395,7 +3414,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 9: switch (sel) { case 0: - gen_op_mtc0_count(); + tcg_gen_helper_0_0(do_mtc0_count); rn = "Count"; break; /* 6,7 are implementation dependent */ @@ -3408,7 +3427,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 10: switch (sel) { case 0: - gen_op_mtc0_entryhi(); + tcg_gen_helper_0_0(do_mtc0_entryhi); rn = "EntryHi"; break; default: @@ -3418,7 +3437,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 11: switch (sel) { case 0: - gen_op_mtc0_compare(); + tcg_gen_helper_0_0(do_mtc0_compare); rn = "Compare"; break; /* 6,7 are implementation dependent */ @@ -3431,7 +3450,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 12: switch (sel) { case 0: - gen_op_mtc0_status(); + tcg_gen_helper_0_0(do_mtc0_status); /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; @@ -3439,21 +3458,21 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_intctl(); + tcg_gen_helper_0_0(do_mtc0_intctl); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsctl(); + tcg_gen_helper_0_0(do_mtc0_srsctl); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSCtl"; break; case 3: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsmap(); + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSMap"; @@ -3465,7 +3484,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 13: switch (sel) { case 0: - gen_op_mtc0_cause(); + tcg_gen_helper_0_0(do_mtc0_cause); rn = "Cause"; break; default: @@ -3477,7 +3496,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 14: switch (sel) { case 0: - gen_op_mtc0_epc(); + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_EPC)); rn = "EPC"; break; default: @@ -3492,7 +3511,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_ebase(); + tcg_gen_helper_0_0(do_mtc0_ebase); rn = "EBase"; break; default: @@ -3502,7 +3521,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 16: switch (sel) { case 0: - gen_op_mtc0_config0(); + tcg_gen_helper_0_0(do_mtc0_config0); rn = "Config"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -3512,7 +3531,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) rn = "Config1"; break; case 2: - gen_op_mtc0_config2(); + tcg_gen_helper_0_0(do_mtc0_config2); rn = "Config2"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -3549,7 +3568,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 18: switch (sel) { case 0 ... 7: - gen_op_mtc0_watchlo(sel); + tcg_gen_helper_0_1i(do_mtc0_watchlo, sel); rn = "WatchLo"; break; default: @@ -3559,7 +3578,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 19: switch (sel) { case 0 ... 7: - gen_op_mtc0_watchhi(sel); + tcg_gen_helper_0_1i(do_mtc0_watchhi, sel); rn = "WatchHi"; break; default: @@ -3571,7 +3590,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 0: #if defined(TARGET_MIPS64) check_insn(env, ctx, ISA_MIPS3); - gen_op_mtc0_xcontext(); + tcg_gen_helper_0_0(do_mtc0_xcontext); rn = "XContext"; break; #endif @@ -3583,7 +3602,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) /* Officially reserved, but sel 0 is used for R1x000 framemask */ switch (sel) { case 0: - gen_op_mtc0_framemask(); + tcg_gen_helper_0_0(do_mtc0_framemask); rn = "Framemask"; break; default: @@ -3597,20 +3616,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 23: switch (sel) { case 0: - gen_op_mtc0_debug(); /* EJTAG support */ + tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */ /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; rn = "Debug"; break; case 1: -// gen_op_mtc0_tracecontrol(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */ rn = "TraceControl"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; // break; case 2: -// gen_op_mtc0_tracecontrol2(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */ rn = "TraceControl2"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -3618,13 +3637,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 3: /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; -// gen_op_mtc0_usertracedata(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */ rn = "UserTraceData"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; // break; case 4: -// gen_op_mtc0_debug(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceBPC"; @@ -3636,7 +3655,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 24: switch (sel) { case 0: - gen_op_mtc0_depc(); /* EJTAG support */ + /* EJTAG support */ + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_DEPC)); rn = "DEPC"; break; default: @@ -3646,35 +3666,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 25: switch (sel) { case 0: - gen_op_mtc0_performance0(); + tcg_gen_helper_0_0(do_mtc0_performance0); rn = "Performance0"; break; case 1: -// gen_op_mtc0_performance1(); +// tcg_gen_helper_0_0(do_mtc0_performance1); rn = "Performance1"; // break; case 2: -// gen_op_mtc0_performance2(); +// tcg_gen_helper_0_0(do_mtc0_performance2); rn = "Performance2"; // break; case 3: -// gen_op_mtc0_performance3(); +// tcg_gen_helper_0_0(do_mtc0_performance3); rn = "Performance3"; // break; case 4: -// gen_op_mtc0_performance4(); +// tcg_gen_helper_0_0(do_mtc0_performance4); rn = "Performance4"; // break; case 5: -// gen_op_mtc0_performance5(); +// tcg_gen_helper_0_0(do_mtc0_performance5); rn = "Performance5"; // break; case 6: -// gen_op_mtc0_performance6(); +// tcg_gen_helper_0_0(do_mtc0_performance6); rn = "Performance6"; // break; case 7: -// gen_op_mtc0_performance7(); +// tcg_gen_helper_0_0(do_mtc0_performance7); rn = "Performance7"; // break; default: @@ -3701,14 +3721,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 2: case 4: case 6: - gen_op_mtc0_taglo(); + tcg_gen_helper_0_0(do_mtc0_taglo); rn = "TagLo"; break; case 1: case 3: case 5: case 7: - gen_op_mtc0_datalo(); + tcg_gen_helper_0_0(do_mtc0_datalo); rn = "DataLo"; break; default: @@ -3721,14 +3741,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 2: case 4: case 6: - gen_op_mtc0_taghi(); + tcg_gen_helper_0_0(do_mtc0_taghi); rn = "TagHi"; break; case 1: case 3: case 5: case 7: - gen_op_mtc0_datahi(); + tcg_gen_helper_0_0(do_mtc0_datahi); rn = "DataHi"; break; default: @@ -3739,7 +3759,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 30: switch (sel) { case 0: - gen_op_mtc0_errorepc(); + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_ErrorEPC)); rn = "ErrorEPC"; break; default: @@ -3749,7 +3769,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 31: switch (sel) { case 0: - gen_op_mtc0_desave(); /* EJTAG support */ + /* EJTAG support */ + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE)); rn = "DESAVE"; break; default: @@ -3796,17 +3817,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_mvpcontrol(); + tcg_gen_helper_0_0(do_mfc0_mvpcontrol); rn = "MVPControl"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_mvpconf0(); + tcg_gen_helper_0_0(do_mfc0_mvpconf0); rn = "MVPConf0"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_mvpconf1(); + tcg_gen_helper_0_0(do_mfc0_mvpconf1); rn = "MVPConf1"; break; default: @@ -3816,7 +3837,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 1: switch (sel) { case 0: - gen_op_mfc0_random(); + tcg_gen_helper_0_0(do_mfc0_random); rn = "Random"; break; case 1: @@ -3866,37 +3887,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tcstatus(); + tcg_gen_helper_0_0(do_mfc0_tcstatus); rn = "TCStatus"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_op_mfc0_tcbind(); + tcg_gen_helper_0_0(do_mfc0_tcbind); rn = "TCBind"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_op_dmfc0_tcrestart(); + tcg_gen_helper_0_0(do_dmfc0_tcrestart); rn = "TCRestart"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_op_dmfc0_tchalt(); + tcg_gen_helper_0_0(do_dmfc0_tchalt); rn = "TCHalt"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_op_dmfc0_tccontext(); + tcg_gen_helper_0_0(do_dmfc0_tccontext); rn = "TCContext"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_op_dmfc0_tcschedule(); + tcg_gen_helper_0_0(do_dmfc0_tcschedule); rn = "TCSchedule"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_op_dmfc0_tcschefback(); + tcg_gen_helper_0_0(do_dmfc0_tcschefback); rn = "TCScheFBack"; break; default: @@ -3920,7 +3941,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) rn = "Context"; break; case 1: -// gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */ +// tcg_gen_helper_0_0(do_dmfc0_contextconfig); /* SmartMIPS ASE */ rn = "ContextConfig"; // break; default: @@ -4001,7 +4022,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 9: switch (sel) { case 0: - gen_op_mfc0_count(); + tcg_gen_helper_0_0(do_mfc0_count); rn = "Count"; break; /* 6,7 are implementation dependent */ @@ -4124,7 +4145,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 17: switch (sel) { case 0: - gen_op_dmfc0_lladdr(); + tcg_gen_helper_0_0(do_dmfc0_lladdr); rn = "LLAddr"; break; default: @@ -4134,7 +4155,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 18: switch (sel) { case 0 ... 7: - gen_op_dmfc0_watchlo(sel); + tcg_gen_helper_0_1i(do_dmfc0_watchlo, sel); rn = "WatchLo"; break; default: @@ -4144,7 +4165,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 19: switch (sel) { case 0 ... 7: - gen_op_mfc0_watchhi(sel); + tcg_gen_helper_0_1i(do_mfc0_watchhi, sel); rn = "WatchHi"; break; default: @@ -4180,23 +4201,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 23: switch (sel) { case 0: - gen_op_mfc0_debug(); /* EJTAG support */ + tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */ rn = "Debug"; break; case 1: -// gen_op_dmfc0_tracecontrol(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_dmfc0_tracecontrol); /* PDtrace support */ rn = "TraceControl"; // break; case 2: -// gen_op_dmfc0_tracecontrol2(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_dmfc0_tracecontrol2); /* PDtrace support */ rn = "TraceControl2"; // break; case 3: -// gen_op_dmfc0_usertracedata(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_dmfc0_usertracedata); /* PDtrace support */ rn = "UserTraceData"; // break; case 4: -// gen_op_dmfc0_debug(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_dmfc0_debug); /* PDtrace support */ rn = "TraceBPC"; // break; default: @@ -4221,31 +4242,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) rn = "Performance0"; break; case 1: -// gen_op_dmfc0_performance1(); +// tcg_gen_helper_0_0(do_dmfc0_performance1); rn = "Performance1"; // break; case 2: -// gen_op_dmfc0_performance2(); +// tcg_gen_helper_0_0(do_dmfc0_performance2); rn = "Performance2"; // break; case 3: -// gen_op_dmfc0_performance3(); +// tcg_gen_helper_0_0(do_dmfc0_performance3); rn = "Performance3"; // break; case 4: -// gen_op_dmfc0_performance4(); +// tcg_gen_helper_0_0(do_dmfc0_performance4); rn = "Performance4"; // break; case 5: -// gen_op_dmfc0_performance5(); +// tcg_gen_helper_0_0(do_dmfc0_performance5); rn = "Performance5"; // break; case 6: -// gen_op_dmfc0_performance6(); +// tcg_gen_helper_0_0(do_dmfc0_performance6); rn = "Performance6"; // break; case 7: -// gen_op_dmfc0_performance7(); +// tcg_gen_helper_0_0(do_dmfc0_performance7); rn = "Performance7"; // break; default: @@ -4358,12 +4379,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 0: switch (sel) { case 0: - gen_op_mtc0_index(); + tcg_gen_helper_0_0(do_mtc0_index); rn = "Index"; break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_mvpcontrol(); + tcg_gen_helper_0_0(do_mtc0_mvpcontrol); rn = "MVPControl"; break; case 2: @@ -4388,37 +4409,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpecontrol(); + tcg_gen_helper_0_0(do_mtc0_vpecontrol); rn = "VPEControl"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeconf0(); + tcg_gen_helper_0_0(do_mtc0_vpeconf0); rn = "VPEConf0"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeconf1(); + tcg_gen_helper_0_0(do_mtc0_vpeconf1); rn = "VPEConf1"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_yqmask(); + tcg_gen_helper_0_0(do_mtc0_yqmask); rn = "YQMask"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeschedule(); + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeschefback(); + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_vpeopt(); + tcg_gen_helper_0_0(do_mtc0_vpeopt); rn = "VPEOpt"; break; default: @@ -4428,42 +4449,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 2: switch (sel) { case 0: - gen_op_mtc0_entrylo0(); + tcg_gen_helper_0_0(do_mtc0_entrylo0); rn = "EntryLo0"; break; case 1: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcstatus(); + tcg_gen_helper_0_0(do_mtc0_tcstatus); rn = "TCStatus"; break; case 2: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcbind(); + tcg_gen_helper_0_0(do_mtc0_tcbind); rn = "TCBind"; break; case 3: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcrestart(); + tcg_gen_helper_0_0(do_mtc0_tcrestart); rn = "TCRestart"; break; case 4: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tchalt(); + tcg_gen_helper_0_0(do_mtc0_tchalt); rn = "TCHalt"; break; case 5: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tccontext(); + tcg_gen_helper_0_0(do_mtc0_tccontext); rn = "TCContext"; break; case 6: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcschedule(); + tcg_gen_helper_0_0(do_mtc0_tcschedule); rn = "TCSchedule"; break; case 7: check_insn(env, ctx, ASE_MT); - gen_op_mtc0_tcschefback(); + tcg_gen_helper_0_0(do_mtc0_tcschefback); rn = "TCScheFBack"; break; default: @@ -4473,7 +4494,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 3: switch (sel) { case 0: - gen_op_mtc0_entrylo1(); + tcg_gen_helper_0_0(do_mtc0_entrylo1); rn = "EntryLo1"; break; default: @@ -4483,11 +4504,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 4: switch (sel) { case 0: - gen_op_mtc0_context(); + tcg_gen_helper_0_0(do_mtc0_context); rn = "Context"; break; case 1: -// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */ +// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */ rn = "ContextConfig"; // break; default: @@ -4497,12 +4518,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 5: switch (sel) { case 0: - gen_op_mtc0_pagemask(); + tcg_gen_helper_0_0(do_mtc0_pagemask); rn = "PageMask"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_pagegrain(); + tcg_gen_helper_0_0(do_mtc0_pagegrain); rn = "PageGrain"; break; default: @@ -4512,32 +4533,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 6: switch (sel) { case 0: - gen_op_mtc0_wired(); + tcg_gen_helper_0_0(do_mtc0_wired); rn = "Wired"; break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf0(); + tcg_gen_helper_0_0(do_mtc0_srsconf0); rn = "SRSConf0"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf1(); + tcg_gen_helper_0_0(do_mtc0_srsconf1); rn = "SRSConf1"; break; case 3: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf2(); + tcg_gen_helper_0_0(do_mtc0_srsconf2); rn = "SRSConf2"; break; case 4: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf3(); + tcg_gen_helper_0_0(do_mtc0_srsconf3); rn = "SRSConf3"; break; case 5: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsconf4(); + tcg_gen_helper_0_0(do_mtc0_srsconf4); rn = "SRSConf4"; break; default: @@ -4548,7 +4569,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) switch (sel) { case 0: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_hwrena(); + tcg_gen_helper_0_0(do_mtc0_hwrena); rn = "HWREna"; break; default: @@ -4562,7 +4583,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 9: switch (sel) { case 0: - gen_op_mtc0_count(); + tcg_gen_helper_0_0(do_mtc0_count); rn = "Count"; break; /* 6,7 are implementation dependent */ @@ -4575,7 +4596,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 10: switch (sel) { case 0: - gen_op_mtc0_entryhi(); + tcg_gen_helper_0_0(do_mtc0_entryhi); rn = "EntryHi"; break; default: @@ -4585,7 +4606,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 11: switch (sel) { case 0: - gen_op_mtc0_compare(); + tcg_gen_helper_0_0(do_mtc0_compare); rn = "Compare"; break; /* 6,7 are implementation dependent */ @@ -4598,7 +4619,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 12: switch (sel) { case 0: - gen_op_mtc0_status(); + tcg_gen_helper_0_0(do_mtc0_status); /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; @@ -4606,21 +4627,21 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_intctl(); + tcg_gen_helper_0_0(do_mtc0_intctl); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsctl(); + tcg_gen_helper_0_0(do_mtc0_srsctl); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSCtl"; break; case 3: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_srsmap(); + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap)); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "SRSMap"; @@ -4632,7 +4653,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 13: switch (sel) { case 0: - gen_op_mtc0_cause(); + tcg_gen_helper_0_0(do_mtc0_cause); rn = "Cause"; break; default: @@ -4644,7 +4665,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 14: switch (sel) { case 0: - gen_op_mtc0_epc(); + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC)); rn = "EPC"; break; default: @@ -4659,7 +4680,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) break; case 1: check_insn(env, ctx, ISA_MIPS32R2); - gen_op_mtc0_ebase(); + tcg_gen_helper_0_0(do_mtc0_ebase); rn = "EBase"; break; default: @@ -4669,7 +4690,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 16: switch (sel) { case 0: - gen_op_mtc0_config0(); + tcg_gen_helper_0_0(do_mtc0_config0); rn = "Config"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -4679,7 +4700,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) rn = "Config1"; break; case 2: - gen_op_mtc0_config2(); + tcg_gen_helper_0_0(do_mtc0_config2); rn = "Config2"; /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -4707,7 +4728,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 18: switch (sel) { case 0 ... 7: - gen_op_mtc0_watchlo(sel); + tcg_gen_helper_0_1i(do_mtc0_watchlo, sel); rn = "WatchLo"; break; default: @@ -4717,7 +4738,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 19: switch (sel) { case 0 ... 7: - gen_op_mtc0_watchhi(sel); + tcg_gen_helper_0_1i(do_mtc0_watchhi, sel); rn = "WatchHi"; break; default: @@ -4728,7 +4749,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) switch (sel) { case 0: check_insn(env, ctx, ISA_MIPS3); - gen_op_mtc0_xcontext(); + tcg_gen_helper_0_0(do_mtc0_xcontext); rn = "XContext"; break; default: @@ -4739,7 +4760,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) /* Officially reserved, but sel 0 is used for R1x000 framemask */ switch (sel) { case 0: - gen_op_mtc0_framemask(); + tcg_gen_helper_0_0(do_mtc0_framemask); rn = "Framemask"; break; default: @@ -4753,32 +4774,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 23: switch (sel) { case 0: - gen_op_mtc0_debug(); /* EJTAG support */ + tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */ /* BS_STOP isn't good enough here, hflags may have changed. */ gen_save_pc(ctx->pc + 4); ctx->bstate = BS_EXCP; rn = "Debug"; break; case 1: -// gen_op_mtc0_tracecontrol(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceControl"; // break; case 2: -// gen_op_mtc0_tracecontrol2(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceControl2"; // break; case 3: -// gen_op_mtc0_usertracedata(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "UserTraceData"; // break; case 4: -// gen_op_mtc0_debug(); /* PDtrace support */ +// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */ /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; rn = "TraceBPC"; @@ -4790,7 +4811,8 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 24: switch (sel) { case 0: - gen_op_mtc0_depc(); /* EJTAG support */ + /* EJTAG support */ + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC)); rn = "DEPC"; break; default: @@ -4800,35 +4822,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 25: switch (sel) { case 0: - gen_op_mtc0_performance0(); + tcg_gen_helper_0_0(do_mtc0_performance0); rn = "Performance0"; break; case 1: -// gen_op_mtc0_performance1(); +// tcg_gen_helper_0_0(do_mtc0_performance1); rn = "Performance1"; // break; case 2: -// gen_op_mtc0_performance2(); +// tcg_gen_helper_0_0(do_mtc0_performance2); rn = "Performance2"; // break; case 3: -// gen_op_mtc0_performance3(); +// tcg_gen_helper_0_0(do_mtc0_performance3); rn = "Performance3"; // break; case 4: -// gen_op_mtc0_performance4(); +// tcg_gen_helper_0_0(do_mtc0_performance4); rn = "Performance4"; // break; case 5: -// gen_op_mtc0_performance5(); +// tcg_gen_helper_0_0(do_mtc0_performance5); rn = "Performance5"; // break; case 6: -// gen_op_mtc0_performance6(); +// tcg_gen_helper_0_0(do_mtc0_performance6); rn = "Performance6"; // break; case 7: -// gen_op_mtc0_performance7(); +// tcg_gen_helper_0_0(do_mtc0_performance7); rn = "Performance7"; // break; default: @@ -4855,14 +4877,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 2: case 4: case 6: - gen_op_mtc0_taglo(); + tcg_gen_helper_0_0(do_mtc0_taglo); rn = "TagLo"; break; case 1: case 3: case 5: case 7: - gen_op_mtc0_datalo(); + tcg_gen_helper_0_0(do_mtc0_datalo); rn = "DataLo"; break; default: @@ -4875,14 +4897,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 2: case 4: case 6: - gen_op_mtc0_taghi(); + tcg_gen_helper_0_0(do_mtc0_taghi); rn = "TagHi"; break; case 1: case 3: case 5: case 7: - gen_op_mtc0_datahi(); + tcg_gen_helper_0_0(do_mtc0_datahi); rn = "DataHi"; break; default: @@ -4893,7 +4915,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 30: switch (sel) { case 0: - gen_op_mtc0_errorepc(); + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC)); rn = "ErrorEPC"; break; default: @@ -4903,7 +4925,8 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) case 31: switch (sel) { case 0: - gen_op_mtc0_desave(); /* EJTAG support */ + /* EJTAG support */ + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE)); rn = "DESAVE"; break; default: @@ -4951,25 +4974,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, case 2: switch (sel) { case 1: - gen_op_mftc0_tcstatus(); + tcg_gen_helper_0_0(do_mftc0_tcstatus); break; case 2: - gen_op_mftc0_tcbind(); + tcg_gen_helper_0_0(do_mftc0_tcbind); break; case 3: - gen_op_mftc0_tcrestart(); + tcg_gen_helper_0_0(do_mftc0_tcrestart); break; case 4: - gen_op_mftc0_tchalt(); + tcg_gen_helper_0_0(do_mftc0_tchalt); break; case 5: - gen_op_mftc0_tccontext(); + tcg_gen_helper_0_0(do_mftc0_tccontext); break; case 6: - gen_op_mftc0_tcschedule(); + tcg_gen_helper_0_0(do_mftc0_tcschedule); break; case 7: - gen_op_mftc0_tcschefback(); + tcg_gen_helper_0_0(do_mftc0_tcschefback); break; default: gen_mfc0(env, ctx, rt, sel); @@ -4979,7 +5002,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, case 10: switch (sel) { case 0: - gen_op_mftc0_entryhi(); + tcg_gen_helper_0_0(do_mftc0_entryhi); break; default: gen_mfc0(env, ctx, rt, sel); @@ -4988,7 +5011,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, case 12: switch (sel) { case 0: - gen_op_mftc0_status(); + tcg_gen_helper_0_0(do_mftc0_status); break; default: gen_mfc0(env, ctx, rt, sel); @@ -4997,7 +5020,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, case 23: switch (sel) { case 0: - gen_op_mftc0_debug(); + tcg_gen_helper_0_0(do_mftc0_debug); break; default: gen_mfc0(env, ctx, rt, sel); @@ -5010,49 +5033,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, } else switch (sel) { /* GPR registers. */ case 0: - gen_op_mftgpr(rt); + tcg_gen_helper_0_1i(do_mftgpr, rt); break; /* Auxiliary CPU registers */ case 1: switch (rt) { case 0: - gen_op_mftlo(0); + tcg_gen_helper_0_1i(do_mftlo, 0); break; case 1: - gen_op_mfthi(0); + tcg_gen_helper_0_1i(do_mfthi, 0); break; case 2: - gen_op_mftacx(0); + tcg_gen_helper_0_1i(do_mftacx, 0); break; case 4: - gen_op_mftlo(1); + tcg_gen_helper_0_1i(do_mftlo, 1); break; case 5: - gen_op_mfthi(1); + tcg_gen_helper_0_1i(do_mfthi, 1); break; case 6: - gen_op_mftacx(1); + tcg_gen_helper_0_1i(do_mftacx, 1); break; case 8: - gen_op_mftlo(2); + tcg_gen_helper_0_1i(do_mftlo, 2); break; case 9: - gen_op_mfthi(2); + tcg_gen_helper_0_1i(do_mfthi, 2); break; case 10: - gen_op_mftacx(2); + tcg_gen_helper_0_1i(do_mftacx, 2); break; case 12: - gen_op_mftlo(3); + tcg_gen_helper_0_1i(do_mftlo, 3); break; case 13: - gen_op_mfthi(3); + tcg_gen_helper_0_1i(do_mfthi, 3); break; case 14: - gen_op_mftacx(3); + tcg_gen_helper_0_1i(do_mftacx, 3); break; case 16: - gen_op_mftdsp(); + tcg_gen_helper_0_0(do_mftdsp); break; default: goto die; @@ -5071,7 +5094,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, break; case 3: /* XXX: For now we support only a single FPU context. */ - gen_op_cfc1(rt); + tcg_gen_helper_0_1i(do_cfc1, rt); break; /* COP2: Not implemented. */ case 4: @@ -5115,25 +5138,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, case 2: switch (sel) { case 1: - gen_op_mttc0_tcstatus(); + tcg_gen_helper_0_0(do_mttc0_tcstatus); break; case 2: - gen_op_mttc0_tcbind(); + tcg_gen_helper_0_0(do_mttc0_tcbind); break; case 3: - gen_op_mttc0_tcrestart(); + tcg_gen_helper_0_0(do_mttc0_tcrestart); break; case 4: - gen_op_mttc0_tchalt(); + tcg_gen_helper_0_0(do_mttc0_tchalt); break; case 5: - gen_op_mttc0_tccontext(); + tcg_gen_helper_0_0(do_mttc0_tccontext); break; case 6: - gen_op_mttc0_tcschedule(); + tcg_gen_helper_0_0(do_mttc0_tcschedule); break; case 7: - gen_op_mttc0_tcschefback(); + tcg_gen_helper_0_0(do_mttc0_tcschefback); break; default: gen_mtc0(env, ctx, rd, sel); @@ -5143,7 +5166,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, case 10: switch (sel) { case 0: - gen_op_mttc0_entryhi(); + tcg_gen_helper_0_0(do_mttc0_entryhi); break; default: gen_mtc0(env, ctx, rd, sel); @@ -5152,7 +5175,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, case 12: switch (sel) { case 0: - gen_op_mttc0_status(); + tcg_gen_helper_0_0(do_mttc0_status); break; default: gen_mtc0(env, ctx, rd, sel); @@ -5161,7 +5184,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, case 23: switch (sel) { case 0: - gen_op_mttc0_debug(); + tcg_gen_helper_0_0(do_mttc0_debug); break; default: gen_mtc0(env, ctx, rd, sel); @@ -5174,49 +5197,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, } else switch (sel) { /* GPR registers. */ case 0: - gen_op_mttgpr(rd); + tcg_gen_helper_0_1i(do_mttgpr, rd); break; /* Auxiliary CPU registers */ case 1: switch (rd) { case 0: - gen_op_mttlo(0); + tcg_gen_helper_0_1i(do_mttlo, 0); break; case 1: - gen_op_mtthi(0); + tcg_gen_helper_0_1i(do_mtthi, 0); break; case 2: - gen_op_mttacx(0); + tcg_gen_helper_0_1i(do_mttacx, 0); break; case 4: - gen_op_mttlo(1); + tcg_gen_helper_0_1i(do_mttlo, 1); break; case 5: - gen_op_mtthi(1); + tcg_gen_helper_0_1i(do_mtthi, 1); break; case 6: - gen_op_mttacx(1); + tcg_gen_helper_0_1i(do_mttacx, 1); break; case 8: - gen_op_mttlo(2); + tcg_gen_helper_0_1i(do_mttlo, 2); break; case 9: - gen_op_mtthi(2); + tcg_gen_helper_0_1i(do_mtthi, 2); break; case 10: - gen_op_mttacx(2); + tcg_gen_helper_0_1i(do_mttacx, 2); break; case 12: - gen_op_mttlo(3); + tcg_gen_helper_0_1i(do_mttlo, 3); break; case 13: - gen_op_mtthi(3); + tcg_gen_helper_0_1i(do_mtthi, 3); break; case 14: - gen_op_mttacx(3); + tcg_gen_helper_0_1i(do_mttacx, 3); break; case 16: - gen_op_mttdsp(); + tcg_gen_helper_0_0(do_mttdsp); break; default: goto die; @@ -5235,7 +5258,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, break; case 3: /* XXX: For now we support only a single FPU context. */ - gen_op_ctc1(rd); + tcg_gen_helper_0_1i(do_ctc1, rd); break; /* COP2: Not implemented. */ case 4: @@ -5380,6 +5403,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int } MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); } +#endif /* !CONFIG_USER_ONLY */ /* CP1 Branches (before delay slot) */ static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, @@ -5464,13 +5488,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) opn = "mtc1"; break; case OPC_CFC1: - gen_op_cfc1(fs); + tcg_gen_helper_0_1i(do_cfc1, fs); gen_store_gpr(cpu_T[0], rt); opn = "cfc1"; break; case OPC_CTC1: gen_load_gpr(cpu_T[0], rt); - gen_op_ctc1(fs); + tcg_gen_helper_0_1i(do_ctc1, fs); opn = "ctc1"; break; case OPC_DMFC1: @@ -6846,12 +6870,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx) check_insn(env, ctx, ASE_MT); gen_load_gpr(cpu_T[0], rt); gen_load_gpr(cpu_T[1], rs); - gen_op_fork(); + tcg_gen_helper_0_0(do_fork); break; case OPC_YIELD: check_insn(env, ctx, ASE_MT); gen_load_gpr(cpu_T[0], rs); - gen_op_yield(); + tcg_gen_helper_0_0(do_yield); gen_store_gpr(cpu_T[0], rd); break; #if defined(TARGET_MIPS64) @@ -6921,29 +6945,33 @@ static void decode_opc (CPUState *env, DisasContext *ctx) case OPC_DMFC0: case OPC_DMTC0: #endif +#ifndef CONFIG_USER_ONLY gen_cp0(env, ctx, op1, rt, rd); +#endif break; case OPC_C0_FIRST ... OPC_C0_LAST: +#ifndef CONFIG_USER_ONLY gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); +#endif break; case OPC_MFMC0: op2 = MASK_MFMC0(ctx->opcode); switch (op2) { case OPC_DMT: check_insn(env, ctx, ASE_MT); - gen_op_dmt(); + tcg_gen_helper_0_0(do_dmt); break; case OPC_EMT: check_insn(env, ctx, ASE_MT); - gen_op_emt(); + tcg_gen_helper_0_0(do_emt); break; case OPC_DVPE: check_insn(env, ctx, ASE_MT); - gen_op_dvpe(); + tcg_gen_helper_0_0(do_dvpe); break; case OPC_EVPE: check_insn(env, ctx, ASE_MT); - gen_op_evpe(); + tcg_gen_helper_0_0(do_evpe); break; case OPC_DI: check_insn(env, ctx, ISA_MIPS32R2); |