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-rw-r--r--target-sparc/cpu.h5
-rw-r--r--target-sparc/op.c433
-rw-r--r--target-sparc/translate.c442
3 files changed, 427 insertions, 453 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 08366e8fc0..ae47a1ba1c 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -184,6 +184,11 @@ typedef struct CPUSPARCState {
target_ulong pc; /* program counter */
target_ulong npc; /* next program counter */
target_ulong y; /* multiply/divide register */
+
+ /* emulator internal flags handling */
+ target_ulong cc_src;
+ target_ulong cc_dst;
+
uint32_t psr; /* processor state register */
target_ulong fsr; /* FPU state register */
uint32_t cwp; /* index of current register window (extracted
diff --git a/target-sparc/op.c b/target-sparc/op.c
index e57a60d357..0c3e0902e6 100644
--- a/target-sparc/op.c
+++ b/target-sparc/op.c
@@ -171,389 +171,6 @@
#define FLAG_SET(x) ((env->psr&x)?1:0)
-void OPPROTO op_add_T1_T0_cc(void)
-{
- target_ulong src1;
-
- src1 = T0;
- T0 += T1;
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
- env->psr |= PSR_CARRY;
- if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
- ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
- env->psr |= PSR_OVF;
-
- env->xcc = 0;
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
- if (T0 < src1)
- env->xcc |= PSR_CARRY;
- if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
- env->xcc |= PSR_OVF;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (T0 < src1)
- env->psr |= PSR_CARRY;
- if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
- env->psr |= PSR_OVF;
-#endif
- FORCE_RET();
-}
-
-void OPPROTO op_addx_T1_T0_cc(void)
-{
- target_ulong src1;
- src1 = T0;
- if (FLAG_SET(PSR_CARRY))
- {
- T0 += T1 + 1;
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if ((T0 & 0xffffffff) <= (src1 & 0xffffffff))
- env->psr |= PSR_CARRY;
- env->xcc = 0;
- if (T0 <= src1)
- env->xcc |= PSR_CARRY;
-#else
- if (T0 <= src1)
- env->psr |= PSR_CARRY;
-#endif
- }
- else
- {
- T0 += T1;
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
- env->psr |= PSR_CARRY;
- env->xcc = 0;
- if (T0 < src1)
- env->xcc |= PSR_CARRY;
-#else
- if (T0 < src1)
- env->psr |= PSR_CARRY;
-#endif
- }
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
- ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
- env->psr |= PSR_OVF;
-
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
- if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
- env->xcc |= PSR_OVF;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
- env->psr |= PSR_OVF;
-#endif
- FORCE_RET();
-}
-
-void OPPROTO op_tadd_T1_T0_cc(void)
-{
- target_ulong src1;
-
- src1 = T0;
- T0 += T1;
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
- env->psr |= PSR_CARRY;
- if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
- ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
- env->psr |= PSR_OVF;
- if ((src1 & 0x03) || (T1 & 0x03))
- env->psr |= PSR_OVF;
-
- env->xcc = 0;
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
- if (T0 < src1)
- env->xcc |= PSR_CARRY;
- if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1ULL << 63))
- env->xcc |= PSR_OVF;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (T0 < src1)
- env->psr |= PSR_CARRY;
- if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
- env->psr |= PSR_OVF;
- if ((src1 & 0x03) || (T1 & 0x03))
- env->psr |= PSR_OVF;
-#endif
- FORCE_RET();
-}
-
-void OPPROTO op_tadd_T1_T0_ccTV(void)
-{
- target_ulong src1;
-
- if ((T0 & 0x03) || (T1 & 0x03)) {
- raise_exception(TT_TOVF);
- FORCE_RET();
- return;
- }
-
- src1 = T0;
- T0 += T1;
-
-#ifdef TARGET_SPARC64
- if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff) ^ -1) &
- ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
- raise_exception(TT_TOVF);
-#else
- if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
- raise_exception(TT_TOVF);
-#endif
-
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if ((T0 & 0xffffffff) < (src1 & 0xffffffff))
- env->psr |= PSR_CARRY;
-
- env->xcc = 0;
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
- if (T0 < src1)
- env->xcc |= PSR_CARRY;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (T0 < src1)
- env->psr |= PSR_CARRY;
-#endif
- FORCE_RET();
-}
-
-void OPPROTO op_sub_T1_T0_cc(void)
-{
- target_ulong src1;
-
- src1 = T0;
- T0 -= T1;
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
- env->psr |= PSR_CARRY;
- if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
- ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
- env->psr |= PSR_OVF;
-
- env->xcc = 0;
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
- if (src1 < T1)
- env->xcc |= PSR_CARRY;
- if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
- env->xcc |= PSR_OVF;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (src1 < T1)
- env->psr |= PSR_CARRY;
- if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
- env->psr |= PSR_OVF;
-#endif
- FORCE_RET();
-}
-
-void OPPROTO op_subx_T1_T0_cc(void)
-{
- target_ulong src1;
- src1 = T0;
- if (FLAG_SET(PSR_CARRY))
- {
- T0 -= T1 + 1;
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if ((src1 & 0xffffffff) <= (T1 & 0xffffffff))
- env->psr |= PSR_CARRY;
- env->xcc = 0;
- if (src1 <= T1)
- env->xcc |= PSR_CARRY;
-#else
- if (src1 <= T1)
- env->psr |= PSR_CARRY;
-#endif
- }
- else
- {
- T0 -= T1;
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
- env->psr |= PSR_CARRY;
- env->xcc = 0;
- if (src1 < T1)
- env->xcc |= PSR_CARRY;
-#else
- if (src1 < T1)
- env->psr |= PSR_CARRY;
-#endif
- }
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
- ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
- env->psr |= PSR_OVF;
-
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
- if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
- env->xcc |= PSR_OVF;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
- env->psr |= PSR_OVF;
-#endif
- FORCE_RET();
-}
-
-void OPPROTO op_tsub_T1_T0_cc(void)
-{
- target_ulong src1;
-
- src1 = T0;
- T0 -= T1;
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
- env->psr |= PSR_CARRY;
- if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
- ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
- env->psr |= PSR_OVF;
- if ((src1 & 0x03) || (T1 & 0x03))
- env->psr |= PSR_OVF;
-
- env->xcc = 0;
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
- if (src1 < T1)
- env->xcc |= PSR_CARRY;
- if (((src1 ^ T1) & (src1 ^ T0)) & (1ULL << 63))
- env->xcc |= PSR_OVF;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (src1 < T1)
- env->psr |= PSR_CARRY;
- if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
- env->psr |= PSR_OVF;
- if ((src1 & 0x03) || (T1 & 0x03))
- env->psr |= PSR_OVF;
-#endif
- FORCE_RET();
-}
-
-void OPPROTO op_tsub_T1_T0_ccTV(void)
-{
- target_ulong src1;
-
- if ((T0 & 0x03) || (T1 & 0x03))
- raise_exception(TT_TOVF);
-
- src1 = T0;
- T0 -= T1;
-
-#ifdef TARGET_SPARC64
- if ((((src1 & 0xffffffff) ^ (T1 & 0xffffffff)) &
- ((src1 & 0xffffffff) ^ (T0 & 0xffffffff))) & (1 << 31))
- raise_exception(TT_TOVF);
-#else
- if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
- raise_exception(TT_TOVF);
-#endif
-
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if ((src1 & 0xffffffff) < (T1 & 0xffffffff))
- env->psr |= PSR_CARRY;
-
- env->xcc = 0;
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
- if (src1 < T1)
- env->xcc |= PSR_CARRY;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (src1 < T1)
- env->psr |= PSR_CARRY;
-#endif
- FORCE_RET();
-}
-
void OPPROTO op_umul_T1_T0(void)
{
uint64_t res;
@@ -652,33 +269,6 @@ void OPPROTO op_sdiv_T1_T0(void)
FORCE_RET();
}
-void OPPROTO op_div_cc(void)
-{
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (T1)
- env->psr |= PSR_OVF;
-
- env->xcc = 0;
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
- if (T1)
- env->psr |= PSR_OVF;
-#endif
- FORCE_RET();
-}
-
#ifdef TARGET_SPARC64
void OPPROTO op_udivx_T1_T0(void)
{
@@ -702,29 +292,6 @@ void OPPROTO op_sdivx_T1_T0(void)
}
#endif
-void OPPROTO op_logic_T0_cc(void)
-{
- env->psr = 0;
-#ifdef TARGET_SPARC64
- if (!(T0 & 0xffffffff))
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
-
- env->xcc = 0;
- if (!T0)
- env->xcc |= PSR_ZERO;
- if ((int64_t) T0 < 0)
- env->xcc |= PSR_NEG;
-#else
- if (!T0)
- env->psr |= PSR_ZERO;
- if ((int32_t) T0 < 0)
- env->psr |= PSR_NEG;
-#endif
- FORCE_RET();
-}
-
/* Load and store */
#define MEMSUFFIX _raw
#include "op_mem.h"
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5d63894aa6..3225b8a152 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -46,7 +46,10 @@
according to jump_pc[T2] */
/* global register indexes */
-static TCGv cpu_env, cpu_T[3], cpu_regwptr;
+static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_dst, cpu_psr;
+#ifdef TARGET_SPARC64
+static TCGv cpu_xcc;
+#endif
/* local register indexes (only used inside old micro ops) */
static TCGv cpu_tmp0;
@@ -356,6 +359,407 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv src)
tcg_gen_andi_tl(reg, reg, 0x1);
}
+static inline void gen_op_exception(int exception)
+{
+ TCGv r_except;
+
+ r_except = tcg_temp_new(TCG_TYPE_I32);
+ tcg_gen_movi_i32(r_except, exception);
+ tcg_gen_helper_0_1(raise_exception, r_except);
+}
+
+static inline void gen_cc_clear(void)
+{
+ tcg_gen_movi_i32(cpu_psr, 0);
+#ifdef TARGET_SPARC64
+ tcg_gen_movi_i32(cpu_xcc, 0);
+#endif
+}
+
+/* old op:
+ if (!T0)
+ env->psr |= PSR_ZERO;
+ if ((int32_t) T0 < 0)
+ env->psr |= PSR_NEG;
+*/
+static inline void gen_cc_NZ(TCGv dst)
+{
+ int l1, l2;
+ TCGv r_zero;
+
+ l1 = gen_new_label();
+ l2 = gen_new_label();
+ r_zero = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_brcond_i32(TCG_COND_NE, dst, r_zero, l1);
+ tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
+ gen_set_label(l1);
+ tcg_gen_brcond_i32(TCG_COND_GE, dst, r_zero, l2);
+ tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
+ gen_set_label(l2);
+#ifdef TARGET_SPARC64
+ {
+ int l3, l4;
+
+ l3 = gen_new_label();
+ l4 = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_NE, dst, r_zero, l3);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
+ gen_set_label(l3);
+ tcg_gen_brcond_tl(TCG_COND_GE, dst, r_zero, l4);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
+ gen_set_label(l4);
+ }
+#endif
+}
+
+/* old op:
+ if (T0 < src1)
+ env->psr |= PSR_CARRY;
+*/
+static inline void gen_cc_C_add(TCGv dst, TCGv src1)
+{
+ int l1;
+
+ l1 = gen_new_label();
+ tcg_gen_brcond_i32(TCG_COND_GEU, dst, src1, l1);
+ tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
+ gen_set_label(l1);
+#ifdef TARGET_SPARC64
+ {
+ int l2;
+
+ l2 = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
+ gen_set_label(l2);
+ }
+#endif
+}
+
+/* old op:
+ if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+*/
+static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2)
+{
+ TCGv r_temp, r_temp2, r_temp3, r_zero;
+ int l1;
+
+ l1 = gen_new_label();
+
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ r_temp2 = tcg_temp_new(TCG_TYPE_TL);
+ r_temp3 = tcg_temp_new(TCG_TYPE_TL);
+ r_zero = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xori_tl(r_temp, r_temp, -1);
+ tcg_gen_xor_tl(r_temp2, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, r_temp2);
+ tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
+ tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
+ tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
+ gen_set_label(l1);
+#ifdef TARGET_SPARC64
+ {
+ int l2;
+
+ l2 = gen_new_label();
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xori_tl(r_temp, r_temp, -1);
+ tcg_gen_xor_tl(r_temp2, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, r_temp2);
+ tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
+ gen_set_label(l2);
+ }
+#endif
+}
+
+static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
+{
+ TCGv r_temp, r_temp2, r_temp3, r_zero;
+ int l1;
+
+ l1 = gen_new_label();
+
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ r_temp2 = tcg_temp_new(TCG_TYPE_TL);
+ r_temp3 = tcg_temp_new(TCG_TYPE_TL);
+ r_zero = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xori_tl(r_temp, r_temp, -1);
+ tcg_gen_xor_tl(r_temp2, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, r_temp2);
+ tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
+ tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
+ gen_op_exception(TT_TOVF);
+ gen_set_label(l1);
+#ifdef TARGET_SPARC64
+ {
+ int l2;
+
+ l2 = gen_new_label();
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xori_tl(r_temp, r_temp, -1);
+ tcg_gen_xor_tl(r_temp2, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, r_temp2);
+ tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
+ gen_op_exception(TT_TOVF);
+ gen_set_label(l2);
+ }
+#endif
+}
+
+static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
+{
+ int l1;
+ TCGv r_zero, r_temp;
+
+ l1 = gen_new_label();
+ r_zero = tcg_temp_new(TCG_TYPE_TL);
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_or_tl(r_temp, src1, src2);
+ tcg_gen_andi_tl(r_temp, r_temp, 0x3);
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
+ tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
+ gen_set_label(l1);
+}
+
+static inline void gen_tag_tv(TCGv src1, TCGv src2)
+{
+ int l1;
+ TCGv r_zero, r_temp;
+
+ l1 = gen_new_label();
+ r_zero = tcg_temp_new(TCG_TYPE_TL);
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_or_tl(r_temp, src1, src2);
+ tcg_gen_andi_tl(r_temp, r_temp, 0x3);
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, r_zero, l1);
+ gen_op_exception(TT_TOVF);
+ gen_set_label(l1);
+}
+
+static inline void gen_op_add_T1_T0_cc(void)
+{
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_cc_clear();
+ gen_cc_NZ(cpu_T[0]);
+ gen_cc_C_add(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
+}
+
+static inline void gen_op_addx_T1_T0_cc(void)
+{
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
+ gen_cc_clear();
+ gen_cc_C_add(cpu_T[0], cpu_cc_src);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_cc_C_add(cpu_T[0], cpu_cc_src);
+ gen_cc_NZ(cpu_T[0]);
+ gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
+}
+
+static inline void gen_op_tadd_T1_T0_cc(void)
+{
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_cc_clear();
+ gen_cc_NZ(cpu_T[0]);
+ gen_cc_C_add(cpu_T[0], cpu_cc_src);
+ gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
+}
+
+static inline void gen_op_tadd_T1_T0_ccTV(void)
+{
+ gen_tag_tv(cpu_T[0], cpu_T[1]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_clear();
+ gen_cc_NZ(cpu_T[0]);
+ gen_cc_C_add(cpu_T[0], cpu_cc_src);
+}
+
+/* old op:
+ if (src1 < T1)
+ env->psr |= PSR_CARRY;
+*/
+static inline void gen_cc_C_sub(TCGv src1, TCGv src2)
+{
+ int l1;
+
+ l1 = gen_new_label();
+ tcg_gen_brcond_i32(TCG_COND_GEU, src1, src2, l1);
+ tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
+ gen_set_label(l1);
+#ifdef TARGET_SPARC64
+ {
+ int l2;
+
+ l2 = gen_new_label();
+ tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
+ gen_set_label(l2);
+ }
+#endif
+}
+
+/* old op:
+ if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
+ env->psr |= PSR_OVF;
+*/
+static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2)
+{
+ TCGv r_temp, r_temp2, r_temp3, r_zero;
+ int l1;
+
+ l1 = gen_new_label();
+
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ r_temp2 = tcg_temp_new(TCG_TYPE_TL);
+ r_temp3 = tcg_temp_new(TCG_TYPE_TL);
+ r_zero = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xor_tl(r_temp2, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, r_temp2);
+ tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
+ tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
+ tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
+ gen_set_label(l1);
+#ifdef TARGET_SPARC64
+ {
+ int l2;
+
+ l2 = gen_new_label();
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xor_tl(r_temp2, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, r_temp2);
+ tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
+ tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
+ gen_set_label(l2);
+ }
+#endif
+}
+
+static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
+{
+ TCGv r_temp, r_temp2, r_temp3, r_zero;
+ int l1;
+
+ l1 = gen_new_label();
+
+ r_temp = tcg_temp_new(TCG_TYPE_TL);
+ r_temp2 = tcg_temp_new(TCG_TYPE_TL);
+ r_temp3 = tcg_temp_new(TCG_TYPE_TL);
+ r_zero = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xor_tl(r_temp2, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, r_temp2);
+ tcg_gen_andi_tl(r_temp3, r_temp, (1 << 31));
+ tcg_gen_brcond_i32(TCG_COND_EQ, r_temp3, r_zero, l1);
+ gen_op_exception(TT_TOVF);
+ gen_set_label(l1);
+#ifdef TARGET_SPARC64
+ {
+ int l2;
+
+ l2 = gen_new_label();
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_xor_tl(r_temp, src1, src2);
+ tcg_gen_xor_tl(r_temp2, src1, dst);
+ tcg_gen_and_tl(r_temp, r_temp, r_temp2);
+ tcg_gen_andi_tl(r_temp3, r_temp, (1ULL << 63));
+ tcg_gen_brcond_tl(TCG_COND_EQ, r_temp3, r_zero, l2);
+ gen_op_exception(TT_TOVF);
+ gen_set_label(l2);
+ }
+#endif
+}
+
+static inline void gen_op_sub_T1_T0_cc(void)
+{
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_cc_clear();
+ gen_cc_NZ(cpu_T[0]);
+ gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
+ gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
+}
+
+static inline void gen_op_subx_T1_T0_cc(void)
+{
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
+ tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
+ gen_cc_clear();
+ gen_cc_C_sub(cpu_T[0], cpu_cc_src);
+ tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_cc_C_sub(cpu_T[0], cpu_cc_src);
+ gen_cc_NZ(cpu_T[0]);
+ gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
+}
+
+static inline void gen_op_tsub_T1_T0_cc(void)
+{
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_cc_clear();
+ gen_cc_NZ(cpu_T[0]);
+ gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
+ gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
+}
+
+static inline void gen_op_tsub_T1_T0_ccTV(void)
+{
+ gen_tag_tv(cpu_T[0], cpu_T[1]);
+ tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
+ tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+ gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
+ gen_cc_clear();
+ gen_cc_NZ(cpu_T[0]);
+ gen_cc_C_sub(cpu_cc_src, cpu_T[1]);
+}
+
+static inline void gen_op_div_cc(void)
+{
+ int l1;
+ TCGv r_zero;
+
+ gen_cc_clear();
+ gen_cc_NZ(cpu_T[0]);
+ l1 = gen_new_label();
+ r_zero = tcg_temp_new(TCG_TYPE_TL);
+ tcg_gen_movi_tl(r_zero, 0);
+ tcg_gen_brcond_i32(TCG_COND_EQ, cpu_T[1], r_zero, l1);
+ tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
+ gen_set_label(l1);
+}
+
+static inline void gen_op_logic_T0_cc(void)
+{
+ gen_cc_clear();
+ gen_cc_NZ(cpu_T[0]);
+}
+
// 1
static inline void gen_op_eval_ba(TCGv dst)
{
@@ -789,14 +1193,13 @@ static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
{
TCGv r_src;
- r_src = tcg_temp_new(TCG_TYPE_TL);
#ifdef TARGET_SPARC64
if (cc)
- tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, xcc));
+ r_src = cpu_xcc;
else
- tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, psr));
+ r_src = cpu_psr;
#else
- tcg_gen_ld_i32(r_src, cpu_env, offsetof(CPUSPARCState, psr));
+ r_src = cpu_psr;
#endif
switch (cond) {
case 0x0:
@@ -1170,15 +1573,6 @@ static inline void gen_op_fcmpeq(int fccno)
#endif
-static inline void gen_op_exception(int exception)
-{
- TCGv r_except;
-
- r_except = tcg_temp_new(TCG_TYPE_I32);
- tcg_gen_movi_i32(r_except, exception);
- tcg_gen_helper_0_1(raise_exception, r_except);
-}
-
static inline void gen_op_fpexception_im(int fsr_flags)
{
tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, fsr));
@@ -2632,9 +3026,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (xop & 0x10)
gen_op_addx_T1_T0_cc();
else {
- tcg_gen_ld_i32(cpu_tmp0, cpu_env,
- offsetof(CPUSPARCState, psr));
- gen_mov_reg_C(cpu_tmp0, cpu_tmp0);
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
@@ -2658,9 +3050,7 @@ static void disas_sparc_insn(DisasContext * dc)
if (xop & 0x10)
gen_op_subx_T1_T0_cc();
else {
- tcg_gen_ld_i32(cpu_tmp0, cpu_env,
- offsetof(CPUSPARCState, psr));
- gen_mov_reg_C(cpu_tmp0, cpu_tmp0);
+ gen_mov_reg_C(cpu_tmp0, cpu_psr);
tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
}
@@ -4345,11 +4735,23 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model)
TCG_AREG0, offsetof(CPUState, t1), "T1");
cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
TCG_AREG0, offsetof(CPUState, t2), "T2");
+ cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
+ TCG_AREG0, offsetof(CPUState, xcc),
+ "xcc");
#else
cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
#endif
+ cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, cc_src),
+ "cc_src");
+ cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
+ TCG_AREG0, offsetof(CPUState, cc_dst),
+ "cc_dst");
+ cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
+ TCG_AREG0, offsetof(CPUState, psr),
+ "psr");
}
cpu_reset(env);
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-27 14:21:10 +0000