diff options
| -rw-r--r-- | target-s390x/cpu-qom.h | 2 | ||||
| -rw-r--r-- | target-s390x/cpu.c | 14 | ||||
| -rw-r--r-- | target-s390x/cpu.h | 3 |
3 files changed, 19 insertions, 0 deletions
diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h index cbe2341b3b..2dc175018f 100644 --- a/target-s390x/cpu-qom.h +++ b/target-s390x/cpu-qom.h @@ -36,6 +36,7 @@ * S390CPUClass: * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. + * @load_normal: Performs a load normal. * * An S/390 CPU model. */ @@ -46,6 +47,7 @@ typedef struct S390CPUClass { DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); + void (*load_normal)(CPUState *cpu); } S390CPUClass; /** diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 5cc99387b2..69f5e105dd 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -65,6 +65,17 @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value) cpu->env.psw.addr = value; } +#if !defined(CONFIG_USER_ONLY) +/* S390CPUClass::load_normal() */ +static void s390_cpu_load_normal(CPUState *s) +{ + S390CPU *cpu = S390_CPU(s); + cpu->env.psw.addr = ldl_phys(4) & PSW_MASK_ESA_ADDR; + cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64; + s390_add_running_cpu(cpu); +} +#endif + /* CPUClass::reset() */ static void s390_cpu_reset(CPUState *s) { @@ -169,6 +180,9 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) dc->realize = s390_cpu_realizefn; scc->parent_reset = cc->reset; +#if !defined(CONFIG_USER_ONLY) + scc->load_normal = s390_cpu_load_normal; +#endif cc->reset = s390_cpu_reset; cc->do_interrupt = s390_cpu_do_interrupt; diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index af9de5ed0b..b866ea189d 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -228,6 +228,8 @@ typedef struct CPUS390XState { #undef PSW_MASK_CC #undef PSW_MASK_PM #undef PSW_MASK_64 +#undef PSW_MASK_32 +#undef PSW_MASK_ESA_ADDR #define PSW_MASK_PER 0x4000000000000000ULL #define PSW_MASK_DAT 0x0400000000000000ULL @@ -243,6 +245,7 @@ typedef struct CPUS390XState { #define PSW_MASK_PM 0x00000F0000000000ULL #define PSW_MASK_64 0x0000000100000000ULL #define PSW_MASK_32 0x0000000080000000ULL +#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL #undef PSW_ASC_PRIMARY #undef PSW_ASC_ACCREG |