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-rw-r--r--hw/i386/acpi-build.c43
-rw-r--r--hw/pci-host/piix.c10
-rw-r--r--hw/pci-host/q35.c12
-rw-r--r--include/hw/i386/pc.h5
-rw-r--r--include/hw/pci-host/q35.h2
5 files changed, 34 insertions, 38 deletions
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 5a594be8ee..576c7af657 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -229,26 +229,25 @@ static Object *acpi_get_i386_pci_host(void)
return OBJECT(host);
}
-static void acpi_get_pci_info(PcPciInfo *info)
+static void acpi_get_pci_holes(Range *hole, Range *hole64)
{
Object *pci_host;
-
pci_host = acpi_get_i386_pci_host();
g_assert(pci_host);
- info->w32.begin = object_property_get_int(pci_host,
- PCI_HOST_PROP_PCI_HOLE_START,
- NULL);
- info->w32.end = object_property_get_int(pci_host,
- PCI_HOST_PROP_PCI_HOLE_END,
- NULL);
- info->w64.begin = object_property_get_int(pci_host,
- PCI_HOST_PROP_PCI_HOLE64_START,
- NULL);
- info->w64.end = object_property_get_int(pci_host,
- PCI_HOST_PROP_PCI_HOLE64_END,
+ hole->begin = object_property_get_int(pci_host,
+ PCI_HOST_PROP_PCI_HOLE_START,
+ NULL);
+ hole->end = object_property_get_int(pci_host,
+ PCI_HOST_PROP_PCI_HOLE_END,
+ NULL);
+ hole64->begin = object_property_get_int(pci_host,
+ PCI_HOST_PROP_PCI_HOLE64_START,
NULL);
+ hole64->end = object_property_get_int(pci_host,
+ PCI_HOST_PROP_PCI_HOLE64_END,
+ NULL);
}
#define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
@@ -1890,7 +1889,7 @@ static Aml *build_q35_osc_method(void)
static void
build_dsdt(GArray *table_data, BIOSLinker *linker,
AcpiPmInfo *pm, AcpiMiscInfo *misc,
- PcPciInfo *pci, MachineState *machine)
+ Range *pci_hole, Range *pci_hole64, MachineState *machine)
{
CrsRangeEntry *entry;
Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
@@ -2047,7 +2046,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
AML_CACHEABLE, AML_READ_WRITE,
0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
- crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
+ crs_replace_with_free_ranges(mem_ranges,
+ pci_hole->begin, pci_hole->end - 1);
for (i = 0; i < mem_ranges->len; i++) {
entry = g_ptr_array_index(mem_ranges, i);
aml_append(crs,
@@ -2057,12 +2057,12 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
0, entry->limit - entry->base + 1));
}
- if (pci->w64.begin) {
+ if (pci_hole64->begin) {
aml_append(crs,
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
AML_CACHEABLE, AML_READ_WRITE,
- 0, pci->w64.begin, pci->w64.end - 1, 0,
- pci->w64.end - pci->w64.begin));
+ 0, pci_hole64->begin, pci_hole64->end - 1, 0,
+ pci_hole64->end - pci_hole64->begin));
}
if (misc->tpm_version != TPM_VERSION_UNSPEC) {
@@ -2554,7 +2554,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
AcpiPmInfo pm;
AcpiMiscInfo misc;
AcpiMcfgInfo mcfg;
- PcPciInfo pci;
+ Range pci_hole, pci_hole64;
uint8_t *u;
size_t aml_len = 0;
GArray *tables_blob = tables->table_data;
@@ -2562,7 +2562,7 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
acpi_get_pm_info(&pm);
acpi_get_misc_info(&misc);
- acpi_get_pci_info(&pci);
+ acpi_get_pci_holes(&pci_hole, &pci_hole64);
acpi_get_slic_oem(&slic_oem);
table_offsets = g_array_new(false, true /* clear */,
@@ -2584,7 +2584,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine)
/* DSDT is pointed to by FADT */
dsdt = tables_blob->len;
- build_dsdt(tables_blob, tables->linker, &pm, &misc, &pci, machine);
+ build_dsdt(tables_blob, tables->linker, &pm, &misc,
+ &pci_hole, &pci_hole64, machine);
/* Count the size of the DSDT and SSDT, we will need it for legacy
* sizing of ACPI tables.
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index d0b76c906e..b1bfc59379 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -48,7 +48,7 @@
typedef struct I440FXState {
PCIHostState parent_obj;
- PcPciInfo pci_info;
+ Range pci_hole;
uint64_t pci_hole64_size;
uint32_t short_root_bus;
} I440FXState;
@@ -221,7 +221,7 @@ static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
Error **errp)
{
I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
- uint32_t value = s->pci_info.w32.begin;
+ uint32_t value = s->pci_hole.begin;
visit_type_uint32(v, name, &value, errp);
}
@@ -231,7 +231,7 @@ static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
Error **errp)
{
I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
- uint32_t value = s->pci_info.w32.end;
+ uint32_t value = s->pci_hole.end;
visit_type_uint32(v, name, &value, errp);
}
@@ -344,8 +344,8 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
f->ram_memory = ram_memory;
i440fx = I440FX_PCI_HOST_BRIDGE(dev);
- i440fx->pci_info.w32.begin = below_4g_mem_size;
- i440fx->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
+ i440fx->pci_hole.begin = below_4g_mem_size;
+ i440fx->pci_hole.end = IO_APIC_DEFAULT_ADDRESS;
/* setup pci memory mapping */
pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index eb1b2f77b7..f908ba36be 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -74,7 +74,7 @@ static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
Error **errp)
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
- uint32_t value = s->mch.pci_info.w32.begin;
+ uint32_t value = s->mch.pci_hole.begin;
visit_type_uint32(v, name, &value, errp);
}
@@ -84,7 +84,7 @@ static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
Error **errp)
{
Q35PCIHost *s = Q35_HOST_DEVICE(obj);
- uint32_t value = s->mch.pci_info.w32.end;
+ uint32_t value = s->mch.pci_hole.end;
visit_type_uint32(v, name, &value, errp);
}
@@ -205,9 +205,9 @@ static void q35_host_initfn(Object *obj)
* it's not a power of two, which means an MTRR
* can't cover it exactly.
*/
- s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
+ s->mch.pci_hole.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
MCH_HOST_BRIDGE_PCIEXBAR_MAX;
- s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
+ s->mch.pci_hole.end = IO_APIC_DEFAULT_ADDRESS;
}
static const TypeInfo q35_host_info = {
@@ -288,9 +288,9 @@ static void mch_update_pciexbar(MCHPCIState *mch)
* which means an MTRR can't cover it exactly.
*/
if (enable) {
- mch->pci_info.w32.begin = addr + length;
+ mch->pci_hole.begin = addr + length;
} else {
- mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
+ mch->pci_hole.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
}
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 7e43b20b4b..d44e5e922b 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -150,11 +150,6 @@ struct PCMachineClass {
/* PC-style peripherals (also used by other machines). */
-typedef struct PcPciInfo {
- Range w32;
- Range w64;
-} PcPciInfo;
-
#define ACPI_PM_PROP_S3_DISABLED "disable_s3"
#define ACPI_PM_PROP_S4_DISABLED "disable_s4"
#define ACPI_PM_PROP_S4_VAL "s4_val"
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 73992b4ed6..0d64032d87 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -55,7 +55,7 @@ typedef struct MCHPCIState {
MemoryRegion smram_region, open_high_smram;
MemoryRegion smram, low_smram, high_smram;
MemoryRegion tseg_blackhole, tseg_window;
- PcPciInfo pci_info;
+ Range pci_hole;
uint64_t below_4g_mem_size;
uint64_t above_4g_mem_size;
uint64_t pci_hole64_size;
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-25 03:04:29 +0000