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-rw-r--r--target-sh4/cpu-qom.h2
-rw-r--r--target-sh4/cpu.c14
-rw-r--r--target-sh4/translate.c5
3 files changed, 19 insertions, 2 deletions
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index 09573c9c34..d368db1b0a 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -33,6 +33,7 @@
/**
* SuperHCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A SuperH CPU model.
@@ -42,6 +43,7 @@ typedef struct SuperHCPUClass {
CPUClass parent_class;
/*< public >*/
+ DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} SuperHCPUClass;
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index d2831226b9..c66442f445 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -54,6 +54,17 @@ static void superh_cpu_reset(CPUState *s)
set_default_nan_mode(1, &env->fp_status);
}
+static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+ SuperHCPU *cpu = SUPERH_CPU(dev);
+ SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
+
+ cpu_reset(CPU(cpu));
+ qemu_init_vcpu(&cpu->env);
+
+ scc->parent_realize(dev, errp);
+}
+
static void superh_cpu_initfn(Object *obj)
{
SuperHCPU *cpu = SUPERH_CPU(obj);
@@ -75,6 +86,9 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
CPUClass *cc = CPU_CLASS(oc);
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+ scc->parent_realize = dc->realize;
+ dc->realize = superh_cpu_realizefn;
+
scc->parent_reset = cc->reset;
cc->reset = superh_cpu_reset;
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 260aaab559..2409a103b2 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -253,9 +253,10 @@ SuperHCPU *cpu_sh4_init(const char *cpu_model)
env->features = def->features;
sh4_translate_init();
env->cpu_model_str = cpu_model;
- cpu_reset(CPU(cpu));
cpu_register(env, def);
- qemu_init_vcpu(env);
+
+ object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
return cpu;
}