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-rw-r--r--Makefile.target2
-rw-r--r--cpu-exec.c1
-rw-r--r--hw/gt64xxx.c5
-rw-r--r--hw/i8259.c7
-rw-r--r--hw/mips_int.c39
-rw-r--r--hw/mips_malta.c10
-rw-r--r--hw/mips_r4k.c9
-rw-r--r--hw/mips_timer.c6
-rw-r--r--target-mips/cpu.h1
-rw-r--r--target-mips/exec.h1
-rw-r--r--target-mips/op.c62
-rw-r--r--target-mips/op_helper.c5
-rw-r--r--vl.h3
13 files changed, 76 insertions, 75 deletions
diff --git a/Makefile.target b/Makefile.target
index ba8d5e99bd..0deef01122 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -376,7 +376,7 @@ VL_OBJS+= grackle_pci.o prep_pci.o unin_pci.o
CPPFLAGS += -DHAS_AUDIO
endif
ifeq ($(TARGET_ARCH), mips)
-VL_OBJS+= mips_r4k.o mips_malta.o mips_timer.o dma.o vga.o serial.o i8254.o i8259.o
+VL_OBJS+= mips_r4k.o mips_malta.o mips_timer.o mips_int.o dma.o vga.o serial.o i8254.o i8259.o
VL_OBJS+= ide.o gt64xxx.o pckbd.o ps2.o fdc.o mc146818rtc.o usb-uhci.o acpi.o
VL_OBJS+= piix_pci.o parallel.o mixeng.o cirrus_vga.o $(SOUND_HW) $(AUDIODRV)
DEFINES += -DHAS_AUDIO
diff --git a/cpu-exec.c b/cpu-exec.c
index f9a06e5302..6662b39741 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -535,7 +535,6 @@ int cpu_exec(CPUState *env1)
env->exception_index = EXCP_EXT_INTERRUPT;
env->error_code = 0;
do_interrupt(env);
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
#if defined(__sparc__) && !defined(HOST_SOLARIS)
tmp_T0 = 0;
#else
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index f3ff613811..84e041fcfc 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -1,7 +1,7 @@
/*
* QEMU GT64120 PCI host
*
- * Copyright (c) 2006 Aurelien Jarno
+ * Copyright (c) 2006,2007 Aurelien Jarno
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -433,7 +433,8 @@ static uint32_t gt64120_readl (void *opaque,
val = s->regs[saddr];
break;
case GT_PCI0_IACK:
- val = pic_intack_read(isa_pic);
+ /* Read the IRQ number */
+ val = pic_read_irq(isa_pic);
break;
/* SDRAM Parameters */
diff --git a/hw/i8259.c b/hw/i8259.c
index c747f106e9..f8b5a984b5 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -161,6 +161,13 @@ void pic_update_irq(PicState2 *s)
#endif
s->irq_request(s->irq_request_opaque, 1);
}
+
+/* all targets should do this rather than acking the IRQ in the cpu */
+#if defined(TARGET_MIPS)
+ else {
+ s->irq_request(s->irq_request_opaque, 0);
+ }
+#endif
}
#ifdef DEBUG_IRQ_LATENCY
diff --git a/hw/mips_int.c b/hw/mips_int.c
new file mode 100644
index 0000000000..93d599fc60
--- /dev/null
+++ b/hw/mips_int.c
@@ -0,0 +1,39 @@
+#include "vl.h"
+#include "cpu.h"
+
+/* Raise IRQ to CPU if necessary. It must be called every time the active
+ IRQ may change */
+void cpu_mips_update_irq(CPUState *env)
+{
+ if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
+ (env->CP0_Status & (1 << CP0St_IE)) &&
+ !(env->hflags & MIPS_HFLAG_EXL) &&
+ !(env->hflags & MIPS_HFLAG_ERL) &&
+ !(env->hflags & MIPS_HFLAG_DM)) {
+ if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
+ cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ }
+ } else {
+ cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ }
+}
+
+void cpu_mips_irq_request(void *opaque, int irq, int level)
+{
+ CPUState *env = first_cpu;
+
+ uint32_t mask;
+
+ if (irq >= 16)
+ return;
+
+ mask = 1 << (irq + CP0Ca_IP);
+
+ if (level) {
+ env->CP0_Cause |= mask;
+ } else {
+ env->CP0_Cause &= ~mask;
+ }
+ cpu_mips_update_irq(env);
+}
+
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 12343e0ade..7ddf2fd175 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -54,16 +54,10 @@ typedef struct {
static PITState *pit;
+/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
static void pic_irq_request(void *opaque, int level)
{
- CPUState *env = first_cpu;
- if (level) {
- env->CP0_Cause |= 0x00000400;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
- } else {
- env->CP0_Cause &= ~0x00000400;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
- }
+ cpu_mips_irq_request(opaque, 2, level);
}
/* Malta FPGA */
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c
index ffed67c2a5..5fa5b76a68 100644
--- a/hw/mips_r4k.c
+++ b/hw/mips_r4k.c
@@ -38,14 +38,7 @@ static PITState *pit; /* PIT i8254 */
/*The PIC is attached to the MIPS CPU INT0 pin */
static void pic_irq_request(void *opaque, int level)
{
- CPUState *env = first_cpu;
- if (level) {
- env->CP0_Cause |= 0x00000400;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
- } else {
- env->CP0_Cause &= ~0x00000400;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
- }
+ cpu_mips_irq_request(opaque, 2, level);
}
static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index 251324d7b8..bc83036b34 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -57,8 +57,7 @@ void cpu_mips_store_count (CPUState *env, uint32_t value)
void cpu_mips_store_compare (CPUState *env, uint32_t value)
{
cpu_mips_update_count(env, cpu_mips_get_count(env), value);
- env->CP0_Cause &= ~0x00008000;
- cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_mips_irq_request(env, 7, 0);
}
static void mips_timer_cb (void *opaque)
@@ -72,8 +71,7 @@ static void mips_timer_cb (void *opaque)
}
#endif
cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
- env->CP0_Cause |= 0x00008000;
- cpu_interrupt(env, CPU_INTERRUPT_HARD);
+ cpu_mips_irq_request(env, 7, 1);
}
void cpu_mips_clock_init (CPUState *env)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 8781e3098d..3c99054d6d 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -158,6 +158,7 @@ struct CPUMIPSState {
#define CP0Ca_IV 23
#define CP0Ca_WP 22
#define CP0Ca_IP 8
+#define CP0Ca_IP_mask 0x0000FF00
#define CP0Ca_EC 2
target_ulong CP0_EPC;
int32_t CP0_PRid;
diff --git a/target-mips/exec.h b/target-mips/exec.h
index 3d6bb7d609..15397b6920 100644
--- a/target-mips/exec.h
+++ b/target-mips/exec.h
@@ -164,6 +164,7 @@ uint32_t cpu_mips_get_random (CPUState *env);
uint32_t cpu_mips_get_count (CPUState *env);
void cpu_mips_store_count (CPUState *env, uint32_t value);
void cpu_mips_store_compare (CPUState *env, uint32_t value);
+void cpu_mips_update_irq(CPUState *env);
void cpu_mips_clock_init (CPUState *env);
void cpu_mips_tlb_flush (CPUState *env, int flush_global);
diff --git a/target-mips/op.c b/target-mips/op.c
index dec9f31ade..9d30d03cd3 100644
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -1357,7 +1357,7 @@ void op_mtc0_compare (void)
void op_mtc0_status (void)
{
- uint32_t val, old, mask;
+ uint32_t val, old;
val = (int32_t)T0 & 0xFA78FF01;
old = env->CP0_Status;
@@ -1374,21 +1374,9 @@ void op_mtc0_status (void)
else
env->hflags &= ~MIPS_HFLAG_EXL;
env->CP0_Status = val;
- /* If we unmasked an asserted IRQ, raise it */
- mask = 0x0000FF00;
if (loglevel & CPU_LOG_TB_IN_ASM)
CALL_FROM_TB2(do_mtc0_status_debug, old, val);
- if ((val & (1 << CP0St_IE)) && !(old & (1 << CP0St_IE)) &&
- !(env->hflags & MIPS_HFLAG_EXL) &&
- !(env->hflags & MIPS_HFLAG_ERL) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
- (env->CP0_Status & env->CP0_Cause & mask)) {
- env->interrupt_request |= CPU_INTERRUPT_HARD;
- if (logfile)
- CALL_FROM_TB0(do_mtc0_status_irqraise_debug);
- } else if (!(val & (1 << CP0St_IE)) && (old & (1 << CP0St_IE))) {
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
- }
+ CALL_FROM_TB1(cpu_mips_update_irq, env);
RETURN();
}
@@ -1415,22 +1403,13 @@ void op_mtc0_srsmap (void)
void op_mtc0_cause (void)
{
- uint32_t val, old;
+ env->CP0_Cause = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);
- val = (env->CP0_Cause & 0xB000F87C) | (T0 & 0x00C00300);
- old = env->CP0_Cause;
- env->CP0_Cause = val;
-#if 0
- {
- int i, mask;
- /* Check if we ever asserted a software IRQ */
- for (i = 0; i < 2; i++) {
- mask = 0x100 << i;
- if ((val & mask) & !(old & mask))
- CALL_FROM_TB1(mips_set_irq, i);
- }
+ /* Handle the software interrupt as an hardware one, as they
+ are very similar */
+ if (T0 & CP0Ca_IP_mask) {
+ CALL_FROM_TB1(cpu_mips_update_irq, env);
}
-#endif
RETURN();
}
@@ -2074,36 +2053,17 @@ void op_pmon (void)
void op_di (void)
{
- uint32_t val;
-
T0 = env->CP0_Status;
- val = T0 & ~(1 << CP0St_IE);
- if (val != T0) {
- env->interrupt_request &= ~CPU_INTERRUPT_HARD;
- env->CP0_Status = val;
- }
+ env->CP0_Status = T0 & ~(1 << CP0St_IE);
+ CALL_FROM_TB1(cpu_mips_update_irq, env);
RETURN();
}
void op_ei (void)
{
- uint32_t val;
-
T0 = env->CP0_Status;
- val = T0 | (1 << CP0St_IE);
- if (val != T0) {
- const uint32_t mask = 0x0000FF00;
-
- env->CP0_Status = val;
- if (!(env->hflags & MIPS_HFLAG_EXL) &&
- !(env->hflags & MIPS_HFLAG_ERL) &&
- !(env->hflags & MIPS_HFLAG_DM) &&
- (env->CP0_Status & env->CP0_Cause & mask)) {
- env->interrupt_request |= CPU_INTERRUPT_HARD;
- if (logfile)
- CALL_FROM_TB0(do_mtc0_status_irqraise_debug);
- }
- }
+ env->CP0_Status = T0 | (1 << CP0St_IE);
+ CALL_FROM_TB1(cpu_mips_update_irq, env);
RETURN();
}
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index bea5a905e1..9596d04fb6 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -265,6 +265,11 @@ void cpu_mips_store_compare(CPUState *env, uint32_t value)
cpu_abort(env, "mtc0 compare\n");
}
+void cpu_mips_update_irq(CPUState *env)
+{
+ cpu_abort(env, "mtc0 status / mtc0 cause\n");
+}
+
void do_mtc0_status_debug(uint32_t old, uint32_t val)
{
cpu_abort(env, "mtc0 status debug\n");
diff --git a/vl.h b/vl.h
index 543eb722c4..92b1d253af 100644
--- a/vl.h
+++ b/vl.h
@@ -1067,6 +1067,9 @@ extern QEMUMachine mips_machine;
/* mips_malta.c */
extern QEMUMachine mips_malta_machine;
+/* mips_int */
+extern void cpu_mips_irq_request(void *opaque, int irq, int level);
+
/* mips_timer.c */
extern void cpu_mips_clock_init(CPUState *);
extern void cpu_mips_irqctrl_init (void);
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-23 14:39:34 +0000