diff options
| -rw-r--r-- | target/arm/t16.decode | 9 | ||||
| -rw-r--r-- | target/arm/translate.c | 18 |
2 files changed, 12 insertions, 15 deletions
diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 032902a1f4..19a442b894 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -24,6 +24,7 @@ &s_rri_rot !extern s rn rd imm rot &s_rrrr !extern s rd rn rm ra &rrr_rot !extern rd rn rm rot +&rr !extern rd rm &ri !extern rd imm &r !extern rm &ldst_rr !extern p w u rn rt rm shimm shtype @@ -195,3 +196,11 @@ SETEND 1011 0110 010 1 E:1 000 &setend CPS 1011 0110 011 . 0 A:1 I:1 F:1 &cps mode=0 M=0 %imod CPS_v7m 1011 0110 011 im:1 00 I:1 F:1 } + +# Reverse bytes + +@rdm .... .... .. rm:3 rd:3 &rr + +REV 1011 1010 00 ... ... @rdm +REV16 1011 1010 01 ... ... @rdm +REVSH 1011 1010 11 ... ... @rdm diff --git a/target/arm/translate.c b/target/arm/translate.c index ce394ddb00..b70491d39e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10730,7 +10730,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn) { - uint32_t val, op, rm, rn, rd, shift, cond; + uint32_t val, op, rm, rd, shift, cond; int32_t offset; int i; TCGv_i32 tmp; @@ -10927,20 +10927,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) break; } - /* Otherwise this is rev */ - ARCH(6); - rn = (insn >> 3) & 0x7; - rd = insn & 0x7; - tmp = load_reg(s, rn); - switch (op1) { - case 0: tcg_gen_bswap32_i32(tmp, tmp); break; - case 1: gen_rev16(tmp, tmp); break; - case 3: gen_revsh(tmp, tmp); break; - default: - g_assert_not_reached(); - } - store_reg(s, rd, tmp); - break; + /* Otherwise this is rev, in decodetree */ + goto illegal_op; } case 6: /* setend, cps; in decodetree */ |