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-rw-r--r--include/exec/cpu-defs.h2
-rw-r--r--target/alpha/cpu.h3
-rw-r--r--target/arm/cpu.h4
-rw-r--r--target/cris/cpu.h2
-rw-r--r--target/hppa/cpu.h3
-rw-r--r--target/i386/cpu.h4
-rw-r--r--target/lm32/cpu.h2
-rw-r--r--target/m68k/cpu.h2
-rw-r--r--target/microblaze/cpu.h2
-rw-r--r--target/mips/cpu.h2
-rw-r--r--target/moxie/cpu.h3
-rw-r--r--target/nios2/cpu.h2
-rw-r--r--target/openrisc/cpu.h2
-rw-r--r--target/ppc/cpu.h2
-rw-r--r--target/riscv/cpu.h3
-rw-r--r--target/s390x/cpu.h2
-rw-r--r--target/sh4/cpu.h2
-rw-r--r--target/sparc/cpu.h2
-rw-r--r--target/tilegx/cpu.h2
-rw-r--r--target/tricore/cpu.h2
-rw-r--r--target/unicore32/cpu.h2
-rw-r--r--target/xtensa/cpu.h2
22 files changed, 2 insertions, 50 deletions
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 006f8db9cf..9bc713a70b 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -231,8 +231,6 @@ typedef struct CPUTLB { } CPUTLB;
#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
-#define CPU_COMMON /* Nothing */
-
/*
* This structure must be placed in ArchCPU immedately
* before CPUArchState, as a field named "neg".
diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index 94fbc00a3b..5d6fb222b5 100644
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -251,9 +251,6 @@ struct CPUAlphaState {
/* This alarm doesn't exist in real hardware; we wish it did. */
uint64_t alarm_expire;
- /* Those resources are used only in QEMU core */
- CPU_COMMON
-
int error_code;
uint32_t features;
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5965c52f0c..8fa9772c9d 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -645,9 +645,7 @@ typedef struct CPUARMState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
- /* Fields after CPU_COMMON are preserved across CPU reset. */
+ /* Fields after this point are preserved across CPU reset. */
/* Internal CPU feature flags. */
uint64_t features;
diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index ad93d1a9ee..9d2a80d995 100644
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -163,8 +163,6 @@ typedef struct CPUCRISState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Members from load_info on are preserved across resets. */
void *load_info;
} CPUCRISState;
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index f7c6205218..c7db2eca9a 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -197,9 +197,6 @@ struct CPUHPPAState {
target_ureg cr_back[2]; /* back of cr17/cr18 */
target_ureg shadow[7]; /* shadow registers */
- /* Those resources are used only in QEMU core */
- CPU_COMMON
-
/* ??? The number of entries isn't specified by the architecture. */
/* ??? Implement a unified itlb/dtlb for the moment. */
/* ??? We should use a more intelligent data structure. */
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e7580a86e5..edad6e1efb 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1289,9 +1289,7 @@ typedef struct CPUX86State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
- /* Fields after CPU_COMMON are preserved across CPU reset. */
+ /* Fields after this point are preserved across CPU reset. */
/* processor features (e.g. for CPUID insn) */
/* Minimum level/xlevel/xlevel2, based on CPU model + features */
diff --git a/target/lm32/cpu.h b/target/lm32/cpu.h
index 324bc90f81..3e10a693a3 100644
--- a/target/lm32/cpu.h
+++ b/target/lm32/cpu.h
@@ -159,8 +159,6 @@ struct CPULM32State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
uint32_t eba; /* exception base address */
uint32_t deba; /* debug exception base address */
diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index d92263b750..1ebd360afb 100644
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -143,8 +143,6 @@ typedef struct CPUM68KState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
uint32_t features;
} CPUM68KState;
diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index d90c4fbcb5..98b4d915d7 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -266,8 +266,6 @@ struct CPUMBState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* These fields are preserved on reset. */
struct {
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 62af24937d..bbf1aa8b0d 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1041,8 +1041,6 @@ struct CPUMIPSState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
CPUMIPSMVPContext *mvp;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target/moxie/cpu.h b/target/moxie/cpu.h
index c6b681531d..2b596d5d45 100644
--- a/target/moxie/cpu.h
+++ b/target/moxie/cpu.h
@@ -45,9 +45,6 @@ typedef struct CPUMoxieState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
-
- CPU_COMMON
-
} CPUMoxieState;
#include "qom/cpu.h"
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 8cc3d4971e..e40ee27e53 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -167,8 +167,6 @@ struct CPUNios2State {
uint32_t irq_pending;
#endif
-
- CPU_COMMON
};
/**
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 51723e9312..9b80834d68 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -286,8 +286,6 @@ typedef struct CPUOpenRISCState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
uint32_t cpucfgr; /* CPU configure register */
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index e8962e4655..c93ebc4c10 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -999,8 +999,6 @@ struct CPUPPCState {
/* when a memory exception occurs, the access type is stored here */
int access_type;
- CPU_COMMON
-
/* MMU context - only relevant for full system emulation */
#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0ed7031915..a935b17dbd 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -171,9 +171,6 @@ struct CPURISCVState {
float_status fp_status;
- /* QEMU */
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
QEMUTimer *timer; /* Internal timer */
};
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 21688b7c8c..cb103bc3e7 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -114,8 +114,6 @@ struct CPUS390XState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
#if !defined(CONFIG_USER_ONLY)
uint32_t core_id; /* PoP "CPU address", same as cpu_index */
uint64_t cpuid;
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index e266db411f..08cf275f79 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -179,8 +179,6 @@ typedef struct CPUSH4State {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved over CPU reset. */
int id; /* CPU model */
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index a3c4f47d40..49e0349a81 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -446,8 +446,6 @@ struct CPUSPARCState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
- CPU_COMMON
-
/* Fields from here on are preserved across CPU reset. */
target_ulong version;
uint32_t nwindows;
diff --git a/target/tilegx/cpu.h b/target/tilegx/cpu.h
index deb3e836ea..c2acb43c2b 100644
--- a/target/tilegx/cpu.h
+++ b/target/tilegx/cpu.h
@@ -93,8 +93,6 @@ typedef struct CPUTLGState {
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
-
- CPU_COMMON
} CPUTLGState;
#include "qom/cpu.h"
diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index 03b293c1f6..52b07c73bf 100644
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -184,8 +184,6 @@ struct CPUTriCoreState {
int error_code;
uint32_t hflags; /* CPU State */
- CPU_COMMON
-
/* Internal CPU feature flags. */
uint64_t features;
diff --git a/target/unicore32/cpu.h b/target/unicore32/cpu.h
index 39beb32366..6b459dacde 100644
--- a/target/unicore32/cpu.h
+++ b/target/unicore32/cpu.h
@@ -55,8 +55,6 @@ typedef struct CPUUniCore32State {
float_status fp_status;
} ucf64;
- CPU_COMMON
-
/* Internal CPU feature flags. */
uint32_t features;
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index e2d7e8371d..bfc6604b76 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -541,8 +541,6 @@ typedef struct CPUXtensaState {
/* Watchpoints for DBREAK registers */
struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK];
-
- CPU_COMMON
} CPUXtensaState;
/**
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-24 14:01:30 +0000