diff options
| -rw-r--r-- | target/riscv/cpu.c | 12 | ||||
| -rw-r--r-- | target/riscv/cpu.h | 4 |
2 files changed, 16 insertions, 0 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b0a40b83e7..55371b1aa5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -587,6 +587,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) cpu->cfg.ext_d = true; } + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx = true; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { ext |= RVI; @@ -665,6 +670,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) if (cpu->cfg.ext_j) { ext |= RVJ; } + if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh || + cpu->cfg.ext_zfhmin)) { + error_setg(errp, + "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh'," + " 'Zfhmin'"); + return; + } set_misa(env, env->misa_mxl, ext); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8183fb86d5..9ba05042ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -362,8 +362,12 @@ struct RISCVCPUConfig { bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; + bool ext_zdinx; bool ext_zfh; bool ext_zfhmin; + bool ext_zfinx; + bool ext_zhinx; + bool ext_zhinxmin; bool ext_zve32f; bool ext_zve64f; |