diff options
| -rw-r--r-- | hw/mips.h | 6 | ||||
| -rw-r--r-- | hw/mips_jazz.c | 46 | ||||
| -rw-r--r-- | hw/rc4030.c | 286 |
3 files changed, 246 insertions, 92 deletions
@@ -27,6 +27,10 @@ extern void cpu_mips_irq_init_cpu(CPUState *env); extern void cpu_mips_clock_init(CPUState *); /* rc4030.c */ -qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus); +typedef struct rc4030DMAState *rc4030_dma; +typedef void (*rc4030_dma_function)(void *dma, uint8_t *buf, int len); +qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, + rc4030_dma **dmas, + rc4030_dma_function *dma_read, rc4030_dma_function *dma_write); #endif diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index 0dcc332c40..dc08deb301 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -75,6 +75,24 @@ static CPUWriteMemoryFunc *rtc_write[3] = { rtc_writeb, }; +static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +{ + /* Nothing to do. That is only to ensure that + * the current DMA acknowledge cycle is completed. */ +} + +static CPUReadMemoryFunc *dma_dummy_read[3] = { + NULL, + NULL, + NULL, +}; + +static CPUWriteMemoryFunc *dma_dummy_write[3] = { + dma_dummy_writeb, + dma_dummy_writeb, + dma_dummy_writeb, +}; + #ifdef HAS_AUDIO static void audio_init(qemu_irq *pic) { @@ -102,16 +120,6 @@ static void audio_init(qemu_irq *pic) } #endif -static void espdma_memory_read(void *opaque, uint8_t *buf, int len) -{ - printf("espdma_memory_read(buf %p, len %d) not implemented\n", buf, len); -} - -static void espdma_memory_write(void *opaque, uint8_t *buf, int len) -{ - printf("espdma_memory_write(buf %p, len %d) not implemented\n", buf, len); -} - #define MAGNUM_BIOS_SIZE_MAX 0x7e000 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) @@ -125,9 +133,11 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size, int bios_size, n; CPUState *env; qemu_irq *rc4030, *i8259; + rc4030_dma *dmas; + rc4030_dma_function dma_read, dma_write; void *scsi_hba; int hd; - int s_rtc; + int s_rtc, s_dma_dummy; PITState *pit; BlockDriverState *fds[MAX_FD]; qemu_irq esp_reset; @@ -153,7 +163,9 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size, /* load the BIOS image. */ bios_offset = ram_size + vga_ram_size; - snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); + if (bios_name == NULL) + bios_name = BIOS_FILENAME; + snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); bios_size = load_image(buf, phys_ram_base + bios_offset); if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) { fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n", @@ -171,10 +183,14 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size, cpu_mips_clock_init(env); /* Chipset */ - rc4030 = rc4030_init(env->irq[6], env->irq[3]); + rc4030 = rc4030_init(env->irq[6], env->irq[3], + &dmas, &dma_read, &dma_write); + s_dma_dummy = cpu_register_io_memory(0, dma_dummy_read, dma_dummy_write, NULL); + cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy); /* ISA devices */ i8259 = i8259_init(env->irq[4]); + DMA_init(0); pit = pit_init(0x40, i8259[0]); pcspk_init(pit); @@ -200,7 +216,7 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size, /* SCSI adapter */ scsi_hba = esp_init(0x80002000, 0, - espdma_memory_read, espdma_memory_write, NULL, + dma_read, dma_write, dmas[0], rc4030[5], &esp_reset); for (n = 0; n < ESP_MAX_DEVS; n++) { hd = drive_get_index(IF_SCSI, 0, n); @@ -278,6 +294,7 @@ QEMUMachine mips_magnum_machine = { .init = mips_magnum_init, .ram_require = MAGNUM_BIOS_SIZE + VGA_RAM_SIZE, .nodisk_ok = 1, + .use_scsi = 1, }; QEMUMachine mips_pica61_machine = { @@ -286,4 +303,5 @@ QEMUMachine mips_pica61_machine = { .init = mips_pica61_init, .ram_require = MAGNUM_BIOS_SIZE + VGA_RAM_SIZE, .nodisk_ok = 1, + .use_scsi = 1, }; diff --git a/hw/rc4030.c b/hw/rc4030.c index 89cec6e3bb..c37c252508 100644 --- a/hw/rc4030.c +++ b/hw/rc4030.c @@ -26,13 +26,43 @@ #include "mips.h" #include "qemu-timer.h" +/********************************************************/ +/* debug rc4030 */ + //#define DEBUG_RC4030 +//#define DEBUG_RC4030_DMA #ifdef DEBUG_RC4030 +#define DPRINTF(fmt, args...) \ +do { printf("rc4030: " fmt , ##args); } while (0) static const char* irq_names[] = { "parallel", "floppy", "sound", "video", "network", "scsi", "keyboard", "mouse", "serial0", "serial1" }; +#else +#define DPRINTF(fmt, args...) #endif +#define RC4030_ERROR(fmt, args...) \ +do { fprintf(stderr, "rc4030 ERROR: %s: " fmt, __func__ , ##args); } while (0) + +/********************************************************/ +/* rc4030 emulation */ + +typedef struct dma_pagetable_entry { + int32_t frame; + int32_t owner; +} __attribute__((packed)) dma_pagetable_entry; + +#define DMA_PAGESIZE 4096 +#define DMA_REG_ENABLE 1 +#define DMA_REG_COUNT 2 +#define DMA_REG_ADDRESS 3 + +#define DMA_FLAG_ENABLE 0x0001 +#define DMA_FLAG_MEM_TO_DEV 0x0002 +#define DMA_FLAG_TC_INTR 0x0100 +#define DMA_FLAG_MEM_INTR 0x0200 +#define DMA_FLAG_ADDR_INTR 0x0400 + typedef struct rc4030State { uint32_t config; /* 0x0000: RC4030 config register */ @@ -51,7 +81,6 @@ typedef struct rc4030State uint32_t cache_bmask; /* 0x0058: I/O Cache Byte Mask */ uint32_t cache_bwin; /* 0x0060: I/O Cache Buffer Window */ - uint32_t offset208; uint32_t offset210; uint32_t nvram_protect; /* 0x0220: NV ram protect register */ uint32_t offset238; @@ -63,7 +92,6 @@ typedef struct rc4030State QEMUTimer *periodic_timer; uint32_t itr; /* Interval timer reload */ - uint32_t dummy32; qemu_irq timer_irq; qemu_irq jazz_bus_irq; } rc4030State; @@ -165,7 +193,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) case 0x01d0: case 0x01d8: case 0x01e0: - case 0x1e8: + case 0x01e8: case 0x01f0: case 0x01f8: { @@ -176,7 +204,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) break; /* Offset 0x0208 */ case 0x0208: - val = s->offset208; + val = 0; break; /* Offset 0x0210 */ case 0x0210: @@ -188,7 +216,7 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) break; /* Interval timer count */ case 0x0230: - val = s->dummy32; + val = 0; qemu_irq_lower(s->timer_irq); break; /* Offset 0x0238 */ @@ -196,17 +224,13 @@ static uint32_t rc4030_readl(void *opaque, target_phys_addr_t addr) val = s->offset238; break; default: -#ifdef DEBUG_RC4030 - printf("rc4030: invalid read [" TARGET_FMT_lx "]\n", addr); -#endif + RC4030_ERROR("invalid read [" TARGET_FMT_plx "]\n", addr); val = 0; break; } -#ifdef DEBUG_RC4030 if ((addr & ~3) != 0x230) - printf("rc4030: read 0x%02x at " TARGET_FMT_lx "\n", val, addr); -#endif + DPRINTF("read 0x%02x at " TARGET_FMT_plx "\n", val, addr); return val; } @@ -231,9 +255,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) rc4030State *s = opaque; addr &= 0x3fff; -#ifdef DEBUG_RC4030 - printf("rc4030: write 0x%02x at " TARGET_FMT_lx "\n", val, addr); -#endif + DPRINTF("write 0x%02x at " TARGET_FMT_plx "\n", val, addr); switch (addr & ~0x3) { /* Global config register */ @@ -248,6 +270,13 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) case 0x0020: s->dma_tl_limit = val; break; + /* DMA transl. table invalidated */ + case 0x0028: + break; + /* Cache Maintenance */ + case 0x0030: + RC4030_ERROR("Cache maintenance not handled yet (val 0x%02x)\n", val); + break; /* I/O Cache Physical Tag */ case 0x0048: s->cache_ptag = val; @@ -322,7 +351,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) case 0x01d0: case 0x01d8: case 0x01e0: - case 0x1e8: + case 0x01e8: case 0x01f0: case 0x01f8: { @@ -342,9 +371,7 @@ static void rc4030_writel(void *opaque, target_phys_addr_t addr, uint32_t val) set_next_tick(s); break; default: -#ifdef DEBUG_RC4030 - printf("rc4030: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr); -#endif + RC4030_ERROR("invalid write of 0x%02x at [" TARGET_FMT_plx "]\n", val, addr); break; } } @@ -402,7 +429,7 @@ static void update_jazz_irq(rc4030State *s) #ifdef DEBUG_RC4030 if (s->isr_jazz != 0) { uint32_t irq = 0; - printf("jazz pending:"); + DPRINTF("pending irqs:"); for (irq = 0; irq < ARRAY_SIZE(irq_names); irq++) { if (s->isr_jazz & (1 << irq)) { printf(" %s", irq_names[irq]); @@ -442,7 +469,7 @@ static void rc4030_periodic_timer(void *opaque) qemu_irq_raise(s->timer_irq); } -static uint32_t int_readb(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readw(void *opaque, target_phys_addr_t addr) { rc4030State *s = opaque; uint32_t val; @@ -450,14 +477,14 @@ static uint32_t int_readb(void *opaque, target_phys_addr_t addr) addr &= 0xfff; switch (addr) { + /* Local bus int source */ case 0x00: { - /* Local bus int source */ uint32_t pending = s->isr_jazz & s->imr_jazz; val = 0; irq = 0; while (pending) { if (pending & 1) { - //printf("returning irq %s\n", irq_names[irq]); + DPRINTF("returning irq %s\n", irq_names[irq]); val = (irq + 1) << 2; break; } @@ -466,100 +493,93 @@ static uint32_t int_readb(void *opaque, target_phys_addr_t addr) } break; } + /* Local bus int enable mask */ + case 0x02: + val = s->imr_jazz; + break; default: -#ifdef DEBUG_RC4030 - printf("rc4030: (interrupt controller) invalid read [" TARGET_FMT_lx "]\n", addr); -#endif - val = 0; + RC4030_ERROR("(jazz io controller) invalid read [" TARGET_FMT_plx "]\n", addr); + val = 0; } -#ifdef DEBUG_RC4030 - printf("rc4030: (interrupt controller) read 0x%02x at " TARGET_FMT_lx "\n", val, addr); -#endif + DPRINTF("(jazz io controller) read 0x%04x at " TARGET_FMT_plx "\n", val, addr); return val; } -static uint32_t int_readw(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readb(void *opaque, target_phys_addr_t addr) { uint32_t v; - v = int_readb(opaque, addr); - v |= int_readb(opaque, addr + 1) << 8; - return v; + v = jazzio_readw(opaque, addr & ~0x1); + return (v >> (8 * (addr & 0x1))) & 0xff; } -static uint32_t int_readl(void *opaque, target_phys_addr_t addr) +static uint32_t jazzio_readl(void *opaque, target_phys_addr_t addr) { uint32_t v; - v = int_readb(opaque, addr); - v |= int_readb(opaque, addr + 1) << 8; - v |= int_readb(opaque, addr + 2) << 16; - v |= int_readb(opaque, addr + 3) << 24; + v = jazzio_readw(opaque, addr); + v |= jazzio_readw(opaque, addr + 2) << 16; return v; } -static void int_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) +static void jazzio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) { rc4030State *s = opaque; addr &= 0xfff; -#ifdef DEBUG_RC4030 - printf("rc4030: (interrupt controller) write 0x%02x at " TARGET_FMT_lx "\n", val, addr); -#endif + DPRINTF("(jazz io controller) write 0x%04x at " TARGET_FMT_plx "\n", val, addr); switch (addr) { /* Local bus int enable mask */ case 0x02: - s->imr_jazz = (s->imr_jazz & 0xff00) | (val << 0); update_jazz_irq(s); - break; - case 0x03: - s->imr_jazz = (s->imr_jazz & 0x00ff) | (val << 8); update_jazz_irq(s); + s->imr_jazz = val; + update_jazz_irq(s); break; default: -#ifdef DEBUG_RC4030 - printf("rc4030: (interrupt controller) invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr); -#endif + RC4030_ERROR("(jazz io controller) invalid write of 0x%04x at [" TARGET_FMT_plx "]\n", val, addr); break; } } -static void int_writew(void *opaque, target_phys_addr_t addr, uint32_t val) +static void jazzio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) { - int_writeb(opaque, addr, val & 0xff); - int_writeb(opaque, addr + 1, (val >> 8) & 0xff); + uint32_t old_val = jazzio_readw(opaque, addr & ~0x1); + + switch (addr & 1) { + case 0: + val = val | (old_val & 0xff00); + break; + case 1: + val = (val << 8) | (old_val & 0x00ff); + break; + } + jazzio_writew(opaque, addr & ~0x1, val); } -static void int_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void jazzio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) { - int_writeb(opaque, addr, val & 0xff); - int_writeb(opaque, addr + 1, (val >> 8) & 0xff); - int_writeb(opaque, addr + 2, (val >> 16) & 0xff); - int_writeb(opaque, addr + 3, (val >> 24) & 0xff); + jazzio_writew(opaque, addr, val & 0xffff); + jazzio_writew(opaque, addr + 2, (val >> 16) & 0xffff); } -static CPUReadMemoryFunc *int_read[3] = { - int_readb, - int_readw, - int_readl, +static CPUReadMemoryFunc *jazzio_read[3] = { + jazzio_readb, + jazzio_readw, + jazzio_readl, }; -static CPUWriteMemoryFunc *int_write[3] = { - int_writeb, - int_writew, - int_writel, +static CPUWriteMemoryFunc *jazzio_write[3] = { + jazzio_writeb, + jazzio_writew, + jazzio_writel, }; -#define G364_512KB_RAM (0x0) -#define G364_2MB_RAM (0x1) -#define G364_8MB_RAM (0x2) -#define G364_32MB_RAM (0x3) - static void rc4030_reset(void *opaque) { rc4030State *s = opaque; int i; - s->config = (G364_2MB_RAM << 8) | 0x04; + s->config = 0x410; /* some boards seem to accept 0x104 too */ s->invalid_address_register = 0; memset(s->dma_regs, 0, sizeof(s->dma_regs)); @@ -569,7 +589,6 @@ static void rc4030_reset(void *opaque) s->cache_ptag = s->cache_ltag = 0; s->cache_bmask = s->cache_bwin = 0; - s->offset208 = 0; s->offset210 = 0x18186; s->nvram_protect = 7; s->offset238 = 7; @@ -578,21 +597,134 @@ static void rc4030_reset(void *opaque) s->imr_jazz = s->isr_jazz = 0; s->itr = 0; - s->dummy32 = 0; qemu_irq_lower(s->timer_irq); qemu_irq_lower(s->jazz_bus_irq); } -qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus) +static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write) +{ + rc4030State *s = opaque; + target_phys_addr_t entry_addr; + target_phys_addr_t dma_addr, phys_addr; + dma_pagetable_entry entry; + int index, dev_to_mem; + int ncpy, i; + + s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR); + + /* Check DMA channel consistency */ + dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1; + if (!(s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_ENABLE) || + (is_write != dev_to_mem)) { + s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; + return; + } + + if (len > s->dma_regs[n][DMA_REG_COUNT]) + len = s->dma_regs[n][DMA_REG_COUNT]; + + dma_addr = s->dma_regs[n][DMA_REG_ADDRESS]; + i = 0; + for (;;) { + if (i == len) { + s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_TC_INTR; + break; + } + + ncpy = DMA_PAGESIZE - (dma_addr & (DMA_PAGESIZE - 1)); + if (ncpy > len - i) + ncpy = len - i; + + /* Get DMA translation table entry */ + index = dma_addr / DMA_PAGESIZE; + if (index >= s->dma_tl_limit / sizeof(dma_pagetable_entry)) { + s->dma_regs[n][DMA_REG_ENABLE] |= DMA_FLAG_MEM_INTR; + break; + } + entry_addr = s->dma_tl_base + index * sizeof(dma_pagetable_entry); + /* XXX: not sure. should we really use only lowest bits? */ + entry_addr &= 0x7fffffff; + cpu_physical_memory_rw(entry_addr, (uint8_t *)&entry, sizeof(entry), 0); + + /* Read/write data at right place */ + phys_addr = entry.frame + (dma_addr & (DMA_PAGESIZE - 1)); + cpu_physical_memory_rw(phys_addr, &buf[i], ncpy, is_write); + + i += ncpy; + dma_addr += ncpy; + s->dma_regs[n][DMA_REG_COUNT] -= ncpy; + } + +#ifdef DEBUG_RC4030_DMA + { + int i, j; + printf("rc4030 dma: Copying %d bytes %s host %p\n", + len, is_write ? "from" : "to", buf); + for (i = 0; i < len; i += 16) { + int n = min(16, len - i); + for (j = 0; j < n; j++) + printf("%02x ", buf[i + j]); + while (j++ < 16) + printf(" "); + printf("| "); + for (j = 0; j < n; j++) + printf("%c", isprint(buf[i + j]) ? buf[i + j] : '.'); + printf("\n"); + } + } +#endif +} + +struct rc4030DMAState { + void *opaque; + int n; +}; + +static void rc4030_dma_read(void *dma, uint8_t *buf, int len) +{ + rc4030_dma s = dma; + rc4030_do_dma(s->opaque, s->n, buf, len, 0); +} + +static void rc4030_dma_write(void *dma, uint8_t *buf, int len) +{ + rc4030_dma s = dma; + rc4030_do_dma(s->opaque, s->n, buf, len, 1); +} + +static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n) +{ + rc4030_dma *s; + struct rc4030DMAState *p; + int i; + + s = (rc4030_dma *)qemu_mallocz(sizeof(rc4030_dma) * n); + p = (struct rc4030DMAState *)qemu_mallocz(sizeof(struct rc4030DMAState) * n); + for (i = 0; i < n; i++) { + p->opaque = opaque; + p->n = i; + s[i] = p; + p++; + } + return s; +} + +qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus, + rc4030_dma **dmas, + rc4030_dma_function *dma_read, rc4030_dma_function *dma_write) { rc4030State *s; - int s_chipset, s_int; + int s_chipset, s_jazzio; s = qemu_mallocz(sizeof(rc4030State)); if (!s) return NULL; + *dmas = rc4030_allocate_dmas(s, 4); + *dma_read = rc4030_dma_read; + *dma_write = rc4030_dma_write; + s->periodic_timer = qemu_new_timer(vm_clock, rc4030_periodic_timer, s); s->timer_irq = timer; s->jazz_bus_irq = jazz_bus; @@ -602,8 +734,8 @@ qemu_irq *rc4030_init(qemu_irq timer, qemu_irq jazz_bus) s_chipset = cpu_register_io_memory(0, rc4030_read, rc4030_write, s); cpu_register_physical_memory(0x80000000, 0x300, s_chipset); - s_int = cpu_register_io_memory(0, int_read, int_write, s); - cpu_register_physical_memory(0xf0000000, 0x00001000, s_int); + s_jazzio = cpu_register_io_memory(0, jazzio_read, jazzio_write, s); + cpu_register_physical_memory(0xf0000000, 0x00001000, s_jazzio); return qemu_allocate_irqs(rc4030_irq_jazz_request, s, 16); } |