diff options
| -rw-r--r-- | hw/mips_int.c | 2 | ||||
| -rw-r--r-- | hw/mips_malta.c | 36 | ||||
| -rw-r--r-- | hw/serial.c | 29 | ||||
| -rw-r--r-- | target-mips/exec.h | 2 | ||||
| -rw-r--r-- | vl.h | 9 |
5 files changed, 60 insertions, 18 deletions
diff --git a/hw/mips_int.c b/hw/mips_int.c index b384b64d28..ed489f1a16 100644 --- a/hw/mips_int.c +++ b/hw/mips_int.c @@ -27,7 +27,7 @@ void cpu_mips_irq_request(void *opaque, int irq, int level) if (level) { env->CP0_Cause |= 1 << (irq + CP0Ca_IP); } else { - env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP)); + env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); } cpu_mips_update_irq(env); } diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 54b813bdfe..43592df522 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -55,6 +55,7 @@ typedef struct { uint32_t i2csel; CharDriverState *display; char display_text[9]; + SerialState *uart; } MaltaFPGAState; static PITState *pit; @@ -241,6 +242,18 @@ static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr) val = s->brk; break; + /* UART Registers */ + case 0x00900: + case 0x00904: + case 0x00908: + case 0x0090c: + case 0x00910: + case 0x00914: + case 0x00918: + case 0x0091c: + val = serial_mm_readl(s->uart, addr); + break; + /* GPOUT Register */ case 0x00a00: val = s->gpout; @@ -341,6 +354,18 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr, s->brk = val & 0xff; break; + /* UART Registers */ + case 0x00900: + case 0x00904: + case 0x00908: + case 0x0090c: + case 0x00910: + case 0x00914: + case 0x00918: + case 0x0091c: + serial_mm_writel(s->uart, addr, val); + break; + /* GPOUT Register */ case 0x00a00: s->gpout = val & 0xff; @@ -400,15 +425,17 @@ void malta_fpga_reset(void *opaque) malta_fpga_update_display(s); } -MaltaFPGAState *malta_fpga_init(target_phys_addr_t base) +MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env) { MaltaFPGAState *s; + CharDriverState *uart_chr; int malta; s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState)); malta = cpu_register_io_memory(0, malta_fpga_read, malta_fpga_write, s); + cpu_register_physical_memory(base, 0x100000, malta); s->display = qemu_chr_open("vc"); @@ -422,6 +449,11 @@ MaltaFPGAState *malta_fpga_init(target_phys_addr_t base) qemu_chr_printf(s->display, "+ +\r\n"); qemu_chr_printf(s->display, "+--------+\r\n"); + uart_chr = qemu_chr_open("vc"); + qemu_chr_printf(uart_chr, "CBUS UART\r\n"); + s->uart = serial_mm_init(&cpu_mips_irq_request, env, base, 3, 2, + uart_chr, 0); + malta_fpga_reset(s); qemu_register_reset(malta_fpga_reset, s); @@ -683,7 +715,7 @@ void mips_malta_init (int ram_size, int vga_ram_size, int boot_device, cpu_mips_irqctrl_init(); /* FPGA */ - malta_fpga = malta_fpga_init(0x1f000000LL); + malta_fpga = malta_fpga_init(0x1f000000LL, env); /* Interrupt controller */ isa_pic = pic_init(pic_irq_request, env); diff --git a/hw/serial.c b/hw/serial.c index a88aec17d1..ed2a857008 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -371,45 +371,45 @@ SerialState *serial_init(SetIRQFunc *set_irq, void *opaque, } /* Memory mapped interface */ -static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr) +uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr) { SerialState *s = opaque; return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF; } -static void serial_mm_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) +void serial_mm_writeb (void *opaque, + target_phys_addr_t addr, uint32_t value) { SerialState *s = opaque; serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF); } -static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr) +uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr) { SerialState *s = opaque; return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF; } -static void serial_mm_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) +void serial_mm_writew (void *opaque, + target_phys_addr_t addr, uint32_t value) { SerialState *s = opaque; serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF); } -static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr) +uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr) { SerialState *s = opaque; return serial_ioport_read(s, (addr - s->base) >> s->it_shift); } -static void serial_mm_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) +void serial_mm_writel (void *opaque, + target_phys_addr_t addr, uint32_t value) { SerialState *s = opaque; @@ -430,7 +430,8 @@ static CPUWriteMemoryFunc *serial_mm_write[] = { SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque, target_ulong base, int it_shift, - int irq, CharDriverState *chr) + int irq, CharDriverState *chr, + int ioregister) { SerialState *s; int s_io_memory; @@ -449,9 +450,11 @@ SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque, register_savevm("serial", base, 2, serial_save, serial_load, s); - s_io_memory = cpu_register_io_memory(0, serial_mm_read, - serial_mm_write, s); - cpu_register_physical_memory(base, 8 << it_shift, s_io_memory); + if (ioregister) { + s_io_memory = cpu_register_io_memory(0, serial_mm_read, + serial_mm_write, s); + cpu_register_physical_memory(base, 8 << it_shift, s_io_memory); + } s->chr = chr; qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1, serial_event, s); diff --git a/target-mips/exec.h b/target-mips/exec.h index 9816d4246a..6b32027410 100644 --- a/target-mips/exec.h +++ b/target-mips/exec.h @@ -163,7 +163,7 @@ uint32_t cpu_mips_get_random (CPUState *env); uint32_t cpu_mips_get_count (CPUState *env); void cpu_mips_store_count (CPUState *env, uint32_t value); void cpu_mips_store_compare (CPUState *env, uint32_t value); -void cpu_mips_update_irq(CPUState *env); +void cpu_mips_update_irq (CPUState *env); void cpu_mips_clock_init (CPUState *env); void cpu_mips_tlb_flush (CPUState *env, int flush_global); @@ -1035,7 +1035,14 @@ SerialState *serial_init(SetIRQFunc *set_irq, void *opaque, int base, int irq, CharDriverState *chr); SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque, target_ulong base, int it_shift, - int irq, CharDriverState *chr); + int irq, CharDriverState *chr, + int ioregister); +uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr); +void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value); +uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr); +void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value); +uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr); +void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value); /* parallel.c */ |