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-rw-r--r--hw/riscv/sifive_e.c2
-rw-r--r--hw/riscv/sifive_u.c2
-rw-r--r--hw/riscv/spike.c2
-rw-r--r--hw/riscv/virt.c2
-rw-r--r--target/riscv/cpu.h1
5 files changed, 4 insertions, 5 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 22dc526713..6fa2238185 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -88,7 +88,7 @@ static uint64_t load_kernel(const char *kernel_filename)
if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
- 0, ELF_MACHINE, 1, 0) < 0) {
+ 0, EM_RISCV, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
exit(1);
}
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 5bb495ab9a..84afed4c3b 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -74,7 +74,7 @@ static uint64_t load_kernel(const char *kernel_filename)
if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
- 0, ELF_MACHINE, 1, 0) < 0) {
+ 0, EM_RISCV, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
exit(1);
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 44eab94e17..9e18c618bf 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -64,7 +64,7 @@ static uint64_t load_kernel(const char *kernel_filename)
uint64_t kernel_entry, kernel_high;
if (load_elf_ram_sym(kernel_filename, NULL, NULL,
- &kernel_entry, NULL, &kernel_high, 0, ELF_MACHINE, 1, 0,
+ &kernel_entry, NULL, &kernel_high, 0, EM_RISCV, 1, 0,
NULL, true, htif_symbol_callback) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
exit(1);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 88b9ad5093..7ef9ba26de 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -68,7 +68,7 @@ static uint64_t load_kernel(const char *kernel_filename)
if (load_elf(kernel_filename, NULL, NULL,
&kernel_entry, NULL, &kernel_high,
- 0, ELF_MACHINE, 1, 0) < 0) {
+ 0, EM_RISCV, 1, 0) < 0) {
error_report("qemu: could not load kernel '%s'", kernel_filename);
exit(1);
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 41e06ac0f9..9871e6feb1 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -34,7 +34,6 @@
#define TCG_GUEST_DEFAULT_MO 0
-#define ELF_MACHINE EM_RISCV
#define CPUArchState struct CPURISCVState
#include "qemu-common.h"